1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
22 #include "arm_adi_v5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
117 #define ARMV8_COMMON_MAGIC 0x0A450AAA
119 /* VA to PA translation operations opc2 values*/
128 /* L210/L220 cache controller support */
129 struct armv8_l2x_cache {
134 struct armv8_cachesize {
136 /* cache dimensionning */
138 uint32_t associativity;
141 /* info for set way operation on cache */
143 uint32_t index_shift;
148 /* information about one architecture cache at any level */
149 struct armv8_arch_cache {
150 int ctype; /* cache type, CLIDR encoding */
151 struct armv8_cachesize d_u_size; /* data cache */
152 struct armv8_cachesize i_size; /* instruction cache */
155 struct armv8_cache_common {
160 struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
162 int d_u_cache_enabled;
164 /* l2 external unified cache if some */
166 int (*flush_all_data_cache)(struct target *target);
167 int (*display_cache_info)(struct command_context *cmd_ctx,
168 struct armv8_cache_common *armv8_cache);
171 struct armv8_mmu_common {
172 /* following field mmu working way */
173 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
174 uint64_t ttbr0_mask;/* masked to be used */
176 uint32_t ttbcr; /* cache for ttbcr register */
177 uint32_t ttbr_mask[2];
178 uint32_t ttbr_range[2];
180 int (*read_physical_memory)(struct target *target, target_addr_t address,
181 uint32_t size, uint32_t count, uint8_t *buffer);
182 struct armv8_cache_common armv8_cache;
183 uint32_t mmu_enabled;
186 struct armv8_common {
189 struct reg_cache *core_cache;
191 /* Core Debug Unit */
194 struct adiv5_ap *debug_ap;
196 const uint32_t *opcodes;
199 uint8_t multi_processor_system;
203 /* armv8 aarch64 need below information for page translation */
209 struct armv8_mmu_common armv8_mmu;
213 /* Direct processor core register read and writes */
214 int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
215 int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
217 /* SIMD/FPU registers read/write interface */
218 int (*read_reg_u128)(struct armv8_common *armv8, int num,
219 uint64_t *lvalue, uint64_t *hvalue);
220 int (*write_reg_u128)(struct armv8_common *armv8, int num,
221 uint64_t lvalue, uint64_t hvalue);
223 int (*examine_debug_reason)(struct target *target);
224 int (*post_debug_entry)(struct target *target);
226 void (*pre_restore_context)(struct target *target);
229 static inline struct armv8_common *
230 target_to_armv8(struct target *target)
232 return container_of(target->arch_info, struct armv8_common, arm);
235 /* register offsets from armv8.debug_base */
236 #define CPUV8_DBG_MAINID0 0xD00
237 #define CPUV8_DBG_CPUFEATURE0 0xD20
238 #define CPUV8_DBG_DBGFEATURE0 0xD28
239 #define CPUV8_DBG_MEMFEATURE0 0xD38
241 #define CPUV8_DBG_LOCKACCESS 0xFB0
242 #define CPUV8_DBG_LOCKSTATUS 0xFB4
244 #define CPUV8_DBG_EDESR 0x20
245 #define CPUV8_DBG_EDECR 0x24
246 #define CPUV8_DBG_WFAR0 0x30
247 #define CPUV8_DBG_WFAR1 0x34
248 #define CPUV8_DBG_DSCR 0x088
249 #define CPUV8_DBG_DRCR 0x090
250 #define CPUV8_DBG_PRCR 0x310
251 #define CPUV8_DBG_PRSR 0x314
253 #define CPUV8_DBG_DTRRX 0x080
254 #define CPUV8_DBG_ITR 0x084
255 #define CPUV8_DBG_SCR 0x088
256 #define CPUV8_DBG_DTRTX 0x08c
258 #define CPUV8_DBG_BVR_BASE 0x400
259 #define CPUV8_DBG_BCR_BASE 0x408
260 #define CPUV8_DBG_WVR_BASE 0x800
261 #define CPUV8_DBG_WCR_BASE 0x808
262 #define CPUV8_DBG_VCR 0x01C
264 #define CPUV8_DBG_OSLAR 0x300
266 #define CPUV8_DBG_AUTHSTATUS 0xFB8
268 #define PAGE_SIZE_4KB 0x1000
269 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
270 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
271 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
272 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
274 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
275 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
276 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
277 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
279 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
281 int armv8_arch_state(struct target *target);
282 int armv8_read_mpidr(struct armv8_common *armv8);
283 int armv8_identify_cache(struct armv8_common *armv8);
284 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
285 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
286 target_addr_t *val, int meminfo);
287 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
289 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
290 struct armv8_cache_common *armv8_cache);
292 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
294 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
301 case ARM_MODE_ABT: /* FIXME: EL3? */
302 case ARM_MODE_IRQ: /* FIXME: EL3? */
303 case ARM_MODE_FIQ: /* FIXME: EL3? */
304 case ARM_MODE_UND: /* FIXME: EL3? */
305 case ARM_MODE_SYS: /* FIXME: EL3? */
307 /* case ARM_MODE_HYP:
312 /* all Aarch64 modes */
314 return (core_mode >> 2) & 3;
318 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
319 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
321 extern const struct command_registration armv8_command_handlers[];
323 #endif /* OPENOCD_TARGET_ARMV8_H */