git.sur5r.net Git - openocd/blob - src/target/cortex_a.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  28  ***************************************************************************/
  29
  30 #ifndef CORTEX_A_H
  31 #define CORTEX_A_H
  32
  33 #include "armv7a.h"
  34
  35 #define CORTEX_A_COMMON_MAGIC 0x411fc082
  36 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
  37
  38 #define CORTEX_A5_PARTNUM 0xc05
  39 #define CORTEX_A7_PARTNUM 0xc07
  40 #define CORTEX_A8_PARTNUM 0xc08
  41 #define CORTEX_A9_PARTNUM 0xc09
  42 #define CORTEX_A15_PARTNUM 0xc0f
  43 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
  44 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
  45
  46 #define CPUDBG_CPUID    0xD00
  47 #define CPUDBG_CTYPR    0xD04
  48 #define CPUDBG_TTYPR    0xD0C
  49 #define CPUDBG_LOCKACCESS 0xFB0
  50 #define CPUDBG_LOCKSTATUS 0xFB4
  51 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
  52
  53 #define BRP_NORMAL 0
  54 #define BRP_CONTEXT 1
  55
  56 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
  57
  58 enum cortex_a_isrmasking_mode {
  59         CORTEX_A_ISRMASK_OFF,
  60         CORTEX_A_ISRMASK_ON,
  61 };
  62
  63 enum cortex_a_dacrfixup_mode {
  64         CORTEX_A_DACRFIXUP_OFF,
  65         CORTEX_A_DACRFIXUP_ON
  66 };
  67
  68 struct cortex_a_brp {
  69         int used;
  70         int type;
  71         uint32_t value;
  72         uint32_t control;
  73         uint8_t BRPn;
  74 };
  75
  76 struct cortex_a_common {
  77         int common_magic;
  78
  79         /* Context information */
  80         uint32_t cpudbg_dscr;
  81
  82         /* Saved cp15 registers */
  83         uint32_t cp15_control_reg;
  84         /* latest cp15 register value written and cpsr processor mode */
  85         uint32_t cp15_control_reg_curr;
  86         /* auxiliary control reg */
  87         uint32_t cp15_aux_control_reg;
  88         /* DACR */
  89         uint32_t cp15_dacr_reg;
  90         enum arm_mode curr_mode;
  91
  92         /* Breakpoint register pairs */
  93         int brp_num_context;
  94         int brp_num;
  95         int brp_num_available;
  96         struct cortex_a_brp *brp_list;
  97
  98         /* Use cortex_a_read_regs_through_mem for fast register reads */
  99         int fast_reg_read;
 100
 101         uint32_t cpuid;
 102         uint32_t ctypr;
 103         uint32_t ttypr;
 104         uint32_t didr;
 105
 106         enum cortex_a_isrmasking_mode isrmasking_mode;
 107         enum cortex_a_dacrfixup_mode dacrfixup_mode;
 108
 109         struct armv7a_common armv7a_common;
 110
 111 };
 112
 113 static inline struct cortex_a_common *
 114 target_to_cortex_a(struct target *target)
 115 {
 116         return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
 117 }
 118
 119 #endif /* CORTEX_A_H */