1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
31 ***************************************************************************/
36 #include "cortex_a8.h"
40 #include "target_request.h"
41 #include "target_type.h"
44 int cortex_a8_register_commands(struct command_context_s *cmd_ctx);
46 /* forward declarations */
47 int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp);
48 int cortex_a8_init_target(struct command_context_s *cmd_ctx,
49 struct target_s *target);
50 int cortex_a8_examine(struct target_s *target);
51 int cortex_a8_poll(target_t *target);
52 int cortex_a8_halt(target_t *target);
53 int cortex_a8_resume(struct target_s *target, int current, uint32_t address,
54 int handle_breakpoints, int debug_execution);
55 int cortex_a8_step(struct target_s *target, int current, uint32_t address,
56 int handle_breakpoints);
57 int cortex_a8_debug_entry(target_t *target);
58 int cortex_a8_restore_context(target_t *target);
59 int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
60 uint32_t count, uint8_t *buffer);
61 int cortex_a8_set_breakpoint(struct target_s *target,
62 breakpoint_t *breakpoint, uint8_t matchmode);
63 int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
64 int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
65 int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
66 int cortex_a8_dap_read_coreregister_u32(target_t *target,
67 uint32_t *value, int regnum);
68 int cortex_a8_dap_write_coreregister_u32(target_t *target,
69 uint32_t value, int regnum);
71 target_type_t cortexa8_target =
75 .poll = cortex_a8_poll,
76 .arch_state = armv7a_arch_state,
78 .target_request_data = NULL,
80 .halt = cortex_a8_halt,
81 .resume = cortex_a8_resume,
82 .step = cortex_a8_step,
85 .deassert_reset = NULL,
86 .soft_reset_halt = NULL,
88 // .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
89 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
91 .read_memory = cortex_a8_read_memory,
92 .write_memory = cortex_a8_write_memory,
93 .bulk_write_memory = cortex_a8_bulk_write_memory,
94 .checksum_memory = arm7_9_checksum_memory,
95 .blank_check_memory = arm7_9_blank_check_memory,
97 .run_algorithm = armv4_5_run_algorithm,
99 .add_breakpoint = cortex_a8_add_breakpoint,
100 .remove_breakpoint = cortex_a8_remove_breakpoint,
101 .add_watchpoint = NULL,
102 .remove_watchpoint = NULL,
104 .register_commands = cortex_a8_register_commands,
105 .target_create = cortex_a8_target_create,
106 .init_target = cortex_a8_init_target,
107 .examine = cortex_a8_examine,
112 * FIXME do topology discovery using the ROM; don't
113 * assume this is an OMAP3.
115 #define swjdp_memoryap 0
116 #define swjdp_debugap 1
117 #define OMAP3530_DEBUG_BASE 0x54011000
120 * Cortex-A8 Basic debug access, very low level assumes state is saved
122 int cortex_a8_init_debug_access(target_t *target)
125 # Unlocking the debug registers for modification
126 mww 0x54011FB0 0xC5ACCE55 4
128 # Clear Sticky Power Down status Bit to enable access to
129 # the registers in the Core Power Domain
131 # Check that it is cleared
133 # Now we can read Core Debug Registers at offset 0x080
135 # We can also read RAM.
141 # Set DBGEN line for hardware debug (OMAP35xx)
142 mww 0x5401d030 0x00002000
148 mww 0x54011088 0x2000
154 int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
158 /* get pointers to arch-specific information */
159 armv4_5_common_t *armv4_5 = target->arch_info;
160 armv7a_common_t *armv7a = armv4_5->arch_info;
161 swjdp_common_t *swjdp = &armv7a->swjdp_info;
163 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
166 retvalue = mem_ap_read_atomic_u32(swjdp,
167 OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
169 while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
171 mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
175 retvalue = mem_ap_read_atomic_u32(swjdp,
176 OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
178 while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
183 /**************************************************************************
184 Read core register with very few exec_opcode, fast but needs work_area.
185 This can cause problems with MMU active.
186 **************************************************************************/
187 int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
190 int retval = ERROR_OK;
191 /* get pointers to arch-specific information */
192 armv4_5_common_t *armv4_5 = target->arch_info;
193 armv7a_common_t *armv7a = armv4_5->arch_info;
194 swjdp_common_t *swjdp = &armv7a->swjdp_info;
196 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
197 cortex_a8_dap_write_coreregister_u32(target, address, 0);
198 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0));
199 dap_ap_select(swjdp, swjdp_memoryap);
200 mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
201 dap_ap_select(swjdp, swjdp_debugap);
206 int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
207 uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
210 /* get pointers to arch-specific information */
211 armv4_5_common_t *armv4_5 = target->arch_info;
212 armv7a_common_t *armv7a = armv4_5->arch_info;
213 swjdp_common_t *swjdp = &armv7a->swjdp_info;
215 cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
216 /* Move R0 to DTRTX */
217 cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
220 retval = mem_ap_read_atomic_u32(swjdp,
221 OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
226 int cortex_a8_write_cp(target_t *target, uint32_t value,
227 uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
231 /* get pointers to arch-specific information */
232 armv4_5_common_t *armv4_5 = target->arch_info;
233 armv7a_common_t *armv7a = armv4_5->arch_info;
234 swjdp_common_t *swjdp = &armv7a->swjdp_info;
236 retval = mem_ap_write_u32(swjdp,
237 OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
238 /* Move DTRRX to r0 */
239 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
241 cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, 0, 0, 0, 5, 0));
245 int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
246 uint32_t CRn, uint32_t CRm, uint32_t *value)
248 return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
251 int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
252 uint32_t CRn, uint32_t CRm, uint32_t value)
254 return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
257 int cortex_a8_dap_read_coreregister_u32(target_t *target,
258 uint32_t *value, int regnum)
260 int retval = ERROR_OK;
261 uint8_t reg = regnum&0xFF;
264 /* get pointers to arch-specific information */
265 armv4_5_common_t *armv4_5 = target->arch_info;
266 armv7a_common_t *armv7a = armv4_5->arch_info;
267 swjdp_common_t *swjdp = &armv7a->swjdp_info;
274 /* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
275 cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
279 cortex_a8_exec_opcode(target, 0xE1A0000F);
280 cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
284 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
285 cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
291 retval = mem_ap_read_atomic_u32(swjdp,
292 OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
294 while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
296 retval = mem_ap_read_atomic_u32(swjdp,
297 OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
302 int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
304 int retval = ERROR_OK;
305 uint8_t Rd = regnum&0xFF;
307 /* get pointers to arch-specific information */
308 armv4_5_common_t *armv4_5 = target->arch_info;
309 armv7a_common_t *armv7a = armv4_5->arch_info;
310 swjdp_common_t *swjdp = &armv7a->swjdp_info;
316 retval = mem_ap_write_u32(swjdp,
317 OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
321 /* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
322 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
326 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
327 cortex_a8_exec_opcode(target, 0xE1A0F000);
331 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
332 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
333 /* Execute a PrefetchFlush instruction through the ITR. */
334 cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
341 * Cortex-A8 Run control
344 int cortex_a8_poll(target_t *target)
346 int retval = ERROR_OK;
348 /* get pointers to arch-specific information */
349 armv4_5_common_t *armv4_5 = target->arch_info;
350 armv7a_common_t *armv7a = armv4_5->arch_info;
351 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
352 swjdp_common_t *swjdp = &armv7a->swjdp_info;
355 enum target_state prev_target_state = target->state;
357 uint8_t saved_apsel = dap_ap_get_select(swjdp);
358 dap_ap_select(swjdp, swjdp_debugap);
359 retval = mem_ap_read_atomic_u32(swjdp,
360 OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
361 if (retval != ERROR_OK)
363 dap_ap_select(swjdp, saved_apsel);
366 cortex_a8->cpudbg_dscr = dscr;
368 if ((dscr & 0x3) == 0x3)
370 if (prev_target_state != TARGET_HALTED)
372 /* We have a halting debug event */
373 LOG_DEBUG("Target halted");
374 target->state = TARGET_HALTED;
375 if ((prev_target_state == TARGET_RUNNING)
376 || (prev_target_state == TARGET_RESET))
378 retval = cortex_a8_debug_entry(target);
379 if (retval != ERROR_OK)
382 target_call_event_callbacks(target,
383 TARGET_EVENT_HALTED);
385 if (prev_target_state == TARGET_DEBUG_RUNNING)
389 retval = cortex_a8_debug_entry(target);
390 if (retval != ERROR_OK)
393 target_call_event_callbacks(target,
394 TARGET_EVENT_DEBUG_HALTED);
398 else if ((dscr & 0x3) == 0x2)
400 target->state = TARGET_RUNNING;
404 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
405 target->state = TARGET_UNKNOWN;
408 dap_ap_select(swjdp, saved_apsel);
413 int cortex_a8_halt(target_t *target)
415 int retval = ERROR_OK;
416 /* get pointers to arch-specific information */
417 armv4_5_common_t *armv4_5 = target->arch_info;
418 armv7a_common_t *armv7a = armv4_5->arch_info;
419 swjdp_common_t *swjdp = &armv7a->swjdp_info;
421 uint8_t saved_apsel = dap_ap_get_select(swjdp);
422 dap_ap_select(swjdp, swjdp_debugap);
424 /* Perhaps we should do a read-modify-write here */
425 retval = mem_ap_write_atomic_u32(swjdp,
426 OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
428 target->debug_reason = DBG_REASON_DBGRQ;
429 dap_ap_select(swjdp, saved_apsel);
434 int cortex_a8_resume(struct target_s *target, int current,
435 uint32_t address, int handle_breakpoints, int debug_execution)
437 /* get pointers to arch-specific information */
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 armv7a_common_t *armv7a = armv4_5->arch_info;
440 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
441 swjdp_common_t *swjdp = &armv7a->swjdp_info;
443 // breakpoint_t *breakpoint = NULL;
446 uint8_t saved_apsel = dap_ap_get_select(swjdp);
447 dap_ap_select(swjdp, swjdp_debugap);
449 if (!debug_execution)
451 target_free_all_working_areas(target);
452 // cortex_m3_enable_breakpoints(target);
453 // cortex_m3_enable_watchpoints(target);
459 /* Disable interrupts */
460 /* We disable interrupts in the PRIMASK register instead of
461 * masking with C_MASKINTS,
462 * This is probably the same issue as Cortex-M3 Errata 377493:
463 * C_MASKINTS in parallel with disabled interrupts can cause
464 * local faults to not be taken. */
465 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
466 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
467 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
469 /* Make sure we are in Thumb mode */
470 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
471 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
472 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
473 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
477 /* current = 1: continue on current pc, otherwise continue at <address> */
478 resume_pc = buf_get_u32(
479 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
480 armv4_5->core_mode, 15).value,
485 /* Make sure that the Armv7 gdb thumb fixups does not
486 * kill the return address
488 if (!(cortex_a8->cpudbg_dscr & (1 << 5)))
490 resume_pc &= 0xFFFFFFFC;
492 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
493 buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
494 armv4_5->core_mode, 15).value,
496 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
497 armv4_5->core_mode, 15).dirty = 1;
498 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
499 armv4_5->core_mode, 15).valid = 1;
501 cortex_a8_restore_context(target);
502 // arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
504 /* the front-end may request us not to handle breakpoints */
505 if (handle_breakpoints)
507 /* Single step past breakpoint at current address */
508 if ((breakpoint = breakpoint_find(target, resume_pc)))
510 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
511 cortex_m3_unset_breakpoint(target, breakpoint);
512 cortex_m3_single_step_core(target);
513 cortex_m3_set_breakpoint(target, breakpoint);
519 /* Perhaps we should do a read-modify-write here */
520 mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
522 target->debug_reason = DBG_REASON_NOTHALTED;
523 target->state = TARGET_RUNNING;
525 /* registers are now invalid */
526 armv4_5_invalidate_core_regs(target);
528 if (!debug_execution)
530 target->state = TARGET_RUNNING;
531 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
532 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
536 target->state = TARGET_DEBUG_RUNNING;
537 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
538 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
541 dap_ap_select(swjdp, saved_apsel);
546 int cortex_a8_debug_entry(target_t *target)
549 uint32_t regfile[16], pc, cpsr;
550 int retval = ERROR_OK;
551 working_area_t *regfile_working_area = NULL;
553 /* get pointers to arch-specific information */
554 armv4_5_common_t *armv4_5 = target->arch_info;
555 armv7a_common_t *armv7a = armv4_5->arch_info;
556 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
557 swjdp_common_t *swjdp = &armv7a->swjdp_info;
559 if (armv7a->pre_debug_entry)
560 armv7a->pre_debug_entry(target);
562 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
564 /* Examine debug reason */
565 switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
569 target->debug_reason = DBG_REASON_DBGRQ;
573 target->debug_reason = DBG_REASON_BREAKPOINT;
576 target->debug_reason = DBG_REASON_WATCHPOINT;
579 target->debug_reason = DBG_REASON_UNDEFINED;
583 /* Examine target state and mode */
584 dap_ap_select(swjdp, swjdp_memoryap);
585 if (cortex_a8->fast_reg_read)
586 target_alloc_working_area(target, 64, ®file_working_area);
588 /* First load register acessible through core debug port*/
589 if (!regfile_working_area)
591 for (i = 0; i <= 15; i++)
592 cortex_a8_dap_read_coreregister_u32(target,
597 cortex_a8_read_regs_through_mem(target,
598 regfile_working_area->address, regfile);
599 dap_ap_select(swjdp, swjdp_memoryap);
600 target_free_working_area(target, regfile_working_area);
603 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
605 dap_ap_select(swjdp, swjdp_debugap);
606 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
608 armv4_5->core_mode = cpsr & 0x3F;
610 for (i = 0; i <= ARM_PC; i++)
612 buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
613 armv4_5->core_mode, i).value,
615 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
616 armv4_5->core_mode, i).valid = 1;
617 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
618 armv4_5->core_mode, i).dirty = 0;
620 buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
621 armv4_5->core_mode, 16).value,
623 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
624 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
626 /* Fixup PC Resume Address */
627 /* TODO Her we should use arch->core_state */
628 if (cortex_a8->cpudbg_dscr & (1 << 5))
630 // T bit set for Thumb or ThumbEE state
631 regfile[ARM_PC] -= 4;
636 regfile[ARM_PC] -= 8;
638 buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
639 armv4_5->core_mode, ARM_PC).value,
640 0, 32, regfile[ARM_PC]);
642 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
643 .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
644 armv4_5->core_mode, 0).valid;
645 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
646 .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
647 armv4_5->core_mode, 15).valid;
650 /* TODO, Move this */
651 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
652 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
653 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
655 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
656 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
658 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
659 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
662 /* Are we in an exception handler */
663 // armv4_5->exception_number = 0;
664 if (armv7a->post_debug_entry)
665 armv7a->post_debug_entry(target);
673 void cortex_a8_post_debug_entry(target_t *target)
675 /* get pointers to arch-specific information */
676 armv4_5_common_t *armv4_5 = target->arch_info;
677 armv7a_common_t *armv7a = armv4_5->arch_info;
678 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
680 // cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
681 /* examine cp15 control reg */
682 armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
683 jtag_execute_queue();
684 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
686 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
688 uint32_t cache_type_reg;
689 /* identify caches */
690 armv7a->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
691 jtag_execute_queue();
692 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
693 armv4_5_identify_cache(cache_type_reg,
694 &armv7a->armv4_5_mmu.armv4_5_cache);
697 armv7a->armv4_5_mmu.mmu_enabled =
698 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
699 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
700 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
701 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
702 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
707 int cortex_a8_step(struct target_s *target, int current, uint32_t address,
708 int handle_breakpoints)
710 /* get pointers to arch-specific information */
711 armv4_5_common_t *armv4_5 = target->arch_info;
712 armv7a_common_t *armv7a = armv4_5->arch_info;
713 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
714 breakpoint_t *breakpoint = NULL;
715 breakpoint_t stepbreakpoint;
719 if (target->state != TARGET_HALTED)
721 LOG_WARNING("target not halted");
722 return ERROR_TARGET_NOT_HALTED;
725 /* current = 1: continue on current pc, otherwise continue at <address> */
728 buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
729 armv4_5->core_mode, ARM_PC).value,
734 address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
735 armv4_5->core_mode, ARM_PC).value,
739 /* The front-end may request us not to handle breakpoints.
740 * But since Cortex-A8 uses breakpoint for single step,
741 * we MUST handle breakpoints.
743 handle_breakpoints = 1;
744 if (handle_breakpoints) {
745 breakpoint = breakpoint_find(target,
746 buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
747 armv4_5->core_mode, 15).value,
750 cortex_a8_unset_breakpoint(target, breakpoint);
753 /* Setup single step breakpoint */
754 stepbreakpoint.address = address;
755 stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4;
756 stepbreakpoint.type = BKPT_HARD;
757 stepbreakpoint.set = 0;
759 /* Break on IVA mismatch */
760 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
762 target->debug_reason = DBG_REASON_SINGLESTEP;
764 cortex_a8_resume(target, 1, address, 0, 0);
766 while (target->state != TARGET_HALTED)
768 cortex_a8_poll(target);
771 LOG_WARNING("timeout waiting for target halt");
776 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
777 if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
780 cortex_a8_set_breakpoint(target, breakpoint, 0);
782 if (target->state != TARGET_HALTED)
783 LOG_DEBUG("target stepped");
788 int cortex_a8_restore_context(target_t *target)
793 /* get pointers to arch-specific information */
794 armv4_5_common_t *armv4_5 = target->arch_info;
795 armv7a_common_t *armv7a = armv4_5->arch_info;
799 if (armv7a->pre_restore_context)
800 armv7a->pre_restore_context(target);
802 for (i = 15; i >= 0; i--)
804 if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
805 armv4_5->core_mode, i).dirty)
807 value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
808 armv4_5->core_mode, i).value,
810 /* TODO Check return values */
811 cortex_a8_dap_write_coreregister_u32(target, value, i);
815 if (armv7a->post_restore_context)
816 armv7a->post_restore_context(target);
823 * Cortex-A8 Core register functions
826 int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
827 armv4_5_mode_t mode, uint32_t * value)
830 /* get pointers to arch-specific information */
831 armv4_5_common_t *armv4_5 = target->arch_info;
833 if ((num <= ARM_CPSR))
835 /* read a normal core register */
836 retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
838 if (retval != ERROR_OK)
840 LOG_ERROR("JTAG failure %i", retval);
841 return ERROR_JTAG_DEVICE_ERROR;
843 LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
847 return ERROR_INVALID_ARGUMENTS;
850 /* Register other than r0 - r14 uses r0 for access */
852 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
853 armv4_5->core_mode, 0).dirty =
854 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
855 armv4_5->core_mode, 0).valid;
856 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
857 armv4_5->core_mode, 15).dirty =
858 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
859 armv4_5->core_mode, 15).valid;
864 int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
865 armv4_5_mode_t mode, uint32_t value)
870 /* get pointers to arch-specific information */
871 armv4_5_common_t *armv4_5 = target->arch_info;
873 #ifdef ARMV7_GDB_HACKS
874 /* If the LR register is being modified, make sure it will put us
875 * in "thumb" mode, or an INVSTATE exception will occur. This is a
876 * hack to deal with the fact that gdb will sometimes "forge"
877 * return addresses, and doesn't set the LSB correctly (i.e., when
878 * printing expressions containing function calls, it sets LR=0.) */
884 if ((num <= ARM_CPSR))
886 retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
887 if (retval != ERROR_OK)
889 LOG_ERROR("JTAG failure %i", retval);
890 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
891 armv4_5->core_mode, num).dirty =
892 ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
893 armv4_5->core_mode, num).valid;
894 return ERROR_JTAG_DEVICE_ERROR;
896 LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
900 return ERROR_INVALID_ARGUMENTS;
907 int cortex_a8_read_core_reg(struct target_s *target, int num,
908 enum armv4_5_mode mode)
912 armv4_5_common_t *armv4_5 = target->arch_info;
913 cortex_a8_dap_read_coreregister_u32(target, &value, num);
915 if ((retval = jtag_execute_queue()) != ERROR_OK)
920 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
921 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
922 buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
923 mode, num).value, 0, 32, value);
928 int cortex_a8_write_core_reg(struct target_s *target, int num,
929 enum armv4_5_mode mode, uint32_t value)
932 armv4_5_common_t *armv4_5 = target->arch_info;
934 cortex_a8_dap_write_coreregister_u32(target, value, num);
935 if ((retval = jtag_execute_queue()) != ERROR_OK)
940 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
941 ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
948 * Cortex-A8 Breakpoint and watchpoint fuctions
951 /* Setup hardware Breakpoint Register Pair */
952 int cortex_a8_set_breakpoint(struct target_s *target,
953 breakpoint_t *breakpoint, uint8_t matchmode)
958 uint8_t byte_addr_select = 0x0F;
961 /* get pointers to arch-specific information */
962 armv4_5_common_t *armv4_5 = target->arch_info;
963 armv7a_common_t *armv7a = armv4_5->arch_info;
964 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
965 cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
969 LOG_WARNING("breakpoint already set");
973 if (breakpoint->type == BKPT_HARD)
975 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
977 if (brp_i >= cortex_a8->brp_num)
979 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
982 breakpoint->set = brp_i + 1;
983 if (breakpoint->length == 2)
985 byte_addr_select = (3 << (breakpoint->address & 0x02));
987 control = ((matchmode & 0x7) << 20)
988 | (byte_addr_select << 5)
990 brp_list[brp_i].used = 1;
991 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
992 brp_list[brp_i].control = control;
993 target_write_u32(target, OMAP3530_DEBUG_BASE
994 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
995 brp_list[brp_i].value);
996 target_write_u32(target, OMAP3530_DEBUG_BASE
997 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
998 brp_list[brp_i].control);
999 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1000 brp_list[brp_i].control,
1001 brp_list[brp_i].value);
1003 else if (breakpoint->type == BKPT_SOFT)
1006 if (breakpoint->length == 2)
1008 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1012 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1014 retval = target->type->read_memory(target,
1015 breakpoint->address & 0xFFFFFFFE,
1016 breakpoint->length, 1,
1017 breakpoint->orig_instr);
1018 if (retval != ERROR_OK)
1020 retval = target->type->write_memory(target,
1021 breakpoint->address & 0xFFFFFFFE,
1022 breakpoint->length, 1, code);
1023 if (retval != ERROR_OK)
1025 breakpoint->set = 0x11; /* Any nice value but 0 */
1031 int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1034 /* get pointers to arch-specific information */
1035 armv4_5_common_t *armv4_5 = target->arch_info;
1036 armv7a_common_t *armv7a = armv4_5->arch_info;
1037 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
1038 cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
1040 if (!breakpoint->set)
1042 LOG_WARNING("breakpoint not set");
1046 if (breakpoint->type == BKPT_HARD)
1048 int brp_i = breakpoint->set - 1;
1049 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1051 LOG_DEBUG("Invalid BRP number in breakpoint");
1054 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1055 brp_list[brp_i].control, brp_list[brp_i].value);
1056 brp_list[brp_i].used = 0;
1057 brp_list[brp_i].value = 0;
1058 brp_list[brp_i].control = 0;
1059 target_write_u32(target, OMAP3530_DEBUG_BASE
1060 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1061 brp_list[brp_i].control);
1062 target_write_u32(target, OMAP3530_DEBUG_BASE
1063 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1064 brp_list[brp_i].value);
1068 /* restore original instruction (kept in target endianness) */
1069 if (breakpoint->length == 4)
1071 retval = target->type->write_memory(target,
1072 breakpoint->address & 0xFFFFFFFE,
1073 4, 1, breakpoint->orig_instr);
1074 if (retval != ERROR_OK)
1079 retval = target->type->write_memory(target,
1080 breakpoint->address & 0xFFFFFFFE,
1081 2, 1, breakpoint->orig_instr);
1082 if (retval != ERROR_OK)
1086 breakpoint->set = 0;
1091 int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1093 /* get pointers to arch-specific information */
1094 armv4_5_common_t *armv4_5 = target->arch_info;
1095 armv7a_common_t *armv7a = armv4_5->arch_info;
1096 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
1098 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1100 LOG_INFO("no hardware breakpoint available");
1101 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1104 if (breakpoint->type == BKPT_HARD)
1105 cortex_a8->brp_num_available--;
1106 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1111 int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1113 /* get pointers to arch-specific information */
1114 armv4_5_common_t *armv4_5 = target->arch_info;
1115 armv7a_common_t *armv7a = armv4_5->arch_info;
1116 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
1119 /* It is perfectly possible to remove brakpoints while the taget is running */
1120 if (target->state != TARGET_HALTED)
1122 LOG_WARNING("target not halted");
1123 return ERROR_TARGET_NOT_HALTED;
1127 if (breakpoint->set)
1129 cortex_a8_unset_breakpoint(target, breakpoint);
1130 if (breakpoint->type == BKPT_HARD)
1131 cortex_a8->brp_num_available++ ;
1141 * Cortex-A8 Reset fuctions
1146 * Cortex-A8 Memory access
1148 * This is same Cortex M3 but we must also use the correct
1149 * ap number for every access.
1152 int cortex_a8_read_memory(struct target_s *target, uint32_t address,
1153 uint32_t size, uint32_t count, uint8_t *buffer)
1155 /* get pointers to arch-specific information */
1156 armv4_5_common_t *armv4_5 = target->arch_info;
1157 armv7a_common_t *armv7a = armv4_5->arch_info;
1158 swjdp_common_t *swjdp = &armv7a->swjdp_info;
1160 int retval = ERROR_OK;
1162 /* sanitize arguments */
1163 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1164 return ERROR_INVALID_ARGUMENTS;
1166 /* cortex_a8 handles unaligned memory access */
1168 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1173 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1176 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1179 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1182 LOG_ERROR("BUG: we shouldn't get here");
1189 int cortex_a8_write_memory(struct target_s *target, uint32_t address,
1190 uint32_t size, uint32_t count, uint8_t *buffer)
1192 /* get pointers to arch-specific information */
1193 armv4_5_common_t *armv4_5 = target->arch_info;
1194 armv7a_common_t *armv7a = armv4_5->arch_info;
1195 swjdp_common_t *swjdp = &armv7a->swjdp_info;
1199 /* sanitize arguments */
1200 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1201 return ERROR_INVALID_ARGUMENTS;
1203 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1208 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1211 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1214 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1217 LOG_ERROR("BUG: we shouldn't get here");
1224 int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
1225 uint32_t count, uint8_t *buffer)
1227 return cortex_a8_write_memory(target, address, 4, count, buffer);
1231 int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
1236 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1237 *ctrl = (uint8_t)dcrdr;
1238 *value = (uint8_t)(dcrdr >> 8);
1240 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1242 /* write ack back to software dcc register
1243 * signify we have read data */
1244 if (dcrdr & (1 << 0))
1247 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1254 int cortex_a8_handle_target_request(void *priv)
1256 target_t *target = priv;
1257 if (!target->type->examined)
1259 armv4_5_common_t *armv4_5 = target->arch_info;
1260 armv7a_common_t *armv7a = armv4_5->arch_info;
1261 swjdp_common_t *swjdp = &armv7a->swjdp_info;
1264 if (!target->dbg_msg_enabled)
1267 if (target->state == TARGET_RUNNING)
1272 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1274 /* check if we have data */
1275 if (ctrl & (1 << 0))
1279 /* we assume target is quick enough */
1281 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1282 request |= (data << 8);
1283 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1284 request |= (data << 16);
1285 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1286 request |= (data << 24);
1287 target_request(target, request);
1295 * Cortex-A8 target information and configuration
1298 int cortex_a8_examine(struct target_s *target)
1300 /* get pointers to arch-specific information */
1301 armv4_5_common_t *armv4_5 = target->arch_info;
1302 armv7a_common_t *armv7a = armv4_5->arch_info;
1303 cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
1304 swjdp_common_t *swjdp = &armv7a->swjdp_info;
1308 int retval = ERROR_OK;
1309 uint32_t didr, ctypr, ttypr, cpuid;
1313 /* We do one extra read to ensure DAP is configured,
1314 * we call ahbap_debugport_init(swjdp) instead
1316 ahbap_debugport_init(swjdp);
1317 mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid);
1318 if ((retval = mem_ap_read_atomic_u32(swjdp,
1319 OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1321 LOG_DEBUG("Examine failed");
1325 if ((retval = mem_ap_read_atomic_u32(swjdp,
1326 OMAP3530_DEBUG_BASE + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1328 LOG_DEBUG("Examine failed");
1332 if ((retval = mem_ap_read_atomic_u32(swjdp,
1333 OMAP3530_DEBUG_BASE + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1335 LOG_DEBUG("Examine failed");
1339 if ((retval = mem_ap_read_atomic_u32(swjdp,
1340 OMAP3530_DEBUG_BASE + CPUDBG_DIDR, &didr)) != ERROR_OK)
1342 LOG_DEBUG("Examine failed");
1346 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1347 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1348 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1349 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1351 /* Setup Breakpoint Register Pairs */
1352 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1353 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1354 cortex_a8->brp_num_available = cortex_a8->brp_num;
1355 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(cortex_a8_brp_t));
1356 // cortex_a8->brb_enabled = ????;
1357 for (i = 0; i < cortex_a8->brp_num; i++)
1359 cortex_a8->brp_list[i].used = 0;
1360 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1361 cortex_a8->brp_list[i].type = BRP_NORMAL;
1363 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1364 cortex_a8->brp_list[i].value = 0;
1365 cortex_a8->brp_list[i].control = 0;
1366 cortex_a8->brp_list[i].BRPn = i;
1369 /* Setup Watchpoint Register Pairs */
1370 cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
1371 cortex_a8->wrp_num_available = cortex_a8->wrp_num;
1372 cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(cortex_a8_wrp_t));
1373 for (i = 0; i < cortex_a8->wrp_num; i++)
1375 cortex_a8->wrp_list[i].used = 0;
1376 cortex_a8->wrp_list[i].type = 0;
1377 cortex_a8->wrp_list[i].value = 0;
1378 cortex_a8->wrp_list[i].control = 0;
1379 cortex_a8->wrp_list[i].WRPn = i;
1381 LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
1382 cortex_a8->brp_num , cortex_a8->wrp_num);
1384 target->type->examined = 1;
1390 * Cortex-A8 target creation and initialization
1393 void cortex_a8_build_reg_cache(target_t *target)
1395 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1396 /* get pointers to arch-specific information */
1397 armv4_5_common_t *armv4_5 = target->arch_info;
1399 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
1400 armv4_5->core_cache = (*cache_p);
1404 int cortex_a8_init_target(struct command_context_s *cmd_ctx,
1405 struct target_s *target)
1407 cortex_a8_build_reg_cache(target);
1411 int cortex_a8_init_arch_info(target_t *target,
1412 cortex_a8_common_t *cortex_a8, jtag_tap_t *tap)
1414 armv4_5_common_t *armv4_5;
1415 armv7a_common_t *armv7a;
1417 armv7a = &cortex_a8->armv7a_common;
1418 armv4_5 = &armv7a->armv4_5_common;
1419 swjdp_common_t *swjdp = &armv7a->swjdp_info;
1421 /* Setup cortex_a8_common_t */
1422 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1423 cortex_a8->arch_info = NULL;
1424 armv7a->arch_info = cortex_a8;
1425 armv4_5->arch_info = armv7a;
1427 armv4_5_init_arch_info(target, armv4_5);
1429 /* prepare JTAG information for the new target */
1430 cortex_a8->jtag_info.tap = tap;
1431 cortex_a8->jtag_info.scann_size = 4;
1433 swjdp->dp_select_value = -1;
1434 swjdp->ap_csw_value = -1;
1435 swjdp->ap_tar_value = -1;
1436 swjdp->jtag_info = &cortex_a8->jtag_info;
1437 swjdp->memaccess_tck = 80;
1439 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1440 swjdp->tar_autoincr_block = (1 << 10);
1442 cortex_a8->fast_reg_read = 0;
1445 /* register arch-specific functions */
1446 armv7a->examine_debug_reason = NULL;
1448 armv7a->pre_debug_entry = NULL;
1449 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1451 armv7a->pre_restore_context = NULL;
1452 armv7a->post_restore_context = NULL;
1453 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1454 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1455 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1456 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1457 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1458 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1459 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1460 armv7a->armv4_5_mmu.mmu_enabled = 0;
1461 armv7a->read_cp15 = cortex_a8_read_cp15;
1462 armv7a->write_cp15 = cortex_a8_write_cp15;
1465 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1467 armv4_5->read_core_reg = cortex_a8_read_core_reg;
1468 armv4_5->write_core_reg = cortex_a8_write_core_reg;
1469 // armv4_5->full_context = arm7_9_full_context;
1471 // armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
1472 // armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
1473 // armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
1474 // armv4_5->write_core_reg = armv4_5_write_core_reg;
1476 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1481 int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
1483 cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t));
1485 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1490 static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx,
1491 char *cmd, char **args, int argc)
1493 target_t *target = get_current_target(cmd_ctx);
1494 armv4_5_common_t *armv4_5 = target->arch_info;
1495 armv7a_common_t *armv7a = armv4_5->arch_info;
1497 return armv4_5_handle_cache_info_command(cmd_ctx,
1498 &armv7a->armv4_5_mmu.armv4_5_cache);
1502 int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
1504 command_t *cortex_a8_cmd;
1505 int retval = ERROR_OK;
1507 armv4_5_register_commands(cmd_ctx);
1508 armv7a_register_commands(cmd_ctx);
1510 cortex_a8_cmd = register_command(cmd_ctx, NULL, "cortex_a8",
1512 "cortex_a8 specific commands");
1514 register_command(cmd_ctx, cortex_a8_cmd, "cache_info",
1515 cortex_a8_handle_cache_info_command, COMMAND_EXEC,
1516 "display information about target caches");