git.sur5r.net Git - openocd/blob - src/target/cortex_m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "jtag/interface.h"
  35 #include "breakpoints.h"
  36 #include "cortex_m.h"
  37 #include "target_request.h"
  38 #include "target_type.h"
  39 #include "arm_disassembler.h"
  40 #include "register.h"
  41 #include "arm_opcodes.h"
  42 #include "arm_semihosting.h"
  43 #include <helper/time_support.h>
  44
  45 /* NOTE:  most of this should work fine for the Cortex-M1 and
  46  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  47  * Some differences:  M0/M1 doesn't have FBP remapping or the
  48  * DWT tracing/profiling support.  (So the cycle counter will
  49  * not be usable; the other stuff isn't currently used here.)
  50  *
  51  * Although there are some workarounds for errata seen only in r0p0
  52  * silicon, such old parts are hard to find and thus not much tested
  53  * any longer.
  54  */
  55
  56 /**
  57  * Returns the type of a break point required by address location
  58  */
  59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
  60
  61 /* forward declarations */
  62 static int cortex_m_store_core_reg_u32(struct target *target,
  63                 uint32_t num, uint32_t value);
  64 static void cortex_m_dwt_free(struct target *target);
  65
  66 static int cortexm_dap_read_coreregister_u32(struct target *target,
  67         uint32_t *value, int regnum)
  68 {
  69         struct armv7m_common *armv7m = target_to_armv7m(target);
  70         int retval;
  71         uint32_t dcrdr;
  72
  73         /* because the DCB_DCRDR is used for the emulated dcc channel
  74          * we have to save/restore the DCB_DCRDR when used */
  75         if (target->dbg_msg_enabled) {
  76                 retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
  77                 if (retval != ERROR_OK)
  78                         return retval;
  79         }
  80
  81         retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
  82         if (retval != ERROR_OK)
  83                 return retval;
  84
  85         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
  86         if (retval != ERROR_OK)
  87                 return retval;
  88
  89         if (target->dbg_msg_enabled) {
  90                 /* restore DCB_DCRDR - this needs to be in a separate
  91                  * transaction otherwise the emulated DCC channel breaks */
  92                 if (retval == ERROR_OK)
  93                         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
  94         }
  95
  96         return retval;
  97 }
  98
  99 static int cortexm_dap_write_coreregister_u32(struct target *target,
 100         uint32_t value, int regnum)
 101 {
 102         struct armv7m_common *armv7m = target_to_armv7m(target);
 103         int retval;
 104         uint32_t dcrdr;
 105
 106         /* because the DCB_DCRDR is used for the emulated dcc channel
 107          * we have to save/restore the DCB_DCRDR when used */
 108         if (target->dbg_msg_enabled) {
 109                 retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 110                 if (retval != ERROR_OK)
 111                         return retval;
 112         }
 113
 114         retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
 115         if (retval != ERROR_OK)
 116                 return retval;
 117
 118         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
 119         if (retval != ERROR_OK)
 120                 return retval;
 121
 122         if (target->dbg_msg_enabled) {
 123                 /* restore DCB_DCRDR - this needs to be in a seperate
 124                  * transaction otherwise the emulated DCC channel breaks */
 125                 if (retval == ERROR_OK)
 126                         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 127         }
 128
 129         return retval;
 130 }
 131
 132 static int cortex_m_write_debug_halt_mask(struct target *target,
 133         uint32_t mask_on, uint32_t mask_off)
 134 {
 135         struct cortex_m_common *cortex_m = target_to_cm(target);
 136         struct armv7m_common *armv7m = &cortex_m->armv7m;
 137
 138         /* mask off status bits */
 139         cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 140         /* create new register mask */
 141         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 142
 143         return mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 144 }
 145
 146 static int cortex_m_clear_halt(struct target *target)
 147 {
 148         struct cortex_m_common *cortex_m = target_to_cm(target);
 149         struct armv7m_common *armv7m = &cortex_m->armv7m;
 150         int retval;
 151
 152         /* clear step if any */
 153         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 154
 155         /* Read Debug Fault Status Register */
 156         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
 157         if (retval != ERROR_OK)
 158                 return retval;
 159
 160         /* Clear Debug Fault Status */
 161         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 162         if (retval != ERROR_OK)
 163                 return retval;
 164         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 165
 166         return ERROR_OK;
 167 }
 168
 169 static int cortex_m_single_step_core(struct target *target)
 170 {
 171         struct cortex_m_common *cortex_m = target_to_cm(target);
 172         struct armv7m_common *armv7m = &cortex_m->armv7m;
 173         uint32_t dhcsr_save;
 174         int retval;
 175
 176         /* backup dhcsr reg */
 177         dhcsr_save = cortex_m->dcb_dhcsr;
 178
 179         /* Mask interrupts before clearing halt, if done already.  This avoids
 180          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 181          * HALT can put the core into an unknown state.
 182          */
 183         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 184                 retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 185                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 186                 if (retval != ERROR_OK)
 187                         return retval;
 188         }
 189         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 190                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 191         if (retval != ERROR_OK)
 192                 return retval;
 193         LOG_DEBUG(" ");
 194
 195         /* restore dhcsr reg */
 196         cortex_m->dcb_dhcsr = dhcsr_save;
 197         cortex_m_clear_halt(target);
 198
 199         return ERROR_OK;
 200 }
 201
 202 static int cortex_m_enable_fpb(struct target *target)
 203 {
 204         int retval = target_write_u32(target, FP_CTRL, 3);
 205         if (retval != ERROR_OK)
 206                 return retval;
 207
 208         /* check the fpb is actually enabled */
 209         uint32_t fpctrl;
 210         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 211         if (retval != ERROR_OK)
 212                 return retval;
 213
 214         if (fpctrl & 1)
 215                 return ERROR_OK;
 216
 217         return ERROR_FAIL;
 218 }
 219
 220 static int cortex_m_endreset_event(struct target *target)
 221 {
 222         int i;
 223         int retval;
 224         uint32_t dcb_demcr;
 225         struct cortex_m_common *cortex_m = target_to_cm(target);
 226         struct armv7m_common *armv7m = &cortex_m->armv7m;
 227         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 228         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 229         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 230
 231         /* REVISIT The four debug monitor bits are currently ignored... */
 232         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 233         if (retval != ERROR_OK)
 234                 return retval;
 235         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 236
 237         /* this register is used for emulated dcc channel */
 238         retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
 239         if (retval != ERROR_OK)
 240                 return retval;
 241
 242         /* Enable debug requests */
 243         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 244         if (retval != ERROR_OK)
 245                 return retval;
 246         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 247                 retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 248                 if (retval != ERROR_OK)
 249                         return retval;
 250         }
 251
 252         /* clear any interrupt masking */
 253         cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
 254
 255         /* Enable features controlled by ITM and DWT blocks, and catch only
 256          * the vectors we were told to pay attention to.
 257          *
 258          * Target firmware is responsible for all fault handling policy
 259          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 260          * or manual updates to the NVIC SHCSR and CCR registers.
 261          */
 262         retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         /* Paranoia: evidently some (early?) chips don't preserve all the
 267          * debug state (including FBP, DWT, etc) across reset...
 268          */
 269
 270         /* Enable FPB */
 271         retval = cortex_m_enable_fpb(target);
 272         if (retval != ERROR_OK) {
 273                 LOG_ERROR("Failed to enable the FPB");
 274                 return retval;
 275         }
 276
 277         cortex_m->fpb_enabled = 1;
 278
 279         /* Restore FPB registers */
 280         for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 281                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 282                 if (retval != ERROR_OK)
 283                         return retval;
 284         }
 285
 286         /* Restore DWT registers */
 287         for (i = 0; i < cortex_m->dwt_num_comp; i++) {
 288                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 289                                 dwt_list[i].comp);
 290                 if (retval != ERROR_OK)
 291                         return retval;
 292                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 293                                 dwt_list[i].mask);
 294                 if (retval != ERROR_OK)
 295                         return retval;
 296                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 297                                 dwt_list[i].function);
 298                 if (retval != ERROR_OK)
 299                         return retval;
 300         }
 301         retval = dap_run(swjdp);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304
 305         register_cache_invalidate(armv7m->arm.core_cache);
 306
 307         /* make sure we have latest dhcsr flags */
 308         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 309
 310         return retval;
 311 }
 312
 313 static int cortex_m_examine_debug_reason(struct target *target)
 314 {
 315         struct cortex_m_common *cortex_m = target_to_cm(target);
 316
 317         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 318          * only check the debug reason if we don't know it already */
 319
 320         if ((target->debug_reason != DBG_REASON_DBGRQ)
 321                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 322                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 323                         target->debug_reason = DBG_REASON_BREAKPOINT;
 324                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 325                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 326                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 327                         target->debug_reason = DBG_REASON_WATCHPOINT;
 328                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 329                         target->debug_reason = DBG_REASON_BREAKPOINT;
 330                 else    /* EXTERNAL, HALTED */
 331                         target->debug_reason = DBG_REASON_UNDEFINED;
 332         }
 333
 334         return ERROR_OK;
 335 }
 336
 337 static int cortex_m_examine_exception_reason(struct target *target)
 338 {
 339         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 340         struct armv7m_common *armv7m = target_to_armv7m(target);
 341         struct adiv5_dap *swjdp = armv7m->arm.dap;
 342         int retval;
 343
 344         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
 345         if (retval != ERROR_OK)
 346                 return retval;
 347         switch (armv7m->exception_number) {
 348                 case 2: /* NMI */
 349                         break;
 350                 case 3: /* Hard Fault */
 351                         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
 352                         if (retval != ERROR_OK)
 353                                 return retval;
 354                         if (except_sr & 0x40000000) {
 355                                 retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
 356                                 if (retval != ERROR_OK)
 357                                         return retval;
 358                         }
 359                         break;
 360                 case 4: /* Memory Management */
 361                         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 362                         if (retval != ERROR_OK)
 363                                 return retval;
 364                         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
 365                         if (retval != ERROR_OK)
 366                                 return retval;
 367                         break;
 368                 case 5: /* Bus Fault */
 369                         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 370                         if (retval != ERROR_OK)
 371                                 return retval;
 372                         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
 373                         if (retval != ERROR_OK)
 374                                 return retval;
 375                         break;
 376                 case 6: /* Usage Fault */
 377                         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 378                         if (retval != ERROR_OK)
 379                                 return retval;
 380                         break;
 381                 case 11:        /* SVCall */
 382                         break;
 383                 case 12:        /* Debug Monitor */
 384                         retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
 385                         if (retval != ERROR_OK)
 386                                 return retval;
 387                         break;
 388                 case 14:        /* PendSV */
 389                         break;
 390                 case 15:        /* SysTick */
 391                         break;
 392                 default:
 393                         except_sr = 0;
 394                         break;
 395         }
 396         retval = dap_run(swjdp);
 397         if (retval == ERROR_OK)
 398                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 399                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 400                         armv7m_exception_string(armv7m->exception_number),
 401                         shcsr, except_sr, cfsr, except_ar);
 402         return retval;
 403 }
 404
 405 static int cortex_m_debug_entry(struct target *target)
 406 {
 407         int i;
 408         uint32_t xPSR;
 409         int retval;
 410         struct cortex_m_common *cortex_m = target_to_cm(target);
 411         struct armv7m_common *armv7m = &cortex_m->armv7m;
 412         struct arm *arm = &armv7m->arm;
 413         struct reg *r;
 414
 415         LOG_DEBUG(" ");
 416
 417         cortex_m_clear_halt(target);
 418         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 419         if (retval != ERROR_OK)
 420                 return retval;
 421
 422         retval = armv7m->examine_debug_reason(target);
 423         if (retval != ERROR_OK)
 424                 return retval;
 425
 426         /* Examine target state and mode
 427          * First load register accessible through core debug port */
 428         int num_regs = arm->core_cache->num_regs;
 429
 430         for (i = 0; i < num_regs; i++) {
 431                 r = &armv7m->arm.core_cache->reg_list[i];
 432                 if (!r->valid)
 433                         arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 434         }
 435
 436         r = arm->cpsr;
 437         xPSR = buf_get_u32(r->value, 0, 32);
 438
 439         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 440         if (xPSR & 0xf00) {
 441                 r->dirty = r->valid;
 442                 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
 443         }
 444
 445         /* Are we in an exception handler */
 446         if (xPSR & 0x1FF) {
 447                 armv7m->exception_number = (xPSR & 0x1FF);
 448
 449                 arm->core_mode = ARM_MODE_HANDLER;
 450                 arm->map = armv7m_msp_reg_map;
 451         } else {
 452                 unsigned control = buf_get_u32(arm->core_cache
 453                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 454
 455                 /* is this thread privileged? */
 456                 arm->core_mode = control & 1
 457                         ? ARM_MODE_USER_THREAD
 458                         : ARM_MODE_THREAD;
 459
 460                 /* which stack is it using? */
 461                 if (control & 2)
 462                         arm->map = armv7m_psp_reg_map;
 463                 else
 464                         arm->map = armv7m_msp_reg_map;
 465
 466                 armv7m->exception_number = 0;
 467         }
 468
 469         if (armv7m->exception_number)
 470                 cortex_m_examine_exception_reason(target);
 471
 472         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 473                 arm_mode_name(arm->core_mode),
 474                 buf_get_u32(arm->pc->value, 0, 32),
 475                 target_state_name(target));
 476
 477         if (armv7m->post_debug_entry) {
 478                 retval = armv7m->post_debug_entry(target);
 479                 if (retval != ERROR_OK)
 480                         return retval;
 481         }
 482
 483         return ERROR_OK;
 484 }
 485
 486 static int cortex_m_poll(struct target *target)
 487 {
 488         int detected_failure = ERROR_OK;
 489         int retval = ERROR_OK;
 490         enum target_state prev_target_state = target->state;
 491         struct cortex_m_common *cortex_m = target_to_cm(target);
 492         struct armv7m_common *armv7m = &cortex_m->armv7m;
 493
 494         /* Read from Debug Halting Control and Status Register */
 495         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 496         if (retval != ERROR_OK) {
 497                 target->state = TARGET_UNKNOWN;
 498                 return retval;
 499         }
 500
 501         /* Recover from lockup.  See ARMv7-M architecture spec,
 502          * section B1.5.15 "Unrecoverable exception cases".
 503          */
 504         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 505                 LOG_ERROR("%s -- clearing lockup after double fault",
 506                         target_name(target));
 507                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 508                 target->debug_reason = DBG_REASON_DBGRQ;
 509
 510                 /* We have to execute the rest (the "finally" equivalent, but
 511                  * still throw this exception again).
 512                  */
 513                 detected_failure = ERROR_FAIL;
 514
 515                 /* refresh status bits */
 516                 retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 517                 if (retval != ERROR_OK)
 518                         return retval;
 519         }
 520
 521         if (cortex_m->dcb_dhcsr & S_RESET_ST) {
 522                 target->state = TARGET_RESET;
 523                 return ERROR_OK;
 524         }
 525
 526         if (target->state == TARGET_RESET) {
 527                 /* Cannot switch context while running so endreset is
 528                  * called with target->state == TARGET_RESET
 529                  */
 530                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 531                         cortex_m->dcb_dhcsr);
 532                 retval = cortex_m_endreset_event(target);
 533                 if (retval != ERROR_OK) {
 534                         target->state = TARGET_UNKNOWN;
 535                         return retval;
 536                 }
 537                 target->state = TARGET_RUNNING;
 538                 prev_target_state = TARGET_RUNNING;
 539         }
 540
 541         if (cortex_m->dcb_dhcsr & S_HALT) {
 542                 target->state = TARGET_HALTED;
 543
 544                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 545                         retval = cortex_m_debug_entry(target);
 546                         if (retval != ERROR_OK)
 547                                 return retval;
 548
 549                         if (arm_semihosting(target, &retval) != 0)
 550                                 return retval;
 551
 552                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 553                 }
 554                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 555                         LOG_DEBUG(" ");
 556                         retval = cortex_m_debug_entry(target);
 557                         if (retval != ERROR_OK)
 558                                 return retval;
 559
 560                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 561                 }
 562         }
 563
 564         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 565          * How best to model low power modes?
 566          */
 567
 568         if (target->state == TARGET_UNKNOWN) {
 569                 /* check if processor is retiring instructions */
 570                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
 571                         target->state = TARGET_RUNNING;
 572                         retval = ERROR_OK;
 573                 }
 574         }
 575
 576         /* Did we detect a failure condition that we cleared? */
 577         if (detected_failure != ERROR_OK)
 578                 retval = detected_failure;
 579         return retval;
 580 }
 581
 582 static int cortex_m_halt(struct target *target)
 583 {
 584         LOG_DEBUG("target->state: %s",
 585                 target_state_name(target));
 586
 587         if (target->state == TARGET_HALTED) {
 588                 LOG_DEBUG("target was already halted");
 589                 return ERROR_OK;
 590         }
 591
 592         if (target->state == TARGET_UNKNOWN)
 593                 LOG_WARNING("target was in unknown state when halt was requested");
 594
 595         if (target->state == TARGET_RESET) {
 596                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 597                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 598                         return ERROR_TARGET_FAILURE;
 599                 } else {
 600                         /* we came here in a reset_halt or reset_init sequence
 601                          * debug entry was already prepared in cortex_m3_assert_reset()
 602                          */
 603                         target->debug_reason = DBG_REASON_DBGRQ;
 604
 605                         return ERROR_OK;
 606                 }
 607         }
 608
 609         /* Write to Debug Halting Control and Status Register */
 610         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 611
 612         target->debug_reason = DBG_REASON_DBGRQ;
 613
 614         return ERROR_OK;
 615 }
 616
 617 static int cortex_m_soft_reset_halt(struct target *target)
 618 {
 619         struct cortex_m_common *cortex_m = target_to_cm(target);
 620         struct armv7m_common *armv7m = &cortex_m->armv7m;
 621         uint32_t dcb_dhcsr = 0;
 622         int retval, timeout = 0;
 623
 624         /* soft_reset_halt is deprecated on cortex_m as the same functionality
 625          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
 626          * As this reset only used VC_CORERESET it would only ever reset the cortex_m
 627          * core, not the peripherals */
 628         LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
 629
 630         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 631         retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR,
 632                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 633         if (retval != ERROR_OK)
 634                 return retval;
 635
 636         /* Request a core-only reset */
 637         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
 638                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 639         if (retval != ERROR_OK)
 640                 return retval;
 641         target->state = TARGET_RESET;
 642
 643         /* registers are now invalid */
 644         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 645
 646         while (timeout < 100) {
 647                 retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
 648                 if (retval == ERROR_OK) {
 649                         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
 650                                         &cortex_m->nvic_dfsr);
 651                         if (retval != ERROR_OK)
 652                                 return retval;
 653                         if ((dcb_dhcsr & S_HALT)
 654                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
 655                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 656                                         "DFSR 0x%08x",
 657                                         (unsigned) dcb_dhcsr,
 658                                         (unsigned) cortex_m->nvic_dfsr);
 659                                 cortex_m_poll(target);
 660                                 /* FIXME restore user's vector catch config */
 661                                 return ERROR_OK;
 662                         } else
 663                                 LOG_DEBUG("waiting for system reset-halt, "
 664                                         "DHCSR 0x%08x, %d ms",
 665                                         (unsigned) dcb_dhcsr, timeout);
 666                 }
 667                 timeout++;
 668                 alive_sleep(1);
 669         }
 670
 671         return ERROR_OK;
 672 }
 673
 674 void cortex_m_enable_breakpoints(struct target *target)
 675 {
 676         struct breakpoint *breakpoint = target->breakpoints;
 677
 678         /* set any pending breakpoints */
 679         while (breakpoint) {
 680                 if (!breakpoint->set)
 681                         cortex_m_set_breakpoint(target, breakpoint);
 682                 breakpoint = breakpoint->next;
 683         }
 684 }
 685
 686 static int cortex_m_resume(struct target *target, int current,
 687         uint32_t address, int handle_breakpoints, int debug_execution)
 688 {
 689         struct armv7m_common *armv7m = target_to_armv7m(target);
 690         struct breakpoint *breakpoint = NULL;
 691         uint32_t resume_pc;
 692         struct reg *r;
 693
 694         if (target->state != TARGET_HALTED) {
 695                 LOG_WARNING("target not halted");
 696                 return ERROR_TARGET_NOT_HALTED;
 697         }
 698
 699         if (!debug_execution) {
 700                 target_free_all_working_areas(target);
 701                 cortex_m_enable_breakpoints(target);
 702                 cortex_m_enable_watchpoints(target);
 703         }
 704
 705         if (debug_execution) {
 706                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
 707
 708                 /* Disable interrupts */
 709                 /* We disable interrupts in the PRIMASK register instead of
 710                  * masking with C_MASKINTS.  This is probably the same issue
 711                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 712                  * in parallel with disabled interrupts can cause local faults
 713                  * to not be taken.
 714                  *
 715                  * REVISIT this clearly breaks non-debug execution, since the
 716                  * PRIMASK register state isn't saved/restored...  workaround
 717                  * by never resuming app code after debug execution.
 718                  */
 719                 buf_set_u32(r->value, 0, 1, 1);
 720                 r->dirty = true;
 721                 r->valid = true;
 722
 723                 /* Make sure we are in Thumb mode */
 724                 r = armv7m->arm.cpsr;
 725                 buf_set_u32(r->value, 24, 1, 1);
 726                 r->dirty = true;
 727                 r->valid = true;
 728         }
 729
 730         /* current = 1: continue on current pc, otherwise continue at <address> */
 731         r = armv7m->arm.pc;
 732         if (!current) {
 733                 buf_set_u32(r->value, 0, 32, address);
 734                 r->dirty = true;
 735                 r->valid = true;
 736         }
 737
 738         /* if we halted last time due to a bkpt instruction
 739          * then we have to manually step over it, otherwise
 740          * the core will break again */
 741
 742         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 743                 && !debug_execution)
 744                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 745
 746         resume_pc = buf_get_u32(r->value, 0, 32);
 747
 748         armv7m_restore_context(target);
 749
 750         /* the front-end may request us not to handle breakpoints */
 751         if (handle_breakpoints) {
 752                 /* Single step past breakpoint at current address */
 753                 breakpoint = breakpoint_find(target, resume_pc);
 754                 if (breakpoint) {
 755                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")",
 756                                 breakpoint->address,
 757                                 breakpoint->unique_id);
 758                         cortex_m_unset_breakpoint(target, breakpoint);
 759                         cortex_m_single_step_core(target);
 760                         cortex_m_set_breakpoint(target, breakpoint);
 761                 }
 762         }
 763
 764         /* Restart core */
 765         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 766
 767         target->debug_reason = DBG_REASON_NOTHALTED;
 768
 769         /* registers are now invalid */
 770         register_cache_invalidate(armv7m->arm.core_cache);
 771
 772         if (!debug_execution) {
 773                 target->state = TARGET_RUNNING;
 774                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 775                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 776         } else {
 777                 target->state = TARGET_DEBUG_RUNNING;
 778                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 779                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 780         }
 781
 782         return ERROR_OK;
 783 }
 784
 785 /* int irqstepcount = 0; */
 786 static int cortex_m_step(struct target *target, int current,
 787         uint32_t address, int handle_breakpoints)
 788 {
 789         struct cortex_m_common *cortex_m = target_to_cm(target);
 790         struct armv7m_common *armv7m = &cortex_m->armv7m;
 791         struct breakpoint *breakpoint = NULL;
 792         struct reg *pc = armv7m->arm.pc;
 793         bool bkpt_inst_found = false;
 794         int retval;
 795         bool isr_timed_out = false;
 796
 797         if (target->state != TARGET_HALTED) {
 798                 LOG_WARNING("target not halted");
 799                 return ERROR_TARGET_NOT_HALTED;
 800         }
 801
 802         /* current = 1: continue on current pc, otherwise continue at <address> */
 803         if (!current)
 804                 buf_set_u32(pc->value, 0, 32, address);
 805
 806         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 807
 808         /* the front-end may request us not to handle breakpoints */
 809         if (handle_breakpoints) {
 810                 breakpoint = breakpoint_find(target, pc_value);
 811                 if (breakpoint)
 812                         cortex_m_unset_breakpoint(target, breakpoint);
 813         }
 814
 815         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 816
 817         target->debug_reason = DBG_REASON_SINGLESTEP;
 818
 819         armv7m_restore_context(target);
 820
 821         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 822
 823         /* if no bkpt instruction is found at pc then we can perform
 824          * a normal step, otherwise we have to manually step over the bkpt
 825          * instruction - as such simulate a step */
 826         if (bkpt_inst_found == false) {
 827                 /* Automatic ISR masking mode off: Just step over the next instruction */
 828                 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
 829                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 830                 else {
 831                         /* Process interrupts during stepping in a way they don't interfere
 832                          * debugging.
 833                          *
 834                          * Principle:
 835                          *
 836                          * Set a temporary break point at the current pc and let the core run
 837                          * with interrupts enabled. Pending interrupts get served and we run
 838                          * into the breakpoint again afterwards. Then we step over the next
 839                          * instruction with interrupts disabled.
 840                          *
 841                          * If the pending interrupts don't complete within time, we leave the
 842                          * core running. This may happen if the interrupts trigger faster
 843                          * than the core can process them or the handler doesn't return.
 844                          *
 845                          * If no more breakpoints are available we simply do a step with
 846                          * interrupts enabled.
 847                          *
 848                          */
 849
 850                         /* 2012-09-29 ph
 851                          *
 852                          * If a break point is already set on the lower half word then a break point on
 853                          * the upper half word will not break again when the core is restarted. So we
 854                          * just step over the instruction with interrupts disabled.
 855                          *
 856                          * The documentation has no information about this, it was found by observation
 857                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
 858                          * suffer from this problem.
 859                          *
 860                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
 861                          * address has it always cleared. The former is done to indicate thumb mode
 862                          * to gdb.
 863                          *
 864                          */
 865                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
 866                                 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 867                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 868                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 869                                 /* Re-enable interrupts */
 870                                 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 871                         }
 872                         else {
 873
 874                                 /* Set a temporary break point */
 875                                 if (breakpoint)
 876                                         retval = cortex_m_set_breakpoint(target, breakpoint);
 877                                 else
 878                                         retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
 879                                 bool tmp_bp_set = (retval == ERROR_OK);
 880
 881                                 /* No more breakpoints left, just do a step */
 882                                 if (!tmp_bp_set)
 883                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 884                                 else {
 885                                         /* Start the core */
 886                                         LOG_DEBUG("Starting core to serve pending interrupts");
 887                                         int64_t t_start = timeval_ms();
 888                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 889
 890                                         /* Wait for pending handlers to complete or timeout */
 891                                         do {
 892                                                 retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap,
 893                                                                 DCB_DHCSR,
 894                                                                 &cortex_m->dcb_dhcsr);
 895                                                 if (retval != ERROR_OK) {
 896                                                         target->state = TARGET_UNKNOWN;
 897                                                         return retval;
 898                                                 }
 899                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
 900                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
 901
 902                                         /* only remove breakpoint if we created it */
 903                                         if (breakpoint)
 904                                                 cortex_m_unset_breakpoint(target, breakpoint);
 905                                         else {
 906                                                 /* Remove the temporary breakpoint */
 907                                                 breakpoint_remove(target, pc_value);
 908                                         }
 909
 910                                         if (isr_timed_out) {
 911                                                 LOG_DEBUG("Interrupt handlers didn't complete within time, "
 912                                                         "leaving target running");
 913                                         } else {
 914                                                 /* Step over next instruction with interrupts disabled */
 915                                                 cortex_m_write_debug_halt_mask(target,
 916                                                         C_HALT | C_MASKINTS,
 917                                                         0);
 918                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 919                                                 /* Re-enable interrupts */
 920                                                 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926
 927         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 928         if (retval != ERROR_OK)
 929                 return retval;
 930
 931         /* registers are now invalid */
 932         register_cache_invalidate(armv7m->arm.core_cache);
 933
 934         if (breakpoint)
 935                 cortex_m_set_breakpoint(target, breakpoint);
 936
 937         if (isr_timed_out) {
 938                 /* Leave the core running. The user has to stop execution manually. */
 939                 target->debug_reason = DBG_REASON_NOTHALTED;
 940                 target->state = TARGET_RUNNING;
 941                 return ERROR_OK;
 942         }
 943
 944         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 945                 " nvic_icsr = 0x%" PRIx32,
 946                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
 947
 948         retval = cortex_m_debug_entry(target);
 949         if (retval != ERROR_OK)
 950                 return retval;
 951         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 952
 953         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 954                 " nvic_icsr = 0x%" PRIx32,
 955                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
 956
 957         return ERROR_OK;
 958 }
 959
 960 static int cortex_m_assert_reset(struct target *target)
 961 {
 962         struct cortex_m_common *cortex_m = target_to_cm(target);
 963         struct armv7m_common *armv7m = &cortex_m->armv7m;
 964         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
 965
 966         LOG_DEBUG("target->state: %s",
 967                 target_state_name(target));
 968
 969         enum reset_types jtag_reset_config = jtag_get_reset_config();
 970
 971         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 972                 /* allow scripts to override the reset event */
 973
 974                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 975                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 976                 target->state = TARGET_RESET;
 977
 978                 return ERROR_OK;
 979         }
 980
 981         /* some cores support connecting while srst is asserted
 982          * use that mode is it has been configured */
 983
 984         bool srst_asserted = false;
 985
 986         if ((jtag_reset_config & RESET_HAS_SRST) &&
 987             (jtag_reset_config & RESET_SRST_NO_GATING)) {
 988                 adapter_assert_reset();
 989                 srst_asserted = true;
 990         }
 991
 992         /* Enable debug requests */
 993         int retval;
 994         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 995         if (retval != ERROR_OK)
 996                 return retval;
 997         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 998                 retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 999                 if (retval != ERROR_OK)
1000                         return retval;
1001         }
1002
1003         /* If the processor is sleeping in a WFI or WFE instruction, the
1004          * C_HALT bit must be asserted to regain control */
1005         if (cortex_m->dcb_dhcsr & S_SLEEP) {
1006                 retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1007                 if (retval != ERROR_OK)
1008                         return retval;
1009         }
1010
1011         retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1012         if (retval != ERROR_OK)
1013                 return retval;
1014
1015         if (!target->reset_halt) {
1016                 /* Set/Clear C_MASKINTS in a separate operation */
1017                 if (cortex_m->dcb_dhcsr & C_MASKINTS) {
1018                         retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
1019                                         DBGKEY | C_DEBUGEN | C_HALT);
1020                         if (retval != ERROR_OK)
1021                                 return retval;
1022                 }
1023
1024                 /* clear any debug flags before resuming */
1025                 cortex_m_clear_halt(target);
1026
1027                 /* clear C_HALT in dhcsr reg */
1028                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1029         } else {
1030                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1031                  *
1032                  * REVISIT catching BUSERR presumably helps to defend against
1033                  * bad vector table entries.  Should this include MMERR or
1034                  * other flags too?
1035                  */
1036                 retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1037                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1038                 if (retval != ERROR_OK)
1039                         return retval;
1040         }
1041
1042         if (jtag_reset_config & RESET_HAS_SRST) {
1043                 /* default to asserting srst */
1044                 if (!srst_asserted)
1045                         adapter_assert_reset();
1046         } else {
1047                 /* Use a standard Cortex-M3 software reset mechanism.
1048                  * We default to using VECRESET as it is supported on all current cores.
1049                  * This has the disadvantage of not resetting the peripherals, so a
1050                  * reset-init event handler is needed to perform any peripheral resets.
1051                  */
1052                 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1053                         ? "SYSRESETREQ" : "VECTRESET");
1054
1055                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1056                         LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1057                                 "handler to reset any peripherals or configure hardware srst support.");
1058                 }
1059
1060                 retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1061                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1062                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1063                 if (retval != ERROR_OK)
1064                         LOG_DEBUG("Ignoring AP write error right after reset");
1065
1066                 retval = ahbap_debugport_init(armv7m->debug_ap);
1067                 if (retval != ERROR_OK) {
1068                         LOG_ERROR("DP initialisation failed");
1069                         return retval;
1070                 }
1071
1072                 {
1073                         /* I do not know why this is necessary, but it
1074                          * fixes strange effects (step/resume cause NMI
1075                          * after reset) on LM3S6918 -- Michael Schwingen
1076                          */
1077                         uint32_t tmp;
1078                         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1079                         if (retval != ERROR_OK)
1080                                 return retval;
1081                 }
1082         }
1083
1084         target->state = TARGET_RESET;
1085         jtag_add_sleep(50000);
1086
1087         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1088
1089         if (target->reset_halt) {
1090                 retval = target_halt(target);
1091                 if (retval != ERROR_OK)
1092                         return retval;
1093         }
1094
1095         return ERROR_OK;
1096 }
1097
1098 static int cortex_m_deassert_reset(struct target *target)
1099 {
1100         struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1101
1102         LOG_DEBUG("target->state: %s",
1103                 target_state_name(target));
1104
1105         /* deassert reset lines */
1106         adapter_deassert_reset();
1107
1108         enum reset_types jtag_reset_config = jtag_get_reset_config();
1109
1110         if ((jtag_reset_config & RESET_HAS_SRST) &&
1111             !(jtag_reset_config & RESET_SRST_NO_GATING)) {
1112                 int retval = ahbap_debugport_init(armv7m->debug_ap);
1113                 if (retval != ERROR_OK) {
1114                         LOG_ERROR("DP initialisation failed");
1115                         return retval;
1116                 }
1117         }
1118
1119         return ERROR_OK;
1120 }
1121
1122 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1123 {
1124         int retval;
1125         int fp_num = 0;
1126         struct cortex_m_common *cortex_m = target_to_cm(target);
1127         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1128
1129         if (breakpoint->set) {
1130                 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1131                 return ERROR_OK;
1132         }
1133
1134         if (cortex_m->auto_bp_type)
1135                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1136
1137         if (breakpoint->type == BKPT_HARD) {
1138                 uint32_t fpcr_value;
1139                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1140                         fp_num++;
1141                 if (fp_num >= cortex_m->fp_num_code) {
1142                         LOG_ERROR("Can not find free FPB Comparator!");
1143                         return ERROR_FAIL;
1144                 }
1145                 breakpoint->set = fp_num + 1;
1146                 fpcr_value = breakpoint->address | 1;
1147                 if (cortex_m->fp_rev == 0) {
1148                         uint32_t hilo;
1149                         hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1150                         fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1151                 } else if (cortex_m->fp_rev > 1) {
1152                         LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1153                         return ERROR_FAIL;
1154                 }
1155                 comparator_list[fp_num].used = 1;
1156                 comparator_list[fp_num].fpcr_value = fpcr_value;
1157                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1158                         comparator_list[fp_num].fpcr_value);
1159                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1160                         fp_num,
1161                         comparator_list[fp_num].fpcr_value);
1162                 if (!cortex_m->fpb_enabled) {
1163                         LOG_DEBUG("FPB wasn't enabled, do it now");
1164                         retval = cortex_m_enable_fpb(target);
1165                         if (retval != ERROR_OK) {
1166                                 LOG_ERROR("Failed to enable the FPB");
1167                                 return retval;
1168                         }
1169
1170                         cortex_m->fpb_enabled = 1;
1171                 }
1172         } else if (breakpoint->type == BKPT_SOFT) {
1173                 uint8_t code[4];
1174
1175                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1176                  * semihosting; don't use that.  Otherwise the BKPT
1177                  * parameter is arbitrary.
1178                  */
1179                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1180                 retval = target_read_memory(target,
1181                                 breakpoint->address & 0xFFFFFFFE,
1182                                 breakpoint->length, 1,
1183                                 breakpoint->orig_instr);
1184                 if (retval != ERROR_OK)
1185                         return retval;
1186                 retval = target_write_memory(target,
1187                                 breakpoint->address & 0xFFFFFFFE,
1188                                 breakpoint->length, 1,
1189                                 code);
1190                 if (retval != ERROR_OK)
1191                         return retval;
1192                 breakpoint->set = true;
1193         }
1194
1195         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1196                 breakpoint->unique_id,
1197                 (int)(breakpoint->type),
1198                 breakpoint->address,
1199                 breakpoint->length,
1200                 breakpoint->set);
1201
1202         return ERROR_OK;
1203 }
1204
1205 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1206 {
1207         int retval;
1208         struct cortex_m_common *cortex_m = target_to_cm(target);
1209         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1210
1211         if (!breakpoint->set) {
1212                 LOG_WARNING("breakpoint not set");
1213                 return ERROR_OK;
1214         }
1215
1216         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1217                 breakpoint->unique_id,
1218                 (int)(breakpoint->type),
1219                 breakpoint->address,
1220                 breakpoint->length,
1221                 breakpoint->set);
1222
1223         if (breakpoint->type == BKPT_HARD) {
1224                 int fp_num = breakpoint->set - 1;
1225                 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1226                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1227                         return ERROR_OK;
1228                 }
1229                 comparator_list[fp_num].used = 0;
1230                 comparator_list[fp_num].fpcr_value = 0;
1231                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1232                         comparator_list[fp_num].fpcr_value);
1233         } else {
1234                 /* restore original instruction (kept in target endianness) */
1235                 if (breakpoint->length == 4) {
1236                         retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1237                                         breakpoint->orig_instr);
1238                         if (retval != ERROR_OK)
1239                                 return retval;
1240                 } else {
1241                         retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1242                                         breakpoint->orig_instr);
1243                         if (retval != ERROR_OK)
1244                                 return retval;
1245                 }
1246         }
1247         breakpoint->set = false;
1248
1249         return ERROR_OK;
1250 }
1251
1252 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1253 {
1254         struct cortex_m_common *cortex_m = target_to_cm(target);
1255
1256         if (cortex_m->auto_bp_type)
1257                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1258
1259         if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1260                 if (breakpoint->type == BKPT_HARD) {
1261                         LOG_INFO("flash patch comparator requested outside code memory region");
1262                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1263                 }
1264
1265                 if (breakpoint->type == BKPT_SOFT) {
1266                         LOG_INFO("soft breakpoint requested in code (flash) memory region");
1267                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1268                 }
1269         }
1270
1271         if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1272                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1273                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274         }
1275
1276         if (breakpoint->length == 3) {
1277                 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1278                 breakpoint->length = 2;
1279         }
1280
1281         if ((breakpoint->length != 2)) {
1282                 LOG_INFO("only breakpoints of two bytes length supported");
1283                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284         }
1285
1286         if (breakpoint->type == BKPT_HARD)
1287                 cortex_m->fp_code_available--;
1288
1289         return cortex_m_set_breakpoint(target, breakpoint);
1290 }
1291
1292 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1293 {
1294         struct cortex_m_common *cortex_m = target_to_cm(target);
1295
1296         /* REVISIT why check? FBP can be updated with core running ... */
1297         if (target->state != TARGET_HALTED) {
1298                 LOG_WARNING("target not halted");
1299                 return ERROR_TARGET_NOT_HALTED;
1300         }
1301
1302         if (cortex_m->auto_bp_type)
1303                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1304
1305         if (breakpoint->set)
1306                 cortex_m_unset_breakpoint(target, breakpoint);
1307
1308         if (breakpoint->type == BKPT_HARD)
1309                 cortex_m->fp_code_available++;
1310
1311         return ERROR_OK;
1312 }
1313
1314 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1315 {
1316         int dwt_num = 0;
1317         uint32_t mask, temp;
1318         struct cortex_m_common *cortex_m = target_to_cm(target);
1319
1320         /* watchpoint params were validated earlier */
1321         mask = 0;
1322         temp = watchpoint->length;
1323         while (temp) {
1324                 temp >>= 1;
1325                 mask++;
1326         }
1327         mask--;
1328
1329         /* REVISIT Don't fully trust these "not used" records ... users
1330          * may set up breakpoints by hand, e.g. dual-address data value
1331          * watchpoint using comparator #1; comparator #0 matching cycle
1332          * count; send data trace info through ITM and TPIU; etc
1333          */
1334         struct cortex_m_dwt_comparator *comparator;
1335
1336         for (comparator = cortex_m->dwt_comparator_list;
1337                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1338                 comparator++, dwt_num++)
1339                 continue;
1340         if (dwt_num >= cortex_m->dwt_num_comp) {
1341                 LOG_ERROR("Can not find free DWT Comparator");
1342                 return ERROR_FAIL;
1343         }
1344         comparator->used = 1;
1345         watchpoint->set = dwt_num + 1;
1346
1347         comparator->comp = watchpoint->address;
1348         target_write_u32(target, comparator->dwt_comparator_address + 0,
1349                 comparator->comp);
1350
1351         comparator->mask = mask;
1352         target_write_u32(target, comparator->dwt_comparator_address + 4,
1353                 comparator->mask);
1354
1355         switch (watchpoint->rw) {
1356                 case WPT_READ:
1357                         comparator->function = 5;
1358                         break;
1359                 case WPT_WRITE:
1360                         comparator->function = 6;
1361                         break;
1362                 case WPT_ACCESS:
1363                         comparator->function = 7;
1364                         break;
1365         }
1366         target_write_u32(target, comparator->dwt_comparator_address + 8,
1367                 comparator->function);
1368
1369         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1370                 watchpoint->unique_id, dwt_num,
1371                 (unsigned) comparator->comp,
1372                 (unsigned) comparator->mask,
1373                 (unsigned) comparator->function);
1374         return ERROR_OK;
1375 }
1376
1377 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1378 {
1379         struct cortex_m_common *cortex_m = target_to_cm(target);
1380         struct cortex_m_dwt_comparator *comparator;
1381         int dwt_num;
1382
1383         if (!watchpoint->set) {
1384                 LOG_WARNING("watchpoint (wpid: %d) not set",
1385                         watchpoint->unique_id);
1386                 return ERROR_OK;
1387         }
1388
1389         dwt_num = watchpoint->set - 1;
1390
1391         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1392                 watchpoint->unique_id, dwt_num,
1393                 (unsigned) watchpoint->address);
1394
1395         if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1396                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1397                 return ERROR_OK;
1398         }
1399
1400         comparator = cortex_m->dwt_comparator_list + dwt_num;
1401         comparator->used = 0;
1402         comparator->function = 0;
1403         target_write_u32(target, comparator->dwt_comparator_address + 8,
1404                 comparator->function);
1405
1406         watchpoint->set = false;
1407
1408         return ERROR_OK;
1409 }
1410
1411 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1412 {
1413         struct cortex_m_common *cortex_m = target_to_cm(target);
1414
1415         if (cortex_m->dwt_comp_available < 1) {
1416                 LOG_DEBUG("no comparators?");
1417                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1418         }
1419
1420         /* hardware doesn't support data value masking */
1421         if (watchpoint->mask != ~(uint32_t)0) {
1422                 LOG_DEBUG("watchpoint value masks not supported");
1423                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1424         }
1425
1426         /* hardware allows address masks of up to 32K */
1427         unsigned mask;
1428
1429         for (mask = 0; mask < 16; mask++) {
1430                 if ((1u << mask) == watchpoint->length)
1431                         break;
1432         }
1433         if (mask == 16) {
1434                 LOG_DEBUG("unsupported watchpoint length");
1435                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1436         }
1437         if (watchpoint->address & ((1 << mask) - 1)) {
1438                 LOG_DEBUG("watchpoint address is unaligned");
1439                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1440         }
1441
1442         /* Caller doesn't seem to be able to describe watching for data
1443          * values of zero; that flags "no value".
1444          *
1445          * REVISIT This DWT may well be able to watch for specific data
1446          * values.  Requires comparator #1 to set DATAVMATCH and match
1447          * the data, and another comparator (DATAVADDR0) matching addr.
1448          */
1449         if (watchpoint->value) {
1450                 LOG_DEBUG("data value watchpoint not YET supported");
1451                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1452         }
1453
1454         cortex_m->dwt_comp_available--;
1455         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1456
1457         return ERROR_OK;
1458 }
1459
1460 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1461 {
1462         struct cortex_m_common *cortex_m = target_to_cm(target);
1463
1464         /* REVISIT why check? DWT can be updated with core running ... */
1465         if (target->state != TARGET_HALTED) {
1466                 LOG_WARNING("target not halted");
1467                 return ERROR_TARGET_NOT_HALTED;
1468         }
1469
1470         if (watchpoint->set)
1471                 cortex_m_unset_watchpoint(target, watchpoint);
1472
1473         cortex_m->dwt_comp_available++;
1474         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1475
1476         return ERROR_OK;
1477 }
1478
1479 void cortex_m_enable_watchpoints(struct target *target)
1480 {
1481         struct watchpoint *watchpoint = target->watchpoints;
1482
1483         /* set any pending watchpoints */
1484         while (watchpoint) {
1485                 if (!watchpoint->set)
1486                         cortex_m_set_watchpoint(target, watchpoint);
1487                 watchpoint = watchpoint->next;
1488         }
1489 }
1490
1491 static int cortex_m_load_core_reg_u32(struct target *target,
1492                 uint32_t num, uint32_t *value)
1493 {
1494         int retval;
1495
1496         /* NOTE:  we "know" here that the register identifiers used
1497          * in the v7m header match the Cortex-M3 Debug Core Register
1498          * Selector values for R0..R15, xPSR, MSP, and PSP.
1499          */
1500         switch (num) {
1501                 case 0 ... 18:
1502                         /* read a normal core register */
1503                         retval = cortexm_dap_read_coreregister_u32(target, value, num);
1504
1505                         if (retval != ERROR_OK) {
1506                                 LOG_ERROR("JTAG failure %i", retval);
1507                                 return ERROR_JTAG_DEVICE_ERROR;
1508                         }
1509                         LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
1510                         break;
1511
1512                 case ARMV7M_FPSCR:
1513                         /* Floating-point Status and Registers */
1514                         retval = target_write_u32(target, DCB_DCRSR, 0x21);
1515                         if (retval != ERROR_OK)
1516                                 return retval;
1517                         retval = target_read_u32(target, DCB_DCRDR, value);
1518                         if (retval != ERROR_OK)
1519                                 return retval;
1520                         LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
1521                         break;
1522
1523                 case ARMV7M_S0 ... ARMV7M_S31:
1524                         /* Floating-point Status and Registers */
1525                         retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1526                         if (retval != ERROR_OK)
1527                                 return retval;
1528                         retval = target_read_u32(target, DCB_DCRDR, value);
1529                         if (retval != ERROR_OK)
1530                                 return retval;
1531                         LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
1532                                   (int)(num - ARMV7M_S0), *value);
1533                         break;
1534
1535                 case ARMV7M_PRIMASK:
1536                 case ARMV7M_BASEPRI:
1537                 case ARMV7M_FAULTMASK:
1538                 case ARMV7M_CONTROL:
1539                         /* Cortex-M3 packages these four registers as bitfields
1540                          * in one Debug Core register.  So say r0 and r2 docs;
1541                          * it was removed from r1 docs, but still works.
1542                          */
1543                         cortexm_dap_read_coreregister_u32(target, value, 20);
1544
1545                         switch (num) {
1546                                 case ARMV7M_PRIMASK:
1547                                         *value = buf_get_u32((uint8_t *)value, 0, 1);
1548                                         break;
1549
1550                                 case ARMV7M_BASEPRI:
1551                                         *value = buf_get_u32((uint8_t *)value, 8, 8);
1552                                         break;
1553
1554                                 case ARMV7M_FAULTMASK:
1555                                         *value = buf_get_u32((uint8_t *)value, 16, 1);
1556                                         break;
1557
1558                                 case ARMV7M_CONTROL:
1559                                         *value = buf_get_u32((uint8_t *)value, 24, 2);
1560                                         break;
1561                         }
1562
1563                         LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1564                         break;
1565
1566                 default:
1567                         return ERROR_COMMAND_SYNTAX_ERROR;
1568         }
1569
1570         return ERROR_OK;
1571 }
1572
1573 static int cortex_m_store_core_reg_u32(struct target *target,
1574                 uint32_t num, uint32_t value)
1575 {
1576         int retval;
1577         uint32_t reg;
1578         struct armv7m_common *armv7m = target_to_armv7m(target);
1579
1580         /* NOTE:  we "know" here that the register identifiers used
1581          * in the v7m header match the Cortex-M3 Debug Core Register
1582          * Selector values for R0..R15, xPSR, MSP, and PSP.
1583          */
1584         switch (num) {
1585                 case 0 ... 18:
1586                         retval = cortexm_dap_write_coreregister_u32(target, value, num);
1587                         if (retval != ERROR_OK) {
1588                                 struct reg *r;
1589
1590                                 LOG_ERROR("JTAG failure");
1591                                 r = armv7m->arm.core_cache->reg_list + num;
1592                                 r->dirty = r->valid;
1593                                 return ERROR_JTAG_DEVICE_ERROR;
1594                         }
1595                         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1596                         break;
1597
1598                 case ARMV7M_FPSCR:
1599                         /* Floating-point Status and Registers */
1600                         retval = target_write_u32(target, DCB_DCRDR, value);
1601                         if (retval != ERROR_OK)
1602                                 return retval;
1603                         retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1604                         if (retval != ERROR_OK)
1605                                 return retval;
1606                         LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1607                         break;
1608
1609                 case ARMV7M_S0 ... ARMV7M_S31:
1610                         /* Floating-point Status and Registers */
1611                         retval = target_write_u32(target, DCB_DCRDR, value);
1612                         if (retval != ERROR_OK)
1613                                 return retval;
1614                         retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1615                         if (retval != ERROR_OK)
1616                                 return retval;
1617                         LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
1618                                   (int)(num - ARMV7M_S0), value);
1619                         break;
1620
1621                 case ARMV7M_PRIMASK:
1622                 case ARMV7M_BASEPRI:
1623                 case ARMV7M_FAULTMASK:
1624                 case ARMV7M_CONTROL:
1625                         /* Cortex-M3 packages these four registers as bitfields
1626                          * in one Debug Core register.  So say r0 and r2 docs;
1627                          * it was removed from r1 docs, but still works.
1628                          */
1629                         cortexm_dap_read_coreregister_u32(target, &reg, 20);
1630
1631                         switch (num) {
1632                                 case ARMV7M_PRIMASK:
1633                                         buf_set_u32((uint8_t *)&reg, 0, 1, value);
1634                                         break;
1635
1636                                 case ARMV7M_BASEPRI:
1637                                         buf_set_u32((uint8_t *)&reg, 8, 8, value);
1638                                         break;
1639
1640                                 case ARMV7M_FAULTMASK:
1641                                         buf_set_u32((uint8_t *)&reg, 16, 1, value);
1642                                         break;
1643
1644                                 case ARMV7M_CONTROL:
1645                                         buf_set_u32((uint8_t *)&reg, 24, 2, value);
1646                                         break;
1647                         }
1648
1649                         cortexm_dap_write_coreregister_u32(target, reg, 20);
1650
1651                         LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1652                         break;
1653
1654                 default:
1655                         return ERROR_COMMAND_SYNTAX_ERROR;
1656         }
1657
1658         return ERROR_OK;
1659 }
1660
1661 static int cortex_m_read_memory(struct target *target, uint32_t address,
1662         uint32_t size, uint32_t count, uint8_t *buffer)
1663 {
1664         struct armv7m_common *armv7m = target_to_armv7m(target);
1665
1666         if (armv7m->arm.is_armv6m) {
1667                 /* armv6m does not handle unaligned memory access */
1668                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1669                         return ERROR_TARGET_UNALIGNED_ACCESS;
1670         }
1671
1672         return mem_ap_sel_read_buf(armv7m->debug_ap, buffer, size, count, address);
1673 }
1674
1675 static int cortex_m_write_memory(struct target *target, uint32_t address,
1676         uint32_t size, uint32_t count, const uint8_t *buffer)
1677 {
1678         struct armv7m_common *armv7m = target_to_armv7m(target);
1679
1680         if (armv7m->arm.is_armv6m) {
1681                 /* armv6m does not handle unaligned memory access */
1682                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1683                         return ERROR_TARGET_UNALIGNED_ACCESS;
1684         }
1685
1686         return mem_ap_sel_write_buf(armv7m->debug_ap, buffer, size, count, address);
1687 }
1688
1689 static int cortex_m_init_target(struct command_context *cmd_ctx,
1690         struct target *target)
1691 {
1692         armv7m_build_reg_cache(target);
1693         return ERROR_OK;
1694 }
1695
1696 void cortex_m_deinit_target(struct target *target)
1697 {
1698         struct cortex_m_common *cortex_m = target_to_cm(target);
1699
1700         free(cortex_m->fp_comparator_list);
1701
1702         cortex_m_dwt_free(target);
1703         armv7m_free_reg_cache(target);
1704
1705         free(cortex_m);
1706 }
1707
1708 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1709  * on r/w if the core is not running, and clear on resume or reset ... or
1710  * at least, in a post_restore_context() method.
1711  */
1712
1713 struct dwt_reg_state {
1714         struct target *target;
1715         uint32_t addr;
1716         uint8_t value[4];               /* scratch/cache */
1717 };
1718
1719 static int cortex_m_dwt_get_reg(struct reg *reg)
1720 {
1721         struct dwt_reg_state *state = reg->arch_info;
1722
1723         uint32_t tmp;
1724         int retval = target_read_u32(state->target, state->addr, &tmp);
1725         if (retval != ERROR_OK)
1726                 return retval;
1727
1728         buf_set_u32(state->value, 0, 32, tmp);
1729         return ERROR_OK;
1730 }
1731
1732 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1733 {
1734         struct dwt_reg_state *state = reg->arch_info;
1735
1736         return target_write_u32(state->target, state->addr,
1737                         buf_get_u32(buf, 0, reg->size));
1738 }
1739
1740 struct dwt_reg {
1741         uint32_t addr;
1742         char *name;
1743         unsigned size;
1744 };
1745
1746 static struct dwt_reg dwt_base_regs[] = {
1747         { DWT_CTRL, "dwt_ctrl", 32, },
1748         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1749          * increments while the core is asleep.
1750          */
1751         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1752         /* plus some 8 bit counters, useful for profiling with TPIU */
1753 };
1754
1755 static struct dwt_reg dwt_comp[] = {
1756 #define DWT_COMPARATOR(i) \
1757                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1758                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1759                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1760         DWT_COMPARATOR(0),
1761         DWT_COMPARATOR(1),
1762         DWT_COMPARATOR(2),
1763         DWT_COMPARATOR(3),
1764 #undef DWT_COMPARATOR
1765 };
1766
1767 static const struct reg_arch_type dwt_reg_type = {
1768         .get = cortex_m_dwt_get_reg,
1769         .set = cortex_m_dwt_set_reg,
1770 };
1771
1772 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1773 {
1774         struct dwt_reg_state *state;
1775
1776         state = calloc(1, sizeof *state);
1777         if (!state)
1778                 return;
1779         state->addr = d->addr;
1780         state->target = t;
1781
1782         r->name = d->name;
1783         r->size = d->size;
1784         r->value = state->value;
1785         r->arch_info = state;
1786         r->type = &dwt_reg_type;
1787 }
1788
1789 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1790 {
1791         uint32_t dwtcr;
1792         struct reg_cache *cache;
1793         struct cortex_m_dwt_comparator *comparator;
1794         int reg, i;
1795
1796         target_read_u32(target, DWT_CTRL, &dwtcr);
1797         if (!dwtcr) {
1798                 LOG_DEBUG("no DWT");
1799                 return;
1800         }
1801
1802         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1803         cm->dwt_comp_available = cm->dwt_num_comp;
1804         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1805                         sizeof(struct cortex_m_dwt_comparator));
1806         if (!cm->dwt_comparator_list) {
1807 fail0:
1808                 cm->dwt_num_comp = 0;
1809                 LOG_ERROR("out of mem");
1810                 return;
1811         }
1812
1813         cache = calloc(1, sizeof *cache);
1814         if (!cache) {
1815 fail1:
1816                 free(cm->dwt_comparator_list);
1817                 goto fail0;
1818         }
1819         cache->name = "Cortex-M DWT registers";
1820         cache->num_regs = 2 + cm->dwt_num_comp * 3;
1821         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1822         if (!cache->reg_list) {
1823                 free(cache);
1824                 goto fail1;
1825         }
1826
1827         for (reg = 0; reg < 2; reg++)
1828                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1829                         dwt_base_regs + reg);
1830
1831         comparator = cm->dwt_comparator_list;
1832         for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1833                 int j;
1834
1835                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1836                 for (j = 0; j < 3; j++, reg++)
1837                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
1838                                 dwt_comp + 3 * i + j);
1839
1840                 /* make sure we clear any watchpoints enabled on the target */
1841                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1842         }
1843
1844         *register_get_last_cache_p(&target->reg_cache) = cache;
1845         cm->dwt_cache = cache;
1846
1847         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1848                 dwtcr, cm->dwt_num_comp,
1849                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1850
1851         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1852          * implement single-address data value watchpoints ... so we
1853          * won't need to check it later, when asked to set one up.
1854          */
1855 }
1856
1857 static void cortex_m_dwt_free(struct target *target)
1858 {
1859         struct cortex_m_common *cm = target_to_cm(target);
1860         struct reg_cache *cache = cm->dwt_cache;
1861
1862         free(cm->dwt_comparator_list);
1863         cm->dwt_comparator_list = NULL;
1864         cm->dwt_num_comp = 0;
1865
1866         if (cache) {
1867                 register_unlink_cache(&target->reg_cache, cache);
1868
1869                 if (cache->reg_list) {
1870                         for (size_t i = 0; i < cache->num_regs; i++)
1871                                 free(cache->reg_list[i].arch_info);
1872                         free(cache->reg_list);
1873                 }
1874                 free(cache);
1875         }
1876         cm->dwt_cache = NULL;
1877 }
1878
1879 #define MVFR0 0xe000ef40
1880 #define MVFR1 0xe000ef44
1881
1882 #define MVFR0_DEFAULT_M4 0x10110021
1883 #define MVFR1_DEFAULT_M4 0x11000011
1884
1885 int cortex_m_examine(struct target *target)
1886 {
1887         int retval;
1888         uint32_t cpuid, fpcr, mvfr0, mvfr1;
1889         int i;
1890         struct cortex_m_common *cortex_m = target_to_cm(target);
1891         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1892         struct armv7m_common *armv7m = target_to_armv7m(target);
1893
1894         /* Search for the MEM-AP */
1895         retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
1896         if (retval != ERROR_OK) {
1897                 LOG_ERROR("Could not find MEM-AP to control the core");
1898                 return retval;
1899         }
1900
1901         /* Leave (only) generic DAP stuff for debugport_init(); */
1902         armv7m->debug_ap->memaccess_tck = 8;
1903
1904         /* stlink shares the examine handler but does not support
1905          * all its calls */
1906         if (!armv7m->stlink) {
1907                 retval = ahbap_debugport_init(armv7m->debug_ap);
1908                 if (retval != ERROR_OK)
1909                         return retval;
1910         }
1911
1912         if (!target_was_examined(target)) {
1913                 target_set_examined(target);
1914
1915                 /* Read from Device Identification Registers */
1916                 retval = target_read_u32(target, CPUID, &cpuid);
1917                 if (retval != ERROR_OK)
1918                         return retval;
1919
1920                 /* Get CPU Type */
1921                 i = (cpuid >> 4) & 0xf;
1922
1923                 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1924                                 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1925                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1926
1927                 /* test for floating point feature on cortex-m4 */
1928                 if (i == 4) {
1929                         target_read_u32(target, MVFR0, &mvfr0);
1930                         target_read_u32(target, MVFR1, &mvfr1);
1931
1932                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
1933                                 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
1934                                 armv7m->fp_feature = FPv4_SP;
1935                         }
1936                 } else if (i == 0) {
1937                         /* Cortex-M0 does not support unaligned memory access */
1938                         armv7m->arm.is_armv6m = true;
1939                 }
1940
1941                 if (armv7m->fp_feature != FPv4_SP &&
1942                     armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
1943                         /* free unavailable FPU registers */
1944                         size_t idx;
1945
1946                         for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
1947                              idx < armv7m->arm.core_cache->num_regs;
1948                              idx++) {
1949                                 free(armv7m->arm.core_cache->reg_list[idx].value);
1950                                 free(armv7m->arm.core_cache->reg_list[idx].feature);
1951                                 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
1952                         }
1953                         armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
1954                 }
1955
1956                 if (i == 4 || i == 3) {
1957                         /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1958                         armv7m->debug_ap->tar_autoincr_block = (1 << 12);
1959                 }
1960
1961                 /* Configure trace modules */
1962                 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
1963                 if (retval != ERROR_OK)
1964                         return retval;
1965
1966                 if (armv7m->trace_config.config_type != DISABLED) {
1967                         armv7m_trace_tpiu_config(target);
1968                         armv7m_trace_itm_config(target);
1969                 }
1970
1971                 /* NOTE: FPB and DWT are both optional. */
1972
1973                 /* Setup FPB */
1974                 target_read_u32(target, FP_CTRL, &fpcr);
1975                 cortex_m->auto_bp_type = 1;
1976                 /* bits [14:12] and [7:4] */
1977                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
1978                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
1979                 cortex_m->fp_code_available = cortex_m->fp_num_code;
1980                 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
1981                    Revision is zero base, fp_rev == 1 means Rev.2 ! */
1982                 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
1983                 free(cortex_m->fp_comparator_list);
1984                 cortex_m->fp_comparator_list = calloc(
1985                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
1986                                 sizeof(struct cortex_m_fp_comparator));
1987                 cortex_m->fpb_enabled = fpcr & 1;
1988                 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
1989                         cortex_m->fp_comparator_list[i].type =
1990                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1991                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1992
1993                         /* make sure we clear any breakpoints enabled on the target */
1994                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
1995                 }
1996                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
1997                         fpcr,
1998                         cortex_m->fp_num_code,
1999                         cortex_m->fp_num_lit);
2000
2001                 /* Setup DWT */
2002                 cortex_m_dwt_free(target);
2003                 cortex_m_dwt_setup(cortex_m, target);
2004
2005                 /* These hardware breakpoints only work for code in flash! */
2006                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2007                         target_name(target),
2008                         cortex_m->fp_num_code,
2009                         cortex_m->dwt_num_comp);
2010         }
2011
2012         return ERROR_OK;
2013 }
2014
2015 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2016 {
2017         struct armv7m_common *armv7m = target_to_armv7m(target);
2018         uint16_t dcrdr;
2019         uint8_t buf[2];
2020         int retval;
2021
2022         retval = mem_ap_sel_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2023         if (retval != ERROR_OK)
2024                 return retval;
2025
2026         dcrdr = target_buffer_get_u16(target, buf);
2027         *ctrl = (uint8_t)dcrdr;
2028         *value = (uint8_t)(dcrdr >> 8);
2029
2030         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2031
2032         /* write ack back to software dcc register
2033          * signify we have read data */
2034         if (dcrdr & (1 << 0)) {
2035                 target_buffer_set_u16(target, buf, 0);
2036                 retval = mem_ap_sel_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2037                 if (retval != ERROR_OK)
2038                         return retval;
2039         }
2040
2041         return ERROR_OK;
2042 }
2043
2044 static int cortex_m_target_request_data(struct target *target,
2045         uint32_t size, uint8_t *buffer)
2046 {
2047         uint8_t data;
2048         uint8_t ctrl;
2049         uint32_t i;
2050
2051         for (i = 0; i < (size * 4); i++) {
2052                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2053                 if (retval != ERROR_OK)
2054                         return retval;
2055                 buffer[i] = data;
2056         }
2057
2058         return ERROR_OK;
2059 }
2060
2061 static int cortex_m_handle_target_request(void *priv)
2062 {
2063         struct target *target = priv;
2064         if (!target_was_examined(target))
2065                 return ERROR_OK;
2066
2067         if (!target->dbg_msg_enabled)
2068                 return ERROR_OK;
2069
2070         if (target->state == TARGET_RUNNING) {
2071                 uint8_t data;
2072                 uint8_t ctrl;
2073                 int retval;
2074
2075                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2076                 if (retval != ERROR_OK)
2077                         return retval;
2078
2079                 /* check if we have data */
2080                 if (ctrl & (1 << 0)) {
2081                         uint32_t request;
2082
2083                         /* we assume target is quick enough */
2084                         request = data;
2085                         for (int i = 1; i <= 3; i++) {
2086                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2087                                 if (retval != ERROR_OK)
2088                                         return retval;
2089                                 request |= ((uint32_t)data << (i * 8));
2090                         }
2091                         target_request(target, request);
2092                 }
2093         }
2094
2095         return ERROR_OK;
2096 }
2097
2098 static int cortex_m_init_arch_info(struct target *target,
2099         struct cortex_m_common *cortex_m, struct jtag_tap *tap)
2100 {
2101         struct armv7m_common *armv7m = &cortex_m->armv7m;
2102
2103         armv7m_init_arch_info(target, armv7m);
2104
2105         /*  tap has no dap initialized */
2106         if (!tap->dap) {
2107                 tap->dap = dap_init();
2108
2109                 /* Leave (only) generic DAP stuff for debugport_init() */
2110                 tap->dap->tap = tap;
2111         }
2112
2113         /* default reset mode is to use srst if fitted
2114          * if not it will use CORTEX_M3_RESET_VECTRESET */
2115         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2116
2117         armv7m->arm.dap = tap->dap;
2118
2119         /* Leave (only) generic DAP stuff for debugport_init(); */
2120         tap->dap->ap[dap_ap_get_select(tap->dap)].memaccess_tck = 8;
2121
2122         /* register arch-specific functions */
2123         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2124
2125         armv7m->post_debug_entry = NULL;
2126
2127         armv7m->pre_restore_context = NULL;
2128
2129         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2130         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2131
2132         target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2133
2134         return ERROR_OK;
2135 }
2136
2137 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2138 {
2139         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2140
2141         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2142         cortex_m_init_arch_info(target, cortex_m, target->tap);
2143
2144         return ERROR_OK;
2145 }
2146
2147 /*--------------------------------------------------------------------------*/
2148
2149 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2150         struct cortex_m_common *cm)
2151 {
2152         if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2153                 command_print(cmd_ctx, "target is not a Cortex-M");
2154                 return ERROR_TARGET_INVALID;
2155         }
2156         return ERROR_OK;
2157 }
2158
2159 /*
2160  * Only stuff below this line should need to verify that its target
2161  * is a Cortex-M3.  Everything else should have indirected through the
2162  * cortexm3_target structure, which is only used with CM3 targets.
2163  */
2164
2165 static const struct {
2166         char name[10];
2167         unsigned mask;
2168 } vec_ids[] = {
2169         { "hard_err",   VC_HARDERR, },
2170         { "int_err",    VC_INTERR, },
2171         { "bus_err",    VC_BUSERR, },
2172         { "state_err",  VC_STATERR, },
2173         { "chk_err",    VC_CHKERR, },
2174         { "nocp_err",   VC_NOCPERR, },
2175         { "mm_err",     VC_MMERR, },
2176         { "reset",      VC_CORERESET, },
2177 };
2178
2179 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2180 {
2181         struct target *target = get_current_target(CMD_CTX);
2182         struct cortex_m_common *cortex_m = target_to_cm(target);
2183         struct armv7m_common *armv7m = &cortex_m->armv7m;
2184         uint32_t demcr = 0;
2185         int retval;
2186
2187         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2188         if (retval != ERROR_OK)
2189                 return retval;
2190
2191         retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2192         if (retval != ERROR_OK)
2193                 return retval;
2194
2195         if (CMD_ARGC > 0) {
2196                 unsigned catch = 0;
2197
2198                 if (CMD_ARGC == 1) {
2199                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2200                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2201                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2202                                         | VC_MMERR | VC_CORERESET;
2203                                 goto write;
2204                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2205                                 goto write;
2206                 }
2207                 while (CMD_ARGC-- > 0) {
2208                         unsigned i;
2209                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2210                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2211                                         continue;
2212                                 catch |= vec_ids[i].mask;
2213                                 break;
2214                         }
2215                         if (i == ARRAY_SIZE(vec_ids)) {
2216                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2217                                 return ERROR_COMMAND_SYNTAX_ERROR;
2218                         }
2219                 }
2220 write:
2221                 /* For now, armv7m->demcr only stores vector catch flags. */
2222                 armv7m->demcr = catch;
2223
2224                 demcr &= ~0xffff;
2225                 demcr |= catch;
2226
2227                 /* write, but don't assume it stuck (why not??) */
2228                 retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2229                 if (retval != ERROR_OK)
2230                         return retval;
2231                 retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2232                 if (retval != ERROR_OK)
2233                         return retval;
2234
2235                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2236                  * Otherwise the vector catch hardware could fire when there's
2237                  * no debugger hooked up, causing much confusion...
2238                  */
2239         }
2240
2241         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2242                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2243                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2244         }
2245
2246         return ERROR_OK;
2247 }
2248
2249 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2250 {
2251         struct target *target = get_current_target(CMD_CTX);
2252         struct cortex_m_common *cortex_m = target_to_cm(target);
2253         int retval;
2254
2255         static const Jim_Nvp nvp_maskisr_modes[] = {
2256                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2257                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2258                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2259                 { .name = NULL, .value = -1 },
2260         };
2261         const Jim_Nvp *n;
2262
2263
2264         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2265         if (retval != ERROR_OK)
2266                 return retval;
2267
2268         if (target->state != TARGET_HALTED) {
2269                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2270                 return ERROR_OK;
2271         }
2272
2273         if (CMD_ARGC > 0) {
2274                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2275                 if (n->name == NULL)
2276                         return ERROR_COMMAND_SYNTAX_ERROR;
2277                 cortex_m->isrmasking_mode = n->value;
2278
2279
2280                 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2281                         cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2282                 else
2283                         cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2284         }
2285
2286         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2287         command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2288
2289         return ERROR_OK;
2290 }
2291
2292 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2293 {
2294         struct target *target = get_current_target(CMD_CTX);
2295         struct cortex_m_common *cortex_m = target_to_cm(target);
2296         int retval;
2297         char *reset_config;
2298
2299         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2300         if (retval != ERROR_OK)
2301                 return retval;
2302
2303         if (CMD_ARGC > 0) {
2304                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2305                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2306                 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2307                         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2308         }
2309
2310         switch (cortex_m->soft_reset_config) {
2311                 case CORTEX_M_RESET_SYSRESETREQ:
2312                         reset_config = "sysresetreq";
2313                         break;
2314
2315                 case CORTEX_M_RESET_VECTRESET:
2316                         reset_config = "vectreset";
2317                         break;
2318
2319                 default:
2320                         reset_config = "unknown";
2321                         break;
2322         }
2323
2324         command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2325
2326         return ERROR_OK;
2327 }
2328
2329 static const struct command_registration cortex_m_exec_command_handlers[] = {
2330         {
2331                 .name = "maskisr",
2332                 .handler = handle_cortex_m_mask_interrupts_command,
2333                 .mode = COMMAND_EXEC,
2334                 .help = "mask cortex_m interrupts",
2335                 .usage = "['auto'|'on'|'off']",
2336         },
2337         {
2338                 .name = "vector_catch",
2339                 .handler = handle_cortex_m_vector_catch_command,
2340                 .mode = COMMAND_EXEC,
2341                 .help = "configure hardware vectors to trigger debug entry",
2342                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2343         },
2344         {
2345                 .name = "reset_config",
2346                 .handler = handle_cortex_m_reset_config_command,
2347                 .mode = COMMAND_ANY,
2348                 .help = "configure software reset handling",
2349                 .usage = "['srst'|'sysresetreq'|'vectreset']",
2350         },
2351         COMMAND_REGISTRATION_DONE
2352 };
2353 static const struct command_registration cortex_m_command_handlers[] = {
2354         {
2355                 .chain = armv7m_command_handlers,
2356         },
2357         {
2358                 .chain = armv7m_trace_command_handlers,
2359         },
2360         {
2361                 .name = "cortex_m",
2362                 .mode = COMMAND_EXEC,
2363                 .help = "Cortex-M command group",
2364                 .usage = "",
2365                 .chain = cortex_m_exec_command_handlers,
2366         },
2367         COMMAND_REGISTRATION_DONE
2368 };
2369
2370 struct target_type cortexm_target = {
2371         .name = "cortex_m",
2372         .deprecated_name = "cortex_m3",
2373
2374         .poll = cortex_m_poll,
2375         .arch_state = armv7m_arch_state,
2376
2377         .target_request_data = cortex_m_target_request_data,
2378
2379         .halt = cortex_m_halt,
2380         .resume = cortex_m_resume,
2381         .step = cortex_m_step,
2382
2383         .assert_reset = cortex_m_assert_reset,
2384         .deassert_reset = cortex_m_deassert_reset,
2385         .soft_reset_halt = cortex_m_soft_reset_halt,
2386
2387         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2388
2389         .read_memory = cortex_m_read_memory,
2390         .write_memory = cortex_m_write_memory,
2391         .checksum_memory = armv7m_checksum_memory,
2392         .blank_check_memory = armv7m_blank_check_memory,
2393
2394         .run_algorithm = armv7m_run_algorithm,
2395         .start_algorithm = armv7m_start_algorithm,
2396         .wait_algorithm = armv7m_wait_algorithm,
2397
2398         .add_breakpoint = cortex_m_add_breakpoint,
2399         .remove_breakpoint = cortex_m_remove_breakpoint,
2400         .add_watchpoint = cortex_m_add_watchpoint,
2401         .remove_watchpoint = cortex_m_remove_watchpoint,
2402
2403         .commands = cortex_m_command_handlers,
2404         .target_create = cortex_m_target_create,
2405         .init_target = cortex_m_init_target,
2406         .examine = cortex_m_examine,
2407         .deinit_target = cortex_m_deinit_target,
2408 };