1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Although there are some workarounds for errata seen only in r0p0
47 * silicon, such old parts are hard to find and thus not much tested
52 /* forward declarations */
53 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
54 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
55 static void cortex_m3_enable_watchpoints(struct target *target);
56 static int cortex_m3_store_core_reg_u32(struct target *target,
57 enum armv7m_regtype type, uint32_t num, uint32_t value);
59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
60 uint32_t *value, int regnum)
65 /* because the DCB_DCRDR is used for the emulated dcc channel
66 * we have to save/restore the DCB_DCRDR when used */
68 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
70 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
72 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
73 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
74 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
76 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
77 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
78 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
80 retval = swjdp_transaction_endcheck(swjdp);
82 /* restore DCB_DCRDR - this needs to be in a seperate
83 * transaction otherwise the emulated DCC channel breaks */
84 if (retval == ERROR_OK)
85 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
91 uint32_t value, int regnum)
96 /* because the DCB_DCRDR is used for the emulated dcc channel
97 * we have to save/restore the DCB_DCRDR when used */
99 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
101 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
103 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
104 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
105 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
107 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
108 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
109 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
111 retval = swjdp_transaction_endcheck(swjdp);
113 /* restore DCB_DCRDR - this needs to be in a seperate
114 * transaction otherwise the emulated DCC channel breaks */
115 if (retval == ERROR_OK)
116 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
121 static int cortex_m3_write_debug_halt_mask(struct target *target,
122 uint32_t mask_on, uint32_t mask_off)
124 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
125 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
127 /* mask off status bits */
128 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
129 /* create new register mask */
130 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
132 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
135 static int cortex_m3_clear_halt(struct target *target)
137 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
138 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
140 /* clear step if any */
141 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
143 /* Read Debug Fault Status Register */
144 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
146 /* Clear Debug Fault Status */
147 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
148 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
153 static int cortex_m3_single_step_core(struct target *target)
155 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
156 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
159 /* backup dhcsr reg */
160 dhcsr_save = cortex_m3->dcb_dhcsr;
162 /* Mask interrupts before clearing halt, if done already. This avoids
163 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
164 * HALT can put the core into an unknown state.
166 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
167 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
168 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
169 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
170 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
173 /* restore dhcsr reg */
174 cortex_m3->dcb_dhcsr = dhcsr_save;
175 cortex_m3_clear_halt(target);
180 static int cortex_m3_endreset_event(struct target *target)
184 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
185 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
186 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
187 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
189 /* FIXME handling of DEMCR clobbers vector_catch config ... */
190 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
191 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
193 /* this register is used for emulated dcc channel */
194 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
196 /* Enable debug requests */
197 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
198 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
199 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
201 /* clear any interrupt masking */
202 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
204 /* Enable trace and DWT; trap hard and bus faults.
206 * REVISIT why trap those two? And why trash the vector_catch
207 * config, instead of preserving it? Catching HARDERR and BUSERR
208 * will interfere with code that handles those itself...
210 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
212 /* Monitor bus faults as such (instead of as generic HARDERR), but
213 * leave memory management and usage faults disabled.
215 * REVISIT setting BUSFAULTENA interferes with code which relies
216 * on the default setting. Why do it?
218 mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
220 /* Paranoia: evidently some (early?) chips don't preserve all the
221 * debug state (including FBP, DWT, etc) across reset...
225 target_write_u32(target, FP_CTRL, 3);
226 cortex_m3->fpb_enabled = 1;
228 /* Restore FPB registers */
229 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
231 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
234 /* Restore DWT registers */
235 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
237 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
239 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
241 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
242 dwt_list[i].function);
244 swjdp_transaction_endcheck(swjdp);
246 register_cache_invalidate(cortex_m3->armv7m.core_cache);
248 /* make sure we have latest dhcsr flags */
249 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
254 static int cortex_m3_examine_debug_reason(struct target *target)
256 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
258 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
259 /* only check the debug reason if we don't know it already */
261 if ((target->debug_reason != DBG_REASON_DBGRQ)
262 && (target->debug_reason != DBG_REASON_SINGLESTEP))
264 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
266 target->debug_reason = DBG_REASON_BREAKPOINT;
267 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
268 target->debug_reason = DBG_REASON_WPTANDBKPT;
270 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
271 target->debug_reason = DBG_REASON_WATCHPOINT;
272 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
273 target->debug_reason = DBG_REASON_BREAKPOINT;
274 else /* EXTERNAL, HALTED */
275 target->debug_reason = DBG_REASON_UNDEFINED;
281 static int cortex_m3_examine_exception_reason(struct target *target)
283 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
284 struct armv7m_common *armv7m = target_to_armv7m(target);
285 struct swjdp_common *swjdp = &armv7m->swjdp_info;
287 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
288 switch (armv7m->exception_number)
292 case 3: /* Hard Fault */
293 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
294 if (except_sr & 0x40000000)
296 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
299 case 4: /* Memory Management */
300 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
301 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
303 case 5: /* Bus Fault */
304 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
305 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
307 case 6: /* Usage Fault */
308 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
310 case 11: /* SVCall */
312 case 12: /* Debug Monitor */
313 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
315 case 14: /* PendSV */
317 case 15: /* SysTick */
323 swjdp_transaction_endcheck(swjdp);
324 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
325 shcsr, except_sr, cfsr, except_ar);
329 static int cortex_m3_debug_entry(struct target *target)
334 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
335 struct armv7m_common *armv7m = &cortex_m3->armv7m;
336 struct swjdp_common *swjdp = &armv7m->swjdp_info;
341 cortex_m3_clear_halt(target);
342 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
344 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
347 /* Examine target state and mode */
348 /* First load register acessible through core debug port*/
349 int num_regs = armv7m->core_cache->num_regs;
351 for (i = 0; i < num_regs; i++)
353 if (!armv7m->core_cache->reg_list[i].valid)
354 armv7m->read_core_reg(target, i);
357 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
358 xPSR = buf_get_u32(r->value, 0, 32);
360 #ifdef ARMV7_GDB_HACKS
361 /* FIXME this breaks on scan chains with more than one Cortex-M3.
362 * Instead, each CM3 should have its own dummy value...
364 /* copy real xpsr reg for gdb, setting thumb bit */
365 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
366 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
367 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
368 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
371 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
375 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
378 /* Are we in an exception handler */
381 armv7m->core_mode = ARMV7M_MODE_HANDLER;
382 armv7m->exception_number = (xPSR & 0x1FF);
386 armv7m->core_mode = buf_get_u32(armv7m->core_cache
387 ->reg_list[ARMV7M_CONTROL].value, 0, 1);
388 armv7m->exception_number = 0;
391 if (armv7m->exception_number)
393 cortex_m3_examine_exception_reason(target);
396 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
397 armv7m_mode_strings[armv7m->core_mode],
398 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
399 target_state_name(target));
401 if (armv7m->post_debug_entry)
402 armv7m->post_debug_entry(target);
407 static int cortex_m3_poll(struct target *target)
410 enum target_state prev_target_state = target->state;
411 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
412 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
414 /* Read from Debug Halting Control and Status Register */
415 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
416 if (retval != ERROR_OK)
418 target->state = TARGET_UNKNOWN;
422 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
424 /* check if still in reset */
425 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
427 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
429 target->state = TARGET_RESET;
434 if (target->state == TARGET_RESET)
436 /* Cannot switch context while running so endreset is
437 * called with target->state == TARGET_RESET
439 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
440 cortex_m3->dcb_dhcsr);
441 cortex_m3_endreset_event(target);
442 target->state = TARGET_RUNNING;
443 prev_target_state = TARGET_RUNNING;
446 if (cortex_m3->dcb_dhcsr & S_HALT)
448 target->state = TARGET_HALTED;
450 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
452 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
455 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
457 if (prev_target_state == TARGET_DEBUG_RUNNING)
460 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
463 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
467 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
468 * How best to model low power modes?
471 if (target->state == TARGET_UNKNOWN)
473 /* check if processor is retiring instructions */
474 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
476 target->state = TARGET_RUNNING;
484 static int cortex_m3_halt(struct target *target)
486 LOG_DEBUG("target->state: %s",
487 target_state_name(target));
489 if (target->state == TARGET_HALTED)
491 LOG_DEBUG("target was already halted");
495 if (target->state == TARGET_UNKNOWN)
497 LOG_WARNING("target was in unknown state when halt was requested");
500 if (target->state == TARGET_RESET)
502 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
504 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
505 return ERROR_TARGET_FAILURE;
509 /* we came here in a reset_halt or reset_init sequence
510 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
512 target->debug_reason = DBG_REASON_DBGRQ;
518 /* Write to Debug Halting Control and Status Register */
519 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
521 target->debug_reason = DBG_REASON_DBGRQ;
526 static int cortex_m3_soft_reset_halt(struct target *target)
528 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
529 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
530 uint32_t dcb_dhcsr = 0;
531 int retval, timeout = 0;
533 /* Enter debug state on reset; see end_reset_event() */
534 mem_ap_write_u32(swjdp, DCB_DEMCR,
535 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
537 /* Request a core-only reset */
538 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
539 AIRCR_VECTKEY | AIRCR_VECTRESET);
540 target->state = TARGET_RESET;
542 /* registers are now invalid */
543 register_cache_invalidate(cortex_m3->armv7m.core_cache);
545 while (timeout < 100)
547 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
548 if (retval == ERROR_OK)
550 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
551 &cortex_m3->nvic_dfsr);
552 if ((dcb_dhcsr & S_HALT)
553 && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
555 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
557 (unsigned) dcb_dhcsr,
558 (unsigned) cortex_m3->nvic_dfsr);
559 cortex_m3_poll(target);
560 /* FIXME restore user's vector catch config */
564 LOG_DEBUG("waiting for system reset-halt, "
565 "DHCSR 0x%08x, %d ms",
566 (unsigned) dcb_dhcsr, timeout);
575 static void cortex_m3_enable_breakpoints(struct target *target)
577 struct breakpoint *breakpoint = target->breakpoints;
579 /* set any pending breakpoints */
582 if (breakpoint->set == 0)
583 cortex_m3_set_breakpoint(target, breakpoint);
584 breakpoint = breakpoint->next;
588 static int cortex_m3_resume(struct target *target, int current,
589 uint32_t address, int handle_breakpoints, int debug_execution)
591 struct armv7m_common *armv7m = target_to_armv7m(target);
592 struct breakpoint *breakpoint = NULL;
596 if (target->state != TARGET_HALTED)
598 LOG_WARNING("target not halted");
599 return ERROR_TARGET_NOT_HALTED;
602 if (!debug_execution)
604 target_free_all_working_areas(target);
605 cortex_m3_enable_breakpoints(target);
606 cortex_m3_enable_watchpoints(target);
611 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
613 /* Disable interrupts */
614 /* We disable interrupts in the PRIMASK register instead of
615 * masking with C_MASKINTS. This is probably the same issue
616 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
617 * in parallel with disabled interrupts can cause local faults
620 * REVISIT this clearly breaks non-debug execution, since the
621 * PRIMASK register state isn't saved/restored... workaround
622 * by never resuming app code after debug execution.
624 buf_set_u32(r->value, 0, 1, 1);
628 /* Make sure we are in Thumb mode */
629 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
630 buf_set_u32(r->value, 24, 1, 1);
635 /* current = 1: continue on current pc, otherwise continue at <address> */
636 r = armv7m->core_cache->reg_list + 15;
639 buf_set_u32(r->value, 0, 32, address);
644 resume_pc = buf_get_u32(r->value, 0, 32);
646 armv7m_restore_context(target);
648 /* the front-end may request us not to handle breakpoints */
649 if (handle_breakpoints)
651 /* Single step past breakpoint at current address */
652 if ((breakpoint = breakpoint_find(target, resume_pc)))
654 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
656 breakpoint->unique_id);
657 cortex_m3_unset_breakpoint(target, breakpoint);
658 cortex_m3_single_step_core(target);
659 cortex_m3_set_breakpoint(target, breakpoint);
664 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
666 target->debug_reason = DBG_REASON_NOTHALTED;
668 /* registers are now invalid */
669 register_cache_invalidate(armv7m->core_cache);
671 if (!debug_execution)
673 target->state = TARGET_RUNNING;
674 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
675 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
679 target->state = TARGET_DEBUG_RUNNING;
680 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
681 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
687 /* int irqstepcount = 0; */
688 static int cortex_m3_step(struct target *target, int current,
689 uint32_t address, int handle_breakpoints)
691 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
692 struct armv7m_common *armv7m = &cortex_m3->armv7m;
693 struct swjdp_common *swjdp = &armv7m->swjdp_info;
694 struct breakpoint *breakpoint = NULL;
695 struct reg *pc = armv7m->core_cache->reg_list + 15;
697 if (target->state != TARGET_HALTED)
699 LOG_WARNING("target not halted");
700 return ERROR_TARGET_NOT_HALTED;
703 /* current = 1: continue on current pc, otherwise continue at <address> */
705 buf_set_u32(pc->value, 0, 32, address);
707 /* the front-end may request us not to handle breakpoints */
708 if (handle_breakpoints) {
709 breakpoint = breakpoint_find(target,
710 buf_get_u32(pc->value, 0, 32));
712 cortex_m3_unset_breakpoint(target, breakpoint);
715 target->debug_reason = DBG_REASON_SINGLESTEP;
717 armv7m_restore_context(target);
719 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
721 /* set step and clear halt */
722 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
723 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
725 /* registers are now invalid */
726 register_cache_invalidate(cortex_m3->armv7m.core_cache);
729 cortex_m3_set_breakpoint(target, breakpoint);
731 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
732 " nvic_icsr = 0x%" PRIx32,
733 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
735 cortex_m3_debug_entry(target);
736 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
738 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
739 " nvic_icsr = 0x%" PRIx32,
740 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
744 static int cortex_m3_assert_reset(struct target *target)
746 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
747 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
750 LOG_DEBUG("target->state: %s",
751 target_state_name(target));
753 enum reset_types jtag_reset_config = jtag_get_reset_config();
756 * We can reset Cortex-M3 targets using just the NVIC without
757 * requiring SRST, getting a SoC reset (or a core-only reset)
758 * instead of a system reset.
760 if (!(jtag_reset_config & RESET_HAS_SRST))
763 /* Enable debug requests */
764 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
765 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
766 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
768 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
770 if (!target->reset_halt)
772 /* Set/Clear C_MASKINTS in a separate operation */
773 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
774 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
775 DBGKEY | C_DEBUGEN | C_HALT);
777 /* clear any debug flags before resuming */
778 cortex_m3_clear_halt(target);
780 /* clear C_HALT in dhcsr reg */
781 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
783 /* Enter debug state on reset, cf. end_reset_event() */
784 mem_ap_write_u32(swjdp, DCB_DEMCR,
785 TRCENA | VC_HARDERR | VC_BUSERR);
789 /* Enter debug state on reset, cf. end_reset_event() */
790 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
791 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
795 * When nRST is asserted on most Stellaris devices, it clears some of
796 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
797 * and OpenOCD depends on those TRMs. So we won't use SRST on those
798 * chips. (Only power-on reset should affect debug state, beyond a
799 * few specified bits; not the chip's nRST input, wired to SRST.)
801 * REVISIT current errata specs don't seem to cover this issue.
802 * Do we have more details than this email?
803 * https://lists.berlios.de/pipermail
804 * /openocd-development/2008-August/003065.html
806 if (strcmp(target->variant, "lm3s") == 0)
808 /* Check for silicon revisions with the issue. */
811 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
813 switch ((did0 >> 16) & 0xff)
816 /* all Sandstorm suffer issue */
822 /* Fury and DustDevil rev A have
823 * this nRST problem. It should
824 * be fixed in rev B silicon.
826 if (((did0 >> 8) & 0xff) == 0)
830 /* Tempest should be fine. */
838 /* default to asserting srst */
839 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
841 jtag_add_reset(1, 1);
845 jtag_add_reset(0, 1);
850 /* Use a standard Cortex-M3 software reset mechanism.
851 * SYSRESETREQ will reset SoC peripherals outside the
852 * core, like watchdog timers, if the SoC wires it up
853 * correctly. Else VECRESET can reset just the core.
855 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
856 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
857 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
860 /* I do not know why this is necessary, but it
861 * fixes strange effects (step/resume cause NMI
862 * after reset) on LM3S6918 -- Michael Schwingen
865 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
869 target->state = TARGET_RESET;
870 jtag_add_sleep(50000);
872 register_cache_invalidate(cortex_m3->armv7m.core_cache);
874 if (target->reset_halt)
877 if ((retval = target_halt(target)) != ERROR_OK)
884 static int cortex_m3_deassert_reset(struct target *target)
886 LOG_DEBUG("target->state: %s",
887 target_state_name(target));
889 /* deassert reset lines */
890 jtag_add_reset(0, 0);
896 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
901 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
902 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
906 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
910 if (cortex_m3->auto_bp_type)
912 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
915 if (breakpoint->type == BKPT_HARD)
917 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
919 if (fp_num >= cortex_m3->fp_num_code)
921 LOG_ERROR("Can not find free FPB Comparator!");
924 breakpoint->set = fp_num + 1;
925 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
926 comparator_list[fp_num].used = 1;
927 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
928 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
929 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
930 if (!cortex_m3->fpb_enabled)
932 LOG_DEBUG("FPB wasn't enabled, do it now");
933 target_write_u32(target, FP_CTRL, 3);
936 else if (breakpoint->type == BKPT_SOFT)
939 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
940 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
944 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
948 breakpoint->set = 0x11; /* Any nice value but 0 */
951 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
952 breakpoint->unique_id,
953 (int)(breakpoint->type),
962 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
965 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
966 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
968 if (!breakpoint->set)
970 LOG_WARNING("breakpoint not set");
974 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
975 breakpoint->unique_id,
976 (int)(breakpoint->type),
981 if (breakpoint->type == BKPT_HARD)
983 int fp_num = breakpoint->set - 1;
984 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
986 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
989 comparator_list[fp_num].used = 0;
990 comparator_list[fp_num].fpcr_value = 0;
991 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
995 /* restore original instruction (kept in target endianness) */
996 if (breakpoint->length == 4)
998 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1005 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1011 breakpoint->set = 0;
1017 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1019 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1021 if (cortex_m3->auto_bp_type)
1023 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1024 #ifdef ARMV7_GDB_HACKS
1025 if (breakpoint->length != 2) {
1026 /* XXX Hack: Replace all breakpoints with length != 2 with
1027 * a hardware breakpoint. */
1028 breakpoint->type = BKPT_HARD;
1029 breakpoint->length = 2;
1034 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1036 LOG_INFO("flash patch comparator requested outside code memory region");
1037 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1040 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1042 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1043 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1046 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1048 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1049 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1052 if ((breakpoint->length != 2))
1054 LOG_INFO("only breakpoints of two bytes length supported");
1055 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1058 if (breakpoint->type == BKPT_HARD)
1059 cortex_m3->fp_code_available--;
1060 cortex_m3_set_breakpoint(target, breakpoint);
1066 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1068 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1070 /* REVISIT why check? FBP can be updated with core running ... */
1071 if (target->state != TARGET_HALTED)
1073 LOG_WARNING("target not halted");
1074 return ERROR_TARGET_NOT_HALTED;
1077 if (cortex_m3->auto_bp_type)
1079 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1082 if (breakpoint->set)
1084 cortex_m3_unset_breakpoint(target, breakpoint);
1087 if (breakpoint->type == BKPT_HARD)
1088 cortex_m3->fp_code_available++;
1094 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1097 uint32_t mask, temp;
1098 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1100 /* watchpoint params were validated earlier */
1102 temp = watchpoint->length;
1109 /* REVISIT Don't fully trust these "not used" records ... users
1110 * may set up breakpoints by hand, e.g. dual-address data value
1111 * watchpoint using comparator #1; comparator #0 matching cycle
1112 * count; send data trace info through ITM and TPIU; etc
1114 struct cortex_m3_dwt_comparator *comparator;
1116 for (comparator = cortex_m3->dwt_comparator_list;
1117 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1118 comparator++, dwt_num++)
1120 if (dwt_num >= cortex_m3->dwt_num_comp)
1122 LOG_ERROR("Can not find free DWT Comparator");
1125 comparator->used = 1;
1126 watchpoint->set = dwt_num + 1;
1128 comparator->comp = watchpoint->address;
1129 target_write_u32(target, comparator->dwt_comparator_address + 0,
1132 comparator->mask = mask;
1133 target_write_u32(target, comparator->dwt_comparator_address + 4,
1136 switch (watchpoint->rw) {
1138 comparator->function = 5;
1141 comparator->function = 6;
1144 comparator->function = 7;
1147 target_write_u32(target, comparator->dwt_comparator_address + 8,
1148 comparator->function);
1150 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1151 watchpoint->unique_id, dwt_num,
1152 (unsigned) comparator->comp,
1153 (unsigned) comparator->mask,
1154 (unsigned) comparator->function);
1159 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1161 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1162 struct cortex_m3_dwt_comparator *comparator;
1165 if (!watchpoint->set)
1167 LOG_WARNING("watchpoint (wpid: %d) not set",
1168 watchpoint->unique_id);
1172 dwt_num = watchpoint->set - 1;
1174 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1175 watchpoint->unique_id, dwt_num,
1176 (unsigned) watchpoint->address);
1178 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1180 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1184 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1185 comparator->used = 0;
1186 comparator->function = 0;
1187 target_write_u32(target, comparator->dwt_comparator_address + 8,
1188 comparator->function);
1190 watchpoint->set = 0;
1196 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1198 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1200 if (cortex_m3->dwt_comp_available < 1)
1202 LOG_DEBUG("no comparators?");
1203 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1206 /* hardware doesn't support data value masking */
1207 if (watchpoint->mask != ~(uint32_t)0) {
1208 LOG_DEBUG("watchpoint value masks not supported");
1209 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1212 /* hardware allows address masks of up to 32K */
1215 for (mask = 0; mask < 16; mask++) {
1216 if ((1u << mask) == watchpoint->length)
1220 LOG_DEBUG("unsupported watchpoint length");
1221 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1223 if (watchpoint->address & ((1 << mask) - 1)) {
1224 LOG_DEBUG("watchpoint address is unaligned");
1225 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1228 /* Caller doesn't seem to be able to describe watching for data
1229 * values of zero; that flags "no value".
1231 * REVISIT This DWT may well be able to watch for specific data
1232 * values. Requires comparator #1 to set DATAVMATCH and match
1233 * the data, and another comparator (DATAVADDR0) matching addr.
1235 if (watchpoint->value) {
1236 LOG_DEBUG("data value watchpoint not YET supported");
1237 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1240 cortex_m3->dwt_comp_available--;
1241 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1247 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1249 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1251 /* REVISIT why check? DWT can be updated with core running ... */
1252 if (target->state != TARGET_HALTED)
1254 LOG_WARNING("target not halted");
1255 return ERROR_TARGET_NOT_HALTED;
1258 if (watchpoint->set)
1260 cortex_m3_unset_watchpoint(target, watchpoint);
1263 cortex_m3->dwt_comp_available++;
1264 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1269 static void cortex_m3_enable_watchpoints(struct target *target)
1271 struct watchpoint *watchpoint = target->watchpoints;
1273 /* set any pending watchpoints */
1276 if (watchpoint->set == 0)
1277 cortex_m3_set_watchpoint(target, watchpoint);
1278 watchpoint = watchpoint->next;
1282 static int cortex_m3_load_core_reg_u32(struct target *target,
1283 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1286 struct armv7m_common *armv7m = target_to_armv7m(target);
1287 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1289 /* NOTE: we "know" here that the register identifiers used
1290 * in the v7m header match the Cortex-M3 Debug Core Register
1291 * Selector values for R0..R15, xPSR, MSP, and PSP.
1295 /* read a normal core register */
1296 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1298 if (retval != ERROR_OK)
1300 LOG_ERROR("JTAG failure %i",retval);
1301 return ERROR_JTAG_DEVICE_ERROR;
1303 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1306 case ARMV7M_PRIMASK:
1307 case ARMV7M_BASEPRI:
1308 case ARMV7M_FAULTMASK:
1309 case ARMV7M_CONTROL:
1310 /* Cortex-M3 packages these four registers as bitfields
1311 * in one Debug Core register. So say r0 and r2 docs;
1312 * it was removed from r1 docs, but still works.
1314 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1318 case ARMV7M_PRIMASK:
1319 *value = buf_get_u32((uint8_t*)value, 0, 1);
1322 case ARMV7M_BASEPRI:
1323 *value = buf_get_u32((uint8_t*)value, 8, 8);
1326 case ARMV7M_FAULTMASK:
1327 *value = buf_get_u32((uint8_t*)value, 16, 1);
1330 case ARMV7M_CONTROL:
1331 *value = buf_get_u32((uint8_t*)value, 24, 2);
1335 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1339 return ERROR_INVALID_ARGUMENTS;
1345 static int cortex_m3_store_core_reg_u32(struct target *target,
1346 enum armv7m_regtype type, uint32_t num, uint32_t value)
1350 struct armv7m_common *armv7m = target_to_armv7m(target);
1351 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1353 #ifdef ARMV7_GDB_HACKS
1354 /* If the LR register is being modified, make sure it will put us
1355 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1356 * hack to deal with the fact that gdb will sometimes "forge"
1357 * return addresses, and doesn't set the LSB correctly (i.e., when
1358 * printing expressions containing function calls, it sets LR = 0.)
1359 * Valid exception return codes have bit 0 set too.
1361 if (num == ARMV7M_R14)
1365 /* NOTE: we "know" here that the register identifiers used
1366 * in the v7m header match the Cortex-M3 Debug Core Register
1367 * Selector values for R0..R15, xPSR, MSP, and PSP.
1371 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1372 if (retval != ERROR_OK)
1376 LOG_ERROR("JTAG failure %i", retval);
1377 r = armv7m->core_cache->reg_list + num;
1378 r->dirty = r->valid;
1379 return ERROR_JTAG_DEVICE_ERROR;
1381 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1384 case ARMV7M_PRIMASK:
1385 case ARMV7M_BASEPRI:
1386 case ARMV7M_FAULTMASK:
1387 case ARMV7M_CONTROL:
1388 /* Cortex-M3 packages these four registers as bitfields
1389 * in one Debug Core register. So say r0 and r2 docs;
1390 * it was removed from r1 docs, but still works.
1392 cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
1396 case ARMV7M_PRIMASK:
1397 buf_set_u32((uint8_t*)®, 0, 1, value);
1400 case ARMV7M_BASEPRI:
1401 buf_set_u32((uint8_t*)®, 8, 8, value);
1404 case ARMV7M_FAULTMASK:
1405 buf_set_u32((uint8_t*)®, 16, 1, value);
1408 case ARMV7M_CONTROL:
1409 buf_set_u32((uint8_t*)®, 24, 2, value);
1413 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1415 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1419 return ERROR_INVALID_ARGUMENTS;
1425 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1426 uint32_t size, uint32_t count, uint8_t *buffer)
1428 struct armv7m_common *armv7m = target_to_armv7m(target);
1429 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1430 int retval = ERROR_INVALID_ARGUMENTS;
1432 /* cortex_m3 handles unaligned memory access */
1433 if (count && buffer) {
1436 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1439 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1442 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1450 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1451 uint32_t size, uint32_t count, uint8_t *buffer)
1453 struct armv7m_common *armv7m = target_to_armv7m(target);
1454 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1455 int retval = ERROR_INVALID_ARGUMENTS;
1457 if (count && buffer) {
1460 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1463 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1466 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1474 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1475 uint32_t count, uint8_t *buffer)
1477 return cortex_m3_write_memory(target, address, 4, count, buffer);
1480 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1481 struct target *target)
1483 armv7m_build_reg_cache(target);
1487 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1488 * on r/w if the core is not running, and clear on resume or reset ... or
1489 * at least, in a post_restore_context() method.
1492 struct dwt_reg_state {
1493 struct target *target;
1495 uint32_t value; /* scratch/cache */
1498 static int cortex_m3_dwt_get_reg(struct reg *reg)
1500 struct dwt_reg_state *state = reg->arch_info;
1502 return target_read_u32(state->target, state->addr, &state->value);
1505 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1507 struct dwt_reg_state *state = reg->arch_info;
1509 return target_write_u32(state->target, state->addr,
1510 buf_get_u32(buf, 0, reg->size));
1519 static struct dwt_reg dwt_base_regs[] = {
1520 { DWT_CTRL, "dwt_ctrl", 32, },
1521 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1522 * increments while the core is asleep.
1524 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1525 /* plus some 8 bit counters, useful for profiling with TPIU */
1528 static struct dwt_reg dwt_comp[] = {
1529 #define DWT_COMPARATOR(i) \
1530 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1531 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1532 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1537 #undef DWT_COMPARATOR
1540 static const struct reg_arch_type dwt_reg_type = {
1541 .get = cortex_m3_dwt_get_reg,
1542 .set = cortex_m3_dwt_set_reg,
1546 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1548 struct dwt_reg_state *state;
1550 state = calloc(1, sizeof *state);
1553 state->addr = d->addr;
1558 r->value = &state->value;
1559 r->arch_info = state;
1560 r->type = &dwt_reg_type;
1564 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1567 struct reg_cache *cache;
1568 struct cortex_m3_dwt_comparator *comparator;
1571 target_read_u32(target, DWT_CTRL, &dwtcr);
1573 LOG_DEBUG("no DWT");
1577 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1578 cm3->dwt_comp_available = cm3->dwt_num_comp;
1579 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1580 sizeof(struct cortex_m3_dwt_comparator));
1581 if (!cm3->dwt_comparator_list) {
1583 cm3->dwt_num_comp = 0;
1584 LOG_ERROR("out of mem");
1588 cache = calloc(1, sizeof *cache);
1591 free(cm3->dwt_comparator_list);
1594 cache->name = "cortex-m3 dwt registers";
1595 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1596 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1597 if (!cache->reg_list) {
1602 for (reg = 0; reg < 2; reg++)
1603 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1604 dwt_base_regs + reg);
1606 comparator = cm3->dwt_comparator_list;
1607 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1610 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1611 for (j = 0; j < 3; j++, reg++)
1612 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1613 dwt_comp + 3 * i + j);
1616 *register_get_last_cache_p(&target->reg_cache) = cache;
1617 cm3->dwt_cache = cache;
1619 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1620 dwtcr, cm3->dwt_num_comp,
1621 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1623 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1624 * implement single-address data value watchpoints ... so we
1625 * won't need to check it later, when asked to set one up.
1629 static int cortex_m3_examine(struct target *target)
1632 uint32_t cpuid, fpcr;
1634 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1635 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1637 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1640 if (!target_was_examined(target))
1642 target_set_examined(target);
1644 /* Read from Device Identification Registers */
1645 retval = target_read_u32(target, CPUID, &cpuid);
1646 if (retval != ERROR_OK)
1649 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1650 LOG_DEBUG("CORTEX-M3 processor detected");
1651 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1653 /* NOTE: FPB and DWT are both optional. */
1656 target_read_u32(target, FP_CTRL, &fpcr);
1657 cortex_m3->auto_bp_type = 1;
1658 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1659 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1660 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1661 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1662 cortex_m3->fpb_enabled = fpcr & 1;
1663 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1665 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1666 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1668 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1671 cortex_m3_dwt_setup(cortex_m3, target);
1673 /* These hardware breakpoints only work for code in flash! */
1674 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1675 target_name(target),
1676 cortex_m3->fp_num_code,
1677 cortex_m3->dwt_num_comp);
1683 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1687 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1688 *ctrl = (uint8_t)dcrdr;
1689 *value = (uint8_t)(dcrdr >> 8);
1691 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1693 /* write ack back to software dcc register
1694 * signify we have read data */
1695 if (dcrdr & (1 << 0))
1698 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1704 static int cortex_m3_target_request_data(struct target *target,
1705 uint32_t size, uint8_t *buffer)
1707 struct armv7m_common *armv7m = target_to_armv7m(target);
1708 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1713 for (i = 0; i < (size * 4); i++)
1715 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1722 static int cortex_m3_handle_target_request(void *priv)
1724 struct target *target = priv;
1725 if (!target_was_examined(target))
1727 struct armv7m_common *armv7m = target_to_armv7m(target);
1728 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1730 if (!target->dbg_msg_enabled)
1733 if (target->state == TARGET_RUNNING)
1738 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1740 /* check if we have data */
1741 if (ctrl & (1 << 0))
1745 /* we assume target is quick enough */
1747 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1748 request |= (data << 8);
1749 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1750 request |= (data << 16);
1751 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1752 request |= (data << 24);
1753 target_request(target, request);
1760 static int cortex_m3_init_arch_info(struct target *target,
1761 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1764 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1766 armv7m_init_arch_info(target, armv7m);
1768 /* prepare JTAG information for the new target */
1769 cortex_m3->jtag_info.tap = tap;
1770 cortex_m3->jtag_info.scann_size = 4;
1772 armv7m->swjdp_info.dp_select_value = -1;
1773 armv7m->swjdp_info.ap_csw_value = -1;
1774 armv7m->swjdp_info.ap_tar_value = -1;
1775 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1776 armv7m->swjdp_info.memaccess_tck = 8;
1777 armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1779 /* register arch-specific functions */
1780 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1782 armv7m->post_debug_entry = NULL;
1784 armv7m->pre_restore_context = NULL;
1785 armv7m->post_restore_context = NULL;
1787 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1788 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1790 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1792 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1800 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1802 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1804 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1805 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1810 /*--------------------------------------------------------------------------*/
1812 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1813 struct cortex_m3_common *cm3)
1815 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1816 command_print(cmd_ctx, "target is not a Cortex-M3");
1817 return ERROR_TARGET_INVALID;
1823 * Only stuff below this line should need to verify that its target
1824 * is a Cortex-M3. Everything else should have indirected through the
1825 * cortexm3_target structure, which is only used with CM3 targets.
1829 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1830 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1831 * that *only* Thumb2 disassembly matters. There are also some small
1832 * additions to Thumb2 that are specific to ARMv7-M.
1834 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1837 struct target *target = get_current_target(CMD_CTX);
1838 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1840 unsigned long count = 1;
1841 struct arm_instruction cur_instruction;
1843 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1844 if (retval != ERROR_OK)
1850 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1853 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1856 command_print(CMD_CTX,
1857 "usage: cortex_m3 disassemble <address> [<count>]");
1862 retval = thumb2_opcode(target, address, &cur_instruction);
1863 if (retval != ERROR_OK)
1865 command_print(CMD_CTX, "%s", cur_instruction.text);
1866 address += cur_instruction.instruction_size;
1872 static const struct {
1876 { "hard_err", VC_HARDERR, },
1877 { "int_err", VC_INTERR, },
1878 { "bus_err", VC_BUSERR, },
1879 { "state_err", VC_STATERR, },
1880 { "chk_err", VC_CHKERR, },
1881 { "nocp_err", VC_NOCPERR, },
1882 { "mm_err", VC_MMERR, },
1883 { "reset", VC_CORERESET, },
1886 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1888 struct target *target = get_current_target(CMD_CTX);
1889 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1890 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1891 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1895 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1896 if (retval != ERROR_OK)
1899 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1904 if (CMD_ARGC == 1) {
1905 if (strcmp(CMD_ARGV[0], "all") == 0) {
1906 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1907 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1908 | VC_MMERR | VC_CORERESET;
1910 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1914 while (CMD_ARGC-- > 0) {
1916 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1917 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1919 catch |= vec_ids[i].mask;
1922 if (i == ARRAY_SIZE(vec_ids)) {
1923 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1924 return ERROR_INVALID_ARGUMENTS;
1931 /* write, but don't assume it stuck */
1932 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1933 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1936 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1938 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1939 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1945 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1947 struct target *target = get_current_target(CMD_CTX);
1948 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1951 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1952 if (retval != ERROR_OK)
1955 if (target->state != TARGET_HALTED)
1957 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1964 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
1965 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
1966 uint32_t mask_off = enable ? 0 : C_MASKINTS;
1967 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
1970 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1971 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1976 static const struct command_registration cortex_m3_exec_command_handlers[] = {
1978 .name = "disassemble",
1979 .handler = &handle_cortex_m3_disassemble_command,
1980 .mode = COMMAND_EXEC,
1981 .help = "disassemble Thumb2 instructions",
1982 .usage = "<address> [<count>]",
1986 .handler = &handle_cortex_m3_mask_interrupts_command,
1987 .mode = COMMAND_EXEC,
1988 .help = "mask cortex_m3 interrupts",
1989 .usage = "['on'|'off']",
1992 .name = "vector_catch",
1993 .handler = &handle_cortex_m3_vector_catch_command,
1994 .mode = COMMAND_EXEC,
1995 .help = "catch hardware vectors",
1996 .usage = "['all'|'none'|<list>]",
1998 COMMAND_REGISTRATION_DONE
2000 static const struct command_registration cortex_m3_command_handlers[] = {
2002 .chain = armv7m_command_handlers,
2005 .name = "cortex_m3",
2006 .mode = COMMAND_EXEC,
2007 .help = "Cortex-M3 command group",
2008 .chain = cortex_m3_exec_command_handlers,
2010 COMMAND_REGISTRATION_DONE
2013 struct target_type cortexm3_target =
2015 .name = "cortex_m3",
2017 .poll = cortex_m3_poll,
2018 .arch_state = armv7m_arch_state,
2020 .target_request_data = cortex_m3_target_request_data,
2022 .halt = cortex_m3_halt,
2023 .resume = cortex_m3_resume,
2024 .step = cortex_m3_step,
2026 .assert_reset = cortex_m3_assert_reset,
2027 .deassert_reset = cortex_m3_deassert_reset,
2028 .soft_reset_halt = cortex_m3_soft_reset_halt,
2030 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2032 .read_memory = cortex_m3_read_memory,
2033 .write_memory = cortex_m3_write_memory,
2034 .bulk_write_memory = cortex_m3_bulk_write_memory,
2035 .checksum_memory = armv7m_checksum_memory,
2036 .blank_check_memory = armv7m_blank_check_memory,
2038 .run_algorithm = armv7m_run_algorithm,
2040 .add_breakpoint = cortex_m3_add_breakpoint,
2041 .remove_breakpoint = cortex_m3_remove_breakpoint,
2042 .add_watchpoint = cortex_m3_add_watchpoint,
2043 .remove_watchpoint = cortex_m3_remove_watchpoint,
2045 .commands = cortex_m3_command_handlers,
2046 .target_create = cortex_m3_target_create,
2047 .init_target = cortex_m3_init_target,
2048 .examine = cortex_m3_examine,