1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 /***************************************************************************
22 * CoreSight (Light?) SerialWireJtagDebugPort *
24 * CoreSightâ„¢ DAP-Lite TRM, ARM DDI 0316A *
25 * Cortex-M3â„¢ TRM, ARM DDI 0337C *
27 ***************************************************************************/
32 #include "replacements.h"
34 #include "cortex_m3.h"
35 #include "cortex_swjdp.h"
42 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
43 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
44 * result checking until swjdp_end_transaction()
45 * This must be done before using or deallocating any return variables.
46 * swjdp->trans_mode == TRANS_MODE_ATOMIC
47 * All reads and writes to the AHB bus are checked for valid completion, and return values
48 * are immediatley available.
51 /***************************************************************************
53 * DPACC and APACC scanchain access through JTAG-DR *
55 ***************************************************************************/
57 /* Scan out and in from target ordered u8 buffers */
58 int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
60 scan_field_t fields[2];
63 jtag_add_end_state(TAP_RTI);
64 arm_jtag_set_instr(jtag_info, instr, NULL);
66 fields[0].device = jtag_info->chain_pos;
67 fields[0].num_bits = 3;
68 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
69 fields[0].out_value = &out_addr_buf;
70 fields[0].out_mask = NULL;
71 fields[0].in_value = ack;
72 fields[0].in_check_value = NULL;
73 fields[0].in_check_mask = NULL;
74 fields[0].in_handler = NULL;
75 fields[0].in_handler_priv = NULL;
77 fields[1].device = jtag_info->chain_pos;
78 fields[1].num_bits = 32;
79 fields[1].out_value = outvalue;
80 fields[1].out_mask = NULL;
81 fields[1].in_value = invalue;
82 fields[1].in_handler = NULL;
83 fields[1].in_handler_priv = NULL;
84 fields[1].in_check_value = NULL;
85 fields[1].in_check_mask = NULL;
87 jtag_add_dr_scan(2, fields, -1);
92 /* Scan out and in from host ordered u32 variables */
93 int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
95 scan_field_t fields[2];
99 jtag_add_end_state(TAP_RTI);
100 arm_jtag_set_instr(jtag_info, instr, NULL);
102 fields[0].device = jtag_info->chain_pos;
103 fields[0].num_bits = 3;
104 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
105 fields[0].out_value = &out_addr_buf;
106 fields[0].out_mask = NULL;
107 fields[0].in_value = ack;
108 fields[0].in_check_value = NULL;
109 fields[0].in_check_mask = NULL;
110 fields[0].in_handler = NULL;
111 fields[0].in_handler_priv = NULL;
113 fields[1].device = jtag_info->chain_pos;
114 fields[1].num_bits = 32;
115 buf_set_u32(out_value_buf, 0, 32, outvalue);
116 fields[1].out_value = out_value_buf;
117 fields[1].out_mask = NULL;
118 fields[1].in_value = NULL;
121 fields[1].in_handler = arm_jtag_buf_to_u32;
122 fields[1].in_handler_priv = invalue;
126 fields[1].in_handler = NULL;
127 fields[1].in_handler_priv = NULL;
129 fields[1].in_check_value = NULL;
130 fields[1].in_check_mask = NULL;
132 jtag_add_dr_scan(2, fields, -1);
137 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
138 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
140 swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
141 if ((RnW == DPAP_READ) && (invalue != NULL))
143 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
146 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
147 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
149 return swjdp_transaction_endcheck(swjdp);
155 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
157 swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
158 if ((RnW==DPAP_READ) && (invalue != NULL))
160 swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
163 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
164 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
166 return swjdp_transaction_endcheck(swjdp);
172 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
177 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
178 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
179 jtag_execute_queue();
181 swjdp->ack = swjdp->ack & 0x7;
183 while (swjdp->ack != 2)
190 LOG_WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
191 return ERROR_JTAG_DEVICE_ERROR;
196 LOG_WARNING("Invalid ACK in SWJDP transaction");
197 return ERROR_JTAG_DEVICE_ERROR;
200 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
201 jtag_execute_queue();
202 swjdp->ack = swjdp->ack & 0x7;
205 /* Check for STICKYERR and STICKYORUN */
206 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
208 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
209 /* Check power to debug regions */
210 if ((ctrlstat & 0xf0000000) != 0xf0000000)
212 ahbap_debugport_init(swjdp);
216 u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
218 if (ctrlstat & SSTICKYORUN)
219 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
221 if (ctrlstat & SSTICKYERR)
222 LOG_ERROR("SWJ-DP STICKY ERROR");
224 /* Clear Sticky Error Bits */
225 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
226 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
227 jtag_execute_queue();
229 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
231 /* Can we find out the reason for the error ?? */
232 ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
233 ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
234 ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
235 ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
236 LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
238 jtag_execute_queue();
239 return ERROR_JTAG_DEVICE_ERROR;
245 /***************************************************************************
247 * DP and AHB-AP register access through APACC and DPACC *
249 ***************************************************************************/
251 int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
253 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
256 int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
258 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
261 int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
264 select = (reg_addr & 0xFF0000F0);
266 if (select != swjdp->dp_select_value)
268 swjdp_write_dpacc(swjdp, select, DP_SELECT);
269 swjdp->dp_select_value = select;
275 int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
277 swjdp_bankselect_apacc(swjdp, reg_addr);
278 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
283 int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
285 swjdp_bankselect_apacc(swjdp, reg_addr);
286 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
290 int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
294 buf_set_u32(out_value_buf, 0, 32, value);
295 swjdp_bankselect_apacc(swjdp, reg_addr);
296 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
301 int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
303 swjdp_bankselect_apacc(swjdp, reg_addr);
304 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
309 /***************************************************************************
311 * AHB-AP access to memory and system registers on AHB bus *
313 ***************************************************************************/
315 int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
317 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
318 if (csw != swjdp->ap_csw_value)
320 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
321 ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
322 swjdp->ap_csw_value = csw;
324 if (tar != swjdp->ap_tar_value)
326 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
327 ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
328 swjdp->ap_tar_value = tar;
330 if (csw & CSW_ADDRINC_MASK)
332 /* Do not cache TAR value when autoincrementing */
333 swjdp->ap_tar_value = -1;
338 /*****************************************************************************
340 * ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
342 * Read a u32 value from memory or system register *
343 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
344 * but with less overhead *
345 *****************************************************************************/
346 int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
348 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
350 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
351 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
356 int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
358 ahbap_read_system_u32(swjdp, address, value);
360 return swjdp_transaction_endcheck(swjdp);
363 /*****************************************************************************
365 * ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
367 * Write a u32 value to memory or system register *
369 *****************************************************************************/
370 int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
372 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
374 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
375 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
380 int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
382 ahbap_write_system_u32(swjdp, address, value);
384 return swjdp_transaction_endcheck(swjdp);
387 /*****************************************************************************
389 * ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
391 * Write a buffer in target order (little endian) *
393 *****************************************************************************/
394 int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
397 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
399 u8* pBuffer = buffer;
401 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
406 /* if we have an unaligned access - reorder data */
409 for (writecount = 0; writecount < count; writecount++)
412 outvalue = *((u32*)pBuffer);
414 for (i = 0; i < 4; i++ )
416 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
426 /* Adjust to write blocks within 4K aligned boundaries */
427 blocksize = (0x1000 - (0xFFF & address)) >> 2;
428 if (wcount < blocksize)
431 /* handle unaligned data at 4k boundary */
435 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
437 for (writecount = 0; writecount < blocksize; writecount++)
439 ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
442 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
444 wcount = wcount - blocksize;
445 address = address + 4 * blocksize;
446 buffer = buffer + 4 * blocksize;
455 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
456 return ERROR_JTAG_DEVICE_ERROR;
463 int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
466 int retval = ERROR_OK;
467 int wcount, blocksize, writecount, i;
469 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
477 /* Adjust to read within 4K block boundaries */
478 blocksize = (0x1000 - (0xFFF & address)) >> 1;
480 if (wcount < blocksize)
483 /* handle unaligned data at 4k boundary */
487 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
488 writecount = blocksize;
492 nbytes = MIN((writecount << 1), 4);
496 if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
498 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
499 return ERROR_JTAG_DEVICE_ERROR;
502 address += nbytes >> 1;
506 outvalue = *((u32*)buffer);
508 for (i = 0; i < nbytes; i++ )
510 *((u8*)buffer + (address & 0x3)) = outvalue;
515 outvalue = *((u32*)buffer);
516 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
517 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
519 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
520 return ERROR_JTAG_DEVICE_ERROR;
524 buffer += nbytes >> 1;
525 writecount -= nbytes >> 1;
527 } while (writecount);
534 int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
537 int retval = ERROR_OK;
540 return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
542 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
546 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
547 outvalue = *((u16*)buffer) << 8 * (address & 0x3);
548 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
549 retval = swjdp_transaction_endcheck(swjdp);
558 int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
561 int retval = ERROR_OK;
562 int wcount, blocksize, writecount, i;
564 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
572 /* Adjust to read within 4K block boundaries */
573 blocksize = (0x1000 - (0xFFF & address));
575 if (wcount < blocksize)
578 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
579 writecount = blocksize;
583 nbytes = MIN(writecount, 4);
587 if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
589 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
590 return ERROR_JTAG_DEVICE_ERROR;
597 outvalue = *((u32*)buffer);
599 for (i = 0; i < nbytes; i++ )
601 *((u8*)buffer + (address & 0x3)) = outvalue;
606 outvalue = *((u32*)buffer);
607 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
608 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
610 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
611 return ERROR_JTAG_DEVICE_ERROR;
616 writecount -= nbytes;
618 } while (writecount);
625 int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
628 int retval = ERROR_OK;
631 return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
633 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
637 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
638 outvalue = *((u8*)buffer) << 8 * (address & 0x3);
639 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
640 retval = swjdp_transaction_endcheck(swjdp);
649 /*********************************************************************************
651 * ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
653 * Read block fast in target order (little endian) into a buffer *
655 **********************************************************************************/
656 int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
658 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
660 u8* pBuffer = buffer;
662 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
669 /* Adjust to read within 4K block boundaries */
670 blocksize = (0x1000 - (0xFFF & address)) >> 2;
671 if (wcount < blocksize)
674 /* handle unaligned data at 4k boundary */
678 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
680 /* Scan out first read */
681 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
682 for (readcount = 0; readcount < blocksize - 1; readcount++)
684 /* Scan out read instruction and scan in previous value */
685 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
688 /* Scan in last value */
689 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
690 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
692 wcount = wcount - blocksize;
693 address += 4 * blocksize;
694 buffer += 4 * blocksize;
703 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
704 return ERROR_JTAG_DEVICE_ERROR;
708 /* if we have an unaligned access - reorder data */
711 for (readcount = 0; readcount < count; readcount++)
714 u32 data = *((u32*)pBuffer);
716 for (i = 0; i < 4; i++ )
718 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
728 int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
731 int retval = ERROR_OK;
732 int wcount, blocksize, readcount, i;
734 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
742 /* Adjust to read within 4K block boundaries */
743 blocksize = (0x1000 - (0xFFF & address)) >> 1;
744 if (wcount < blocksize)
747 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
749 /* handle unaligned data at 4k boundary */
752 readcount = blocksize;
756 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
757 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
759 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
760 return ERROR_JTAG_DEVICE_ERROR;
763 nbytes = MIN((readcount << 1), 4);
765 for (i = 0; i < nbytes; i++ )
767 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
772 readcount -= (nbytes >> 1);
780 int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
783 int retval = ERROR_OK;
786 return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
788 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
792 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
793 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
794 retval = swjdp_transaction_endcheck(swjdp);
797 for (i = 0; i < 2; i++ )
799 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
806 *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
816 int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
819 int retval = ERROR_OK;
820 int wcount, blocksize, readcount, i;
822 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
830 /* Adjust to read within 4K block boundaries */
831 blocksize = (0x1000 - (0xFFF & address));
833 if (wcount < blocksize)
836 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
837 readcount = blocksize;
841 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
842 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
844 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
845 return ERROR_JTAG_DEVICE_ERROR;
848 nbytes = MIN(readcount, 4);
850 for (i = 0; i < nbytes; i++ )
852 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
865 int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
868 int retval = ERROR_OK;
871 return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
873 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
877 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
878 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
879 retval = swjdp_transaction_endcheck(swjdp);
880 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
889 int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
894 /* because the DCB_DCRDR is used for the emulated dcc channel
895 * we gave to save/restore the DCB_DCRDR when used */
897 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
899 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
901 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
902 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
903 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
905 /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
906 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
907 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
909 retval = swjdp_transaction_endcheck(swjdp);
910 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
914 int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
919 /* because the DCB_DCRDR is used for the emulated dcc channel
920 * we gave to save/restore the DCB_DCRDR when used */
922 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
924 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
926 /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
927 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
928 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
930 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
931 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
932 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
934 retval = swjdp_transaction_endcheck(swjdp);
935 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
939 int ahbap_debugport_init(swjdp_common_t *swjdp)
941 u32 idreg, romaddr, dummy;
948 swjdp->ap_csw_value = -1;
949 swjdp->ap_tar_value = -1;
950 swjdp->trans_mode = TRANS_MODE_ATOMIC;
951 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
952 swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
953 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
955 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
957 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
958 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
959 if ((retval=jtag_execute_queue())!=ERROR_OK)
962 /* Check that we have debug power domains activated */
963 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
965 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
966 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
967 if ((retval=jtag_execute_queue())!=ERROR_OK)
972 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
974 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
975 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
976 if ((retval=jtag_execute_queue())!=ERROR_OK)
981 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
982 /* With debug power on we can activate OVERRUN checking */
983 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
984 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
985 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
987 ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
988 ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
990 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);