1 /***************************************************************************
2 * Copyright (C) 2018 by Square, Inc. *
3 * Steven Stallion <stallion@squareup.com> *
4 * James Zhao <hjz@squareup.com> *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
18 ***************************************************************************/
20 #ifndef OPENOCD_TARGET_ESIRISC_REGS_H
21 #define OPENOCD_TARGET_ESIRISC_REGS_H
23 enum esirisc_reg_num {
117 #define CSR_THREAD 0x00
118 #define CSR_INTERRUPT 0x01
119 #define CSR_DEBUG 0x04
120 #define CSR_CONFIG 0x05
121 #define CSR_TRACE 0x09
124 #define CSR_THREAD_TC 0x00 /* Thread Control */
125 #define CSR_THREAD_PC 0x01 /* Program Counter */
126 #define CSR_THREAD_CAS 0x02 /* Comparison & Arithmetic Status */
127 #define CSR_THREAD_AC 0x03 /* Arithmetic Control */
128 #define CSR_THREAD_LF 0x04 /* Locked Flag */
129 #define CSR_THREAD_LA 0x05 /* Locked Address */
130 #define CSR_THREAD_ETA 0x07 /* Exception Table Address */
131 #define CSR_THREAD_ETC 0x08 /* Exception TC */
132 #define CSR_THREAD_EPC 0x09 /* Exception PC */
133 #define CSR_THREAD_ECAS 0x0a /* Exception CAS */
134 #define CSR_THREAD_EID 0x0b /* Exception ID */
135 #define CSR_THREAD_ED 0x0c /* Exception Data */
138 #define CSR_INTERRUPT_IP 0x00 /* Interrupt Pending */
139 #define CSR_INTERRUPT_IA 0x01 /* Interrupt Acknowledge */
140 #define CSR_INTERRUPT_IM 0x02 /* Interrupt Mask */
141 #define CSR_INTERRUPT_IS 0x03 /* Interrupt Sense */
142 #define CSR_INTERRUPT_IT 0x04 /* Interrupt Trigger */
145 #define CSR_DEBUG_DC 0x00 /* Debug Control */
146 #define CSR_DEBUG_IBC 0x01 /* Instruction Breakpoint Control */
147 #define CSR_DEBUG_DBC 0x02 /* Data Breakpoint Control */
148 #define CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */
149 #define CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */
150 #define CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */
151 #define CSR_DEBUG_IBAn 0x08 /* Instruction Breakpoint Address [0..7] */
152 #define CSR_DEBUG_DBAn 0x10 /* Data Breakpoint Address [0..7] */
154 /* Configuration CSRs */
155 #define CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */
156 #define CSR_CONFIG_ARCH1 0x01 /* Architectural Configuration 1 */
157 #define CSR_CONFIG_ARCH2 0x02 /* Architectural Configuration 2 */
158 #define CSR_CONFIG_ARCH3 0x03 /* Architectural Configuration 3 */
159 #define CSR_CONFIG_MEM 0x04 /* Memory Configuration */
160 #define CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */
161 #define CSR_CONFIG_DC 0x06 /* Data Cache Configuration */
162 #define CSR_CONFIG_INT 0x07 /* Interrupt Configuration */
163 #define CSR_CONFIG_ISAn 0x08 /* Instruction Set Configuration [0..6] */
164 #define CSR_CONFIG_DBG 0x0f /* Debug Configuration */
165 #define CSR_CONFIG_MID 0x10 /* Manufacturer ID */
166 #define CSR_CONFIG_REV 0x11 /* Revision Number */
167 #define CSR_CONFIG_MPID 0x12 /* Mulitprocessor ID */
168 #define CSR_CONFIG_FREQn 0x13 /* Frequency [0..2] */
169 #define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */
172 #define CSR_TRACE_CONTROL 0x00
173 #define CSR_TRACE_STATUS 0x01
174 #define CSR_TRACE_BUFFER_START 0x02
175 #define CSR_TRACE_BUFFER_END 0x03
176 #define CSR_TRACE_BUFFER_CUR 0x04
177 #define CSR_TRACE_TRIGGER 0x05
178 #define CSR_TRACE_START_DATA 0x06
179 #define CSR_TRACE_START_MASK 0x07
180 #define CSR_TRACE_STOP_DATA 0x08
181 #define CSR_TRACE_STOP_MASK 0x09
182 #define CSR_TRACE_DELAY 0x0a
184 #endif /* OPENOCD_TARGET_ESIRISC_REGS_H */