1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 static char* etb_reg_list[] =
35 "ETB_ram_read_pointer",
36 "ETB_ram_write_pointer",
37 "ETB_trigger_counter",
41 static int etb_reg_arch_type = -1;
43 static int etb_get_reg(reg_t *reg);
45 static int etb_set_instr(etb_t *etb, uint32_t new_instr)
53 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
58 field.num_bits = tap->ir_length;
59 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
60 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
62 field.in_value = NULL;
64 jtag_add_ir_scan(1, &field, jtag_get_end_state());
66 free(field.out_value);
72 static int etb_scann(etb_t *etb, uint32_t new_scan_chain)
74 if (etb->cur_scan_chain != new_scan_chain)
80 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
81 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
83 field.in_value = NULL;
85 /* select INTEST instruction */
86 etb_set_instr(etb, 0x2);
87 jtag_add_dr_scan(1, &field, jtag_get_end_state());
89 etb->cur_scan_chain = new_scan_chain;
91 free(field.out_value);
97 static int etb_read_reg_w_check(reg_t *, uint8_t *, uint8_t *);
98 static int etb_set_reg_w_exec(reg_t *, uint8_t *);
100 static int etb_read_reg(reg_t *reg)
102 return etb_read_reg_w_check(reg, NULL, NULL);
105 static int etb_get_reg(reg_t *reg)
109 if ((retval = etb_read_reg(reg)) != ERROR_OK)
111 LOG_ERROR("BUG: error scheduling ETB register read");
115 if ((retval = jtag_execute_queue()) != ERROR_OK)
117 LOG_ERROR("ETB register read failed");
124 reg_cache_t* etb_build_reg_cache(etb_t *etb)
126 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
127 reg_t *reg_list = NULL;
128 etb_reg_t *arch_info = NULL;
132 /* register a register arch-type for etm registers only once */
133 if (etb_reg_arch_type == -1)
134 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
136 /* the actual registers are kept in two arrays */
137 reg_list = calloc(num_regs, sizeof(reg_t));
138 arch_info = calloc(num_regs, sizeof(etb_reg_t));
140 /* fill in values for the reg cache */
141 reg_cache->name = "etb registers";
142 reg_cache->next = NULL;
143 reg_cache->reg_list = reg_list;
144 reg_cache->num_regs = num_regs;
146 /* set up registers */
147 for (i = 0; i < num_regs; i++)
149 reg_list[i].name = etb_reg_list[i];
150 reg_list[i].size = 32;
151 reg_list[i].dirty = 0;
152 reg_list[i].valid = 0;
153 reg_list[i].bitfield_desc = NULL;
154 reg_list[i].num_bitfields = 0;
155 reg_list[i].value = calloc(1, 4);
156 reg_list[i].arch_info = &arch_info[i];
157 reg_list[i].arch_type = etb_reg_arch_type;
158 reg_list[i].size = 32;
159 arch_info[i].addr = i;
160 arch_info[i].etb = etb;
166 static void etb_getbuf(jtag_callback_data_t arg)
168 uint8_t *in = (uint8_t *)arg;
170 *((uint32_t *)in) = buf_get_u32(in, 0, 32);
174 static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames)
176 scan_field_t fields[3];
179 jtag_set_end_state(TAP_IDLE);
181 etb_set_instr(etb, 0xc);
183 fields[0].tap = etb->tap;
184 fields[0].num_bits = 32;
185 fields[0].out_value = NULL;
186 fields[0].in_value = NULL;
188 fields[1].tap = etb->tap;
189 fields[1].num_bits = 7;
190 fields[1].out_value = malloc(1);
191 buf_set_u32(fields[1].out_value, 0, 7, 4);
192 fields[1].in_value = NULL;
194 fields[2].tap = etb->tap;
195 fields[2].num_bits = 1;
196 fields[2].out_value = malloc(1);
197 buf_set_u32(fields[2].out_value, 0, 1, 0);
198 fields[2].in_value = NULL;
200 jtag_add_dr_scan(3, fields, jtag_get_end_state());
202 for (i = 0; i < num_frames; i++)
204 /* ensure nR/W reamins set to read */
205 buf_set_u32(fields[2].out_value, 0, 1, 0);
207 /* address remains set to 0x4 (RAM data) until we read the last frame */
208 if (i < num_frames - 1)
209 buf_set_u32(fields[1].out_value, 0, 7, 4);
211 buf_set_u32(fields[1].out_value, 0, 7, 0);
213 fields[0].in_value = (uint8_t *)(data + i);
214 jtag_add_dr_scan(3, fields, jtag_get_end_state());
216 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
219 jtag_execute_queue();
221 free(fields[1].out_value);
222 free(fields[2].out_value);
227 static int etb_read_reg_w_check(reg_t *reg,
228 uint8_t* check_value, uint8_t* check_mask)
230 etb_reg_t *etb_reg = reg->arch_info;
231 uint8_t reg_addr = etb_reg->addr & 0x7f;
232 scan_field_t fields[3];
234 LOG_DEBUG("%i", (int)(etb_reg->addr));
236 jtag_set_end_state(TAP_IDLE);
237 etb_scann(etb_reg->etb, 0x0);
238 etb_set_instr(etb_reg->etb, 0xc);
240 fields[0].tap = etb_reg->etb->tap;
241 fields[0].num_bits = 32;
242 fields[0].out_value = reg->value;
243 fields[0].in_value = NULL;
244 fields[0].check_value = NULL;
245 fields[0].check_mask = NULL;
247 fields[1].tap = etb_reg->etb->tap;
248 fields[1].num_bits = 7;
249 fields[1].out_value = malloc(1);
250 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
251 fields[1].in_value = NULL;
252 fields[1].check_value = NULL;
253 fields[1].check_mask = NULL;
255 fields[2].tap = etb_reg->etb->tap;
256 fields[2].num_bits = 1;
257 fields[2].out_value = malloc(1);
258 buf_set_u32(fields[2].out_value, 0, 1, 0);
259 fields[2].in_value = NULL;
260 fields[2].check_value = NULL;
261 fields[2].check_mask = NULL;
263 jtag_add_dr_scan(3, fields, jtag_get_end_state());
265 /* read the identification register in the second run, to make sure we
266 * don't read the ETB data register twice, skipping every second entry
268 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
269 fields[0].in_value = reg->value;
270 fields[0].check_value = check_value;
271 fields[0].check_mask = check_mask;
273 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
275 free(fields[1].out_value);
276 free(fields[2].out_value);
281 static int etb_write_reg(reg_t *, uint32_t);
283 static int etb_set_reg(reg_t *reg, uint32_t value)
287 if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
289 LOG_ERROR("BUG: error scheduling ETB register write");
293 buf_set_u32(reg->value, 0, reg->size, value);
300 static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
304 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
306 if ((retval = jtag_execute_queue()) != ERROR_OK)
308 LOG_ERROR("ETB: register write failed");
314 static int etb_write_reg(reg_t *reg, uint32_t value)
316 etb_reg_t *etb_reg = reg->arch_info;
317 uint8_t reg_addr = etb_reg->addr & 0x7f;
318 scan_field_t fields[3];
320 LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
322 jtag_set_end_state(TAP_IDLE);
323 etb_scann(etb_reg->etb, 0x0);
324 etb_set_instr(etb_reg->etb, 0xc);
326 fields[0].tap = etb_reg->etb->tap;
327 fields[0].num_bits = 32;
328 fields[0].out_value = malloc(4);
329 buf_set_u32(fields[0].out_value, 0, 32, value);
330 fields[0].in_value = NULL;
332 fields[1].tap = etb_reg->etb->tap;
333 fields[1].num_bits = 7;
334 fields[1].out_value = malloc(1);
335 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
336 fields[1].in_value = NULL;
338 fields[2].tap = etb_reg->etb->tap;
339 fields[2].num_bits = 1;
340 fields[2].out_value = malloc(1);
341 buf_set_u32(fields[2].out_value, 0, 1, 1);
343 fields[2].in_value = NULL;
345 free(fields[0].out_value);
346 free(fields[1].out_value);
347 free(fields[2].out_value);
352 COMMAND_HANDLER(handle_etb_config_command)
360 return ERROR_COMMAND_SYNTAX_ERROR;
363 target = get_target(args[0]);
367 LOG_ERROR("ETB: target '%s' not defined", args[0]);
371 arm = target_to_arm(target);
374 command_print(cmd_ctx, "ETB: '%s' isn't an ARM", args[0]);
378 tap = jtag_tap_by_string(args[1]);
381 command_print(cmd_ctx, "ETB: TAP %s does not exist", args[1]);
387 etb_t *etb = malloc(sizeof(etb_t));
389 arm->etm->capture_driver_priv = etb;
392 etb->cur_scan_chain = 0xffffffff;
393 etb->reg_cache = NULL;
399 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
406 static int etb_register_commands(struct command_context_s *cmd_ctx)
408 command_t *etb_cmd = register_command(cmd_ctx, NULL, "etb",
409 NULL, COMMAND_ANY, "Embedded Trace Buffer");
411 register_command(cmd_ctx, etb_cmd, "config",
412 handle_etb_config_command, COMMAND_CONFIG,
418 static int etb_init(etm_context_t *etm_ctx)
420 etb_t *etb = etm_ctx->capture_driver_priv;
422 etb->etm_ctx = etm_ctx;
424 /* identify ETB RAM depth and width */
425 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
426 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
427 jtag_execute_queue();
429 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
430 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
435 static trace_status_t etb_status(etm_context_t *etm_ctx)
437 etb_t *etb = etm_ctx->capture_driver_priv;
438 reg_t *control = &etb->reg_cache->reg_list[ETB_CTRL];
439 reg_t *status = &etb->reg_cache->reg_list[ETB_STATUS];
440 trace_status_t retval = 0;
441 int etb_timeout = 100;
443 etb->etm_ctx = etm_ctx;
445 /* read control and status registers */
446 etb_read_reg(control);
447 etb_read_reg(status);
448 jtag_execute_queue();
450 /* See if it's (still) active */
451 retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
453 /* check Full bit to identify wraparound/overflow */
454 if (buf_get_u32(status->value, 0, 1) == 1)
455 retval |= TRACE_OVERFLOWED;
457 /* check Triggered bit to identify trigger condition */
458 if (buf_get_u32(status->value, 1, 1) == 1)
459 retval |= TRACE_TRIGGERED;
461 /* check AcqComp to see if trigger counter dropped to zero */
462 if (buf_get_u32(status->value, 2, 1) == 1) {
463 /* wait for DFEmpty */
464 while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
467 if (etb_timeout == 0)
468 LOG_ERROR("ETB: DFEmpty won't go high, status 0x%02x",
469 (unsigned) buf_get_u32(status->value, 0, 4));
471 if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
472 LOG_WARNING("ETB: trace complete without triggering?");
474 retval |= TRACE_COMPLETED;
477 /* NOTE: using a trigger is optional; and at least ETB11 has a mode
478 * where it can ignore the trigger counter.
481 /* update recorded state */
482 etm_ctx->capture_status = retval;
487 static int etb_read_trace(etm_context_t *etm_ctx)
489 etb_t *etb = etm_ctx->capture_driver_priv;
491 int num_frames = etb->ram_depth;
492 uint32_t *trace_data = NULL;
495 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
496 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
497 jtag_execute_queue();
499 /* check if we overflowed, and adjust first frame of the trace accordingly
500 * if we didn't overflow, read only up to the frame that would be written next,
501 * i.e. don't read invalid entries
503 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
505 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
509 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
512 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
514 /* read data into temporary array for unpacking */
515 trace_data = malloc(sizeof(uint32_t) * num_frames);
516 etb_read_ram(etb, trace_data, num_frames);
518 if (etm_ctx->trace_depth > 0)
520 free(etm_ctx->trace_data);
523 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
524 etm_ctx->trace_depth = num_frames * 3;
525 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
526 etm_ctx->trace_depth = num_frames * 2;
528 etm_ctx->trace_depth = num_frames;
530 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
532 for (i = 0, j = 0; i < num_frames; i++)
534 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
537 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
538 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
539 etm_ctx->trace_data[j].flags = 0;
540 if ((trace_data[i] & 0x80) >> 7)
542 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
544 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
546 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
547 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
550 /* trace word j + 1 */
551 etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
552 etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
553 etm_ctx->trace_data[j + 1].flags = 0;
554 if ((trace_data[i] & 0x8000) >> 15)
556 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
558 if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
560 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
561 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
564 /* trace word j + 2 */
565 etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
566 etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
567 etm_ctx->trace_data[j + 2].flags = 0;
568 if ((trace_data[i] & 0x800000) >> 23)
570 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
572 if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
574 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
575 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
580 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
583 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
584 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
585 etm_ctx->trace_data[j].flags = 0;
586 if ((trace_data[i] & 0x800) >> 11)
588 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
590 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
592 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
593 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
596 /* trace word j + 1 */
597 etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
598 etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
599 etm_ctx->trace_data[j + 1].flags = 0;
600 if ((trace_data[i] & 0x800000) >> 23)
602 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
604 if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
606 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
607 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
615 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
616 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
617 etm_ctx->trace_data[j].flags = 0;
618 if ((trace_data[i] & 0x80000) >> 19)
620 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
622 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
624 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
625 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
637 static int etb_start_capture(etm_context_t *etm_ctx)
639 etb_t *etb = etm_ctx->capture_driver_priv;
640 uint32_t etb_ctrl_value = 0x1;
641 uint32_t trigger_count;
643 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
645 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
647 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
648 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
650 etb_ctrl_value |= 0x2;
653 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
654 LOG_ERROR("ETB: can't run in multiplexed mode");
655 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
658 trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
660 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
661 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
662 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
663 jtag_execute_queue();
665 /* we're starting a new trace, initialize capture status */
666 etm_ctx->capture_status = TRACE_RUNNING;
671 static int etb_stop_capture(etm_context_t *etm_ctx)
673 etb_t *etb = etm_ctx->capture_driver_priv;
674 reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
676 etb_write_reg(etb_ctrl_reg, 0x0);
677 jtag_execute_queue();
679 /* trace stopped, just clear running flag, but preserve others */
680 etm_ctx->capture_status &= ~TRACE_RUNNING;
685 etm_capture_driver_t etb_capture_driver =
688 .register_commands = etb_register_commands,
690 .status = etb_status,
691 .start_capture = etb_start_capture,
692 .stop_capture = etb_stop_capture,
693 .read_trace = etb_read_trace,