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1 /***************************************************************************
2  *   Copyright (C) 2007 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <string.h>
25
26 #include "arm7_9_common.h"
27 #include "etb.h"
28 #include "etm.h"
29
30 #include "log.h"
31 #include "types.h"
32 #include "binarybuffer.h"
33 #include "target.h"
34 #include "register.h"
35 #include "jtag.h"
36
37 #include <stdlib.h>
38
39 char* etb_reg_list[] =
40 {
41         "ETB_identification",
42         "ETB_ram_depth",
43         "ETB_ram_width",
44         "ETB_status",
45         "ETB_ram_data",
46         "ETB_ram_read_pointer",
47         "ETB_ram_write_pointer",
48         "ETB_trigger_counter",
49         "ETB_control",
50 };
51
52 int etb_reg_arch_type = -1;
53
54 int etb_get_reg(reg_t *reg);
55 int etb_set_reg(reg_t *reg, u32 value);
56 int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
57
58 int etb_write_reg(reg_t *reg, u32 value);
59 int etb_read_reg(reg_t *reg);
60
61 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
62
63 int etb_set_instr(etb_t *etb, u32 new_instr)
64 {
65         jtag_tap_t *tap;
66         tap = etb->tap;
67         if (tap==NULL)
68                 return ERROR_FAIL;
69
70         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
71         {
72                 scan_field_t field;
73
74                 field.tap = tap;
75                 field.num_bits = tap->ir_length;
76                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
77                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
78                 field.out_mask = NULL;
79                 field.in_value = NULL;
80                 field.in_check_value = NULL;
81                 field.in_check_mask = NULL;
82                 field.in_handler = NULL;
83                 field.in_handler_priv = NULL;
84
85                 jtag_add_ir_scan(1, &field, -1);
86
87                 free(field.out_value);
88         }
89
90         return ERROR_OK;
91 }
92
93 int etb_scann(etb_t *etb, u32 new_scan_chain)
94 {
95         if(etb->cur_scan_chain != new_scan_chain)
96         {
97                 scan_field_t field;
98
99                 field.tap = etb->tap;
100                 field.num_bits = 5;
101                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
102                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
103                 field.out_mask = NULL;
104                 field.in_value = NULL;
105                 field.in_check_value = NULL;
106                 field.in_check_mask = NULL;
107                 field.in_handler = NULL;
108                 field.in_handler_priv = NULL;
109
110                 /* select INTEST instruction */
111                 etb_set_instr(etb, 0x2);
112                 jtag_add_dr_scan(1, &field, -1);
113
114                 etb->cur_scan_chain = new_scan_chain;
115
116                 free(field.out_value);
117         }
118
119         return ERROR_OK;
120 }
121
122 reg_cache_t* etb_build_reg_cache(etb_t *etb)
123 {
124         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
125         reg_t *reg_list = NULL;
126         etb_reg_t *arch_info = NULL;
127         int num_regs = 9;
128         int i;
129
130         /* register a register arch-type for etm registers only once */
131         if (etb_reg_arch_type == -1)
132                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
133
134         /* the actual registers are kept in two arrays */
135         reg_list = calloc(num_regs, sizeof(reg_t));
136         arch_info = calloc(num_regs, sizeof(etb_reg_t));
137
138         /* fill in values for the reg cache */
139         reg_cache->name = "etb registers";
140         reg_cache->next = NULL;
141         reg_cache->reg_list = reg_list;
142         reg_cache->num_regs = num_regs;
143
144         /* set up registers */
145         for (i = 0; i < num_regs; i++)
146         {
147                 reg_list[i].name = etb_reg_list[i];
148                 reg_list[i].size = 32;
149                 reg_list[i].dirty = 0;
150                 reg_list[i].valid = 0;
151                 reg_list[i].bitfield_desc = NULL;
152                 reg_list[i].num_bitfields = 0;
153                 reg_list[i].value = calloc(1, 4);
154                 reg_list[i].arch_info = &arch_info[i];
155                 reg_list[i].arch_type = etb_reg_arch_type;
156                 reg_list[i].size = 32;
157                 arch_info[i].addr = i;
158                 arch_info[i].etb = etb;
159         }
160
161         return reg_cache;
162 }
163
164 int etb_get_reg(reg_t *reg)
165 {
166         int retval;
167         if ((retval = etb_read_reg(reg)) != ERROR_OK)
168         {
169                 LOG_ERROR("BUG: error scheduling etm register read");
170                 return retval;
171         }
172
173         if ((retval = jtag_execute_queue()) != ERROR_OK)
174         {
175                 LOG_ERROR("register read failed");
176                 return retval;
177         }
178
179         return ERROR_OK;
180 }
181
182 int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
183 {
184         scan_field_t fields[3];
185         int i;
186
187         jtag_add_end_state(TAP_RTI);
188         etb_scann(etb, 0x0);
189         etb_set_instr(etb, 0xc);
190
191         fields[0].tap = etb->tap;
192         fields[0].num_bits = 32;
193         fields[0].out_value = NULL;
194         fields[0].out_mask = NULL;
195         fields[0].in_value = NULL;
196         fields[0].in_check_value = NULL;
197         fields[0].in_check_mask = NULL;
198         fields[0].in_handler = NULL;
199         fields[0].in_handler_priv = NULL;
200
201         fields[1].tap = etb->tap;
202         fields[1].num_bits = 7;
203         fields[1].out_value = malloc(1);
204         buf_set_u32(fields[1].out_value, 0, 7, 4);
205         fields[1].out_mask = NULL;
206         fields[1].in_value = NULL;
207         fields[1].in_check_value = NULL;
208         fields[1].in_check_mask = NULL;
209         fields[1].in_handler = NULL;
210         fields[1].in_handler_priv = NULL;
211
212         fields[2].tap = etb->tap;
213         fields[2].num_bits = 1;
214         fields[2].out_value = malloc(1);
215         buf_set_u32(fields[2].out_value, 0, 1, 0);
216         fields[2].out_mask = NULL;
217         fields[2].in_value = NULL;
218         fields[2].in_check_value = NULL;
219         fields[2].in_check_mask = NULL;
220         fields[2].in_handler = NULL;
221         fields[2].in_handler_priv = NULL;
222
223         jtag_add_dr_scan(3, fields, -1);
224
225         fields[0].in_handler = buf_to_u32_handler;
226
227         for (i = 0; i < num_frames; i++)
228         {
229                 /* ensure nR/W reamins set to read */
230                 buf_set_u32(fields[2].out_value, 0, 1, 0);
231
232                 /* address remains set to 0x4 (RAM data) until we read the last frame */
233                 if (i < num_frames - 1)
234                         buf_set_u32(fields[1].out_value, 0, 7, 4);
235                 else
236                         buf_set_u32(fields[1].out_value, 0, 7, 0);
237
238                 fields[0].in_handler_priv = &data[i];
239                 jtag_add_dr_scan(3, fields, -1);
240         }
241
242         jtag_execute_queue();
243
244         free(fields[1].out_value);
245         free(fields[2].out_value);
246
247         return ERROR_OK;
248 }
249
250 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
251 {
252         etb_reg_t *etb_reg = reg->arch_info;
253         u8 reg_addr = etb_reg->addr & 0x7f;
254         scan_field_t fields[3];
255
256         LOG_DEBUG("%i", etb_reg->addr);
257
258         jtag_add_end_state(TAP_RTI);
259         etb_scann(etb_reg->etb, 0x0);
260         etb_set_instr(etb_reg->etb, 0xc);
261
262         fields[0].tap = etb_reg->etb->tap;
263         fields[0].num_bits = 32;
264         fields[0].out_value = reg->value;
265         fields[0].out_mask = NULL;
266         fields[0].in_value = NULL;
267         fields[0].in_check_value = NULL;
268         fields[0].in_check_mask = NULL;
269         fields[0].in_handler = NULL;
270         fields[0].in_handler_priv = NULL;
271
272         fields[1].tap = etb_reg->etb->tap;
273         fields[1].num_bits = 7;
274         fields[1].out_value = malloc(1);
275         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
276         fields[1].out_mask = NULL;
277         fields[1].in_value = NULL;
278         fields[1].in_check_value = NULL;
279         fields[1].in_check_mask = NULL;
280         fields[1].in_handler = NULL;
281         fields[1].in_handler_priv = NULL;
282
283         fields[2].tap = etb_reg->etb->tap;
284         fields[2].num_bits = 1;
285         fields[2].out_value = malloc(1);
286         buf_set_u32(fields[2].out_value, 0, 1, 0);
287         fields[2].out_mask = NULL;
288         fields[2].in_value = NULL;
289         fields[2].in_check_value = NULL;
290         fields[2].in_check_mask = NULL;
291         fields[2].in_handler = NULL;
292         fields[2].in_handler_priv = NULL;
293
294         jtag_add_dr_scan(3, fields, -1);
295
296         /* read the identification register in the second run, to make sure we
297          * don't read the ETB data register twice, skipping every second entry
298          */
299         buf_set_u32(fields[1].out_value, 0, 7, 0x0);
300         fields[0].in_value = reg->value;
301
302         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
303
304         jtag_add_dr_scan(3, fields, -1);
305
306         free(fields[1].out_value);
307         free(fields[2].out_value);
308
309         return ERROR_OK;
310 }
311
312 int etb_read_reg(reg_t *reg)
313 {
314         return etb_read_reg_w_check(reg, NULL, NULL);
315 }
316
317 int etb_set_reg(reg_t *reg, u32 value)
318 {
319         int retval;
320         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
321         {
322                 LOG_ERROR("BUG: error scheduling etm register write");
323                 return retval;
324         }
325
326         buf_set_u32(reg->value, 0, reg->size, value);
327         reg->valid = 1;
328         reg->dirty = 0;
329
330         return ERROR_OK;
331 }
332
333 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
334 {
335         int retval;
336         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
337
338         if ((retval = jtag_execute_queue()) != ERROR_OK)
339         {
340                 LOG_ERROR("register write failed");
341                 return retval;
342         }
343         return ERROR_OK;
344 }
345
346 int etb_write_reg(reg_t *reg, u32 value)
347 {
348         etb_reg_t *etb_reg = reg->arch_info;
349         u8 reg_addr = etb_reg->addr & 0x7f;
350         scan_field_t fields[3];
351
352         LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
353
354         jtag_add_end_state(TAP_RTI);
355         etb_scann(etb_reg->etb, 0x0);
356         etb_set_instr(etb_reg->etb, 0xc);
357
358         fields[0].tap = etb_reg->etb->tap;
359         fields[0].num_bits = 32;
360         fields[0].out_value = malloc(4);
361         buf_set_u32(fields[0].out_value, 0, 32, value);
362         fields[0].out_mask = NULL;
363         fields[0].in_value = NULL;
364         fields[0].in_check_value = NULL;
365         fields[0].in_check_mask = NULL;
366         fields[0].in_handler = NULL;
367         fields[0].in_handler_priv = NULL;
368
369         fields[1].tap = etb_reg->etb->tap;
370         fields[1].num_bits = 7;
371         fields[1].out_value = malloc(1);
372         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
373         fields[1].out_mask = NULL;
374         fields[1].in_value = NULL;
375         fields[1].in_check_value = NULL;
376         fields[1].in_check_mask = NULL;
377         fields[1].in_handler = NULL;
378         fields[1].in_handler_priv = NULL;
379
380         fields[2].tap = etb_reg->etb->tap;
381         fields[2].num_bits = 1;
382         fields[2].out_value = malloc(1);
383         buf_set_u32(fields[2].out_value, 0, 1, 1);
384         fields[2].out_mask = NULL;
385         fields[2].in_value = NULL;
386         fields[2].in_check_value = NULL;
387         fields[2].in_check_mask = NULL;
388         fields[2].in_handler = NULL;
389         fields[2].in_handler_priv = NULL;
390
391         jtag_add_dr_scan(3, fields, -1);
392
393         free(fields[0].out_value);
394         free(fields[1].out_value);
395         free(fields[2].out_value);
396
397         return ERROR_OK;
398 }
399
400 int etb_store_reg(reg_t *reg)
401 {
402         return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
403 }
404
405 int etb_register_commands(struct command_context_s *cmd_ctx)
406 {
407         command_t *etb_cmd;
408
409         etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
410
411         register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
412
413         return ERROR_OK;
414 }
415
416 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
417 {
418         target_t *target;
419         jtag_tap_t *tap;
420         armv4_5_common_t *armv4_5;
421         arm7_9_common_t *arm7_9;
422
423         if (argc != 2)
424         {
425                 return ERROR_COMMAND_SYNTAX_ERROR;
426         }
427
428         target = get_target_by_num(strtoul(args[0], NULL, 0));
429
430         if (!target)
431         {
432                 LOG_ERROR("target number '%s' not defined", args[0]);
433                 return ERROR_FAIL;
434         }
435
436         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
437         {
438                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
439                 return ERROR_FAIL;
440         }
441
442         tap = jtag_TapByString( args[1] );
443         if( tap == NULL ){
444                 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
445                 return ERROR_FAIL;
446         }
447
448
449         if (arm7_9->etm_ctx)
450         {
451                 etb_t *etb = malloc(sizeof(etb_t));
452
453                 arm7_9->etm_ctx->capture_driver_priv = etb;
454
455                 etb->tap  = tap;
456                 etb->cur_scan_chain = -1;
457                 etb->reg_cache = NULL;
458                 etb->ram_width = 0;
459                 etb->ram_depth = 0;
460         }
461         else
462         {
463                 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
464                 return ERROR_FAIL;
465         }
466
467         return ERROR_OK;
468 }
469
470 int etb_init(etm_context_t *etm_ctx)
471 {
472         etb_t *etb = etm_ctx->capture_driver_priv;
473
474         etb->etm_ctx = etm_ctx;
475
476         /* identify ETB RAM depth and width */
477         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
478         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
479         jtag_execute_queue();
480
481         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
482         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
483
484         return ERROR_OK;
485 }
486
487 trace_status_t etb_status(etm_context_t *etm_ctx)
488 {
489         etb_t *etb = etm_ctx->capture_driver_priv;
490
491         etb->etm_ctx = etm_ctx;
492
493         /* if tracing is currently idle, return this information */
494         if (etm_ctx->capture_status == TRACE_IDLE)
495         {
496                 return etm_ctx->capture_status;
497         }
498         else if (etm_ctx->capture_status & TRACE_RUNNING)
499         {
500                 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
501                 int etb_timeout = 100;
502
503                 /* trace is running, check the ETB status flags */
504                 etb_get_reg(etb_status_reg);
505
506                 /* check Full bit to identify an overflow */
507                 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
508                         etm_ctx->capture_status |= TRACE_OVERFLOWED;
509
510                 /* check Triggered bit to identify trigger condition */
511                 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
512                         etm_ctx->capture_status |= TRACE_TRIGGERED;
513
514                 /* check AcqComp to identify trace completion */
515                 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
516                 {
517                         while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
518                         {
519                                 /* wait for data formatter idle */
520                                 etb_get_reg(etb_status_reg);
521                         }
522
523                         if (etb_timeout == 0)
524                         {
525                                 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
526                                         buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
527                         }
528
529                         if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
530                         {
531                                 LOG_ERROR("trace completed, but no trigger condition detected");
532                         }
533
534                         etm_ctx->capture_status &= ~TRACE_RUNNING;
535                         etm_ctx->capture_status |= TRACE_COMPLETED;
536                 }
537         }
538
539         return etm_ctx->capture_status;
540 }
541
542 int etb_read_trace(etm_context_t *etm_ctx)
543 {
544         etb_t *etb = etm_ctx->capture_driver_priv;
545         int first_frame = 0;
546         int num_frames = etb->ram_depth;
547         u32 *trace_data = NULL;
548         int i, j;
549
550         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
551         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
552         jtag_execute_queue();
553
554         /* check if we overflowed, and adjust first frame of the trace accordingly
555          * if we didn't overflow, read only up to the frame that would be written next,
556          * i.e. don't read invalid entries
557          */
558         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
559         {
560                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
561         }
562         else
563         {
564                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
565         }
566
567         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
568
569         /* read data into temporary array for unpacking */
570         trace_data = malloc(sizeof(u32) * num_frames);
571         etb_read_ram(etb, trace_data, num_frames);
572
573         if (etm_ctx->trace_depth > 0)
574         {
575                 free(etm_ctx->trace_data);
576         }
577
578         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
579                 etm_ctx->trace_depth = num_frames * 3;
580         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
581                 etm_ctx->trace_depth = num_frames * 2;
582         else
583                 etm_ctx->trace_depth = num_frames;
584
585         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
586
587         for (i = 0, j = 0; i < num_frames; i++)
588         {
589                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
590                 {
591                         /* trace word j */
592                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
593                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
594                         etm_ctx->trace_data[j].flags = 0;
595                         if ((trace_data[i] & 0x80) >> 7)
596                         {
597                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
598                         }
599                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
600                         {
601                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
602                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
603                         }
604
605                         /* trace word j+1 */
606                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
607                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
608                         etm_ctx->trace_data[j+1].flags = 0;
609                         if ((trace_data[i] & 0x8000) >> 15)
610                         {
611                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
612                         }
613                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
614                         {
615                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
616                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
617                         }
618
619                         /* trace word j+2 */
620                         etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
621                         etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
622                         etm_ctx->trace_data[j+2].flags = 0;
623                         if ((trace_data[i] & 0x800000) >> 23)
624                         {
625                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
626                         }
627                         if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
628                         {
629                                 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
630                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
631                         }
632
633                         j += 3;
634                 }
635                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
636                 {
637                         /* trace word j */
638                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
639                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
640                         etm_ctx->trace_data[j].flags = 0;
641                         if ((trace_data[i] & 0x800) >> 11)
642                         {
643                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
644                         }
645                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
646                         {
647                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
648                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
649                         }
650
651                         /* trace word j+1 */
652                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
653                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
654                         etm_ctx->trace_data[j+1].flags = 0;
655                         if ((trace_data[i] & 0x800000) >> 23)
656                         {
657                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
658                         }
659                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
660                         {
661                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
662                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
663                         }
664
665                         j += 2;
666                 }
667                 else
668                 {
669                         /* trace word j */
670                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
671                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
672                         etm_ctx->trace_data[j].flags = 0;
673                         if ((trace_data[i] & 0x80000) >> 19)
674                         {
675                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
676                         }
677                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
678                         {
679                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
680                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
681                         }
682
683                         j += 1;
684                 }
685         }
686
687         free(trace_data);
688
689         return ERROR_OK;
690 }
691
692 int etb_start_capture(etm_context_t *etm_ctx)
693 {
694         etb_t *etb = etm_ctx->capture_driver_priv;
695         u32 etb_ctrl_value = 0x1;
696         u32 trigger_count;
697
698         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
699         {
700                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
701                 {
702                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
703                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
704                 }
705                 etb_ctrl_value |= 0x2;
706         }
707
708         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
709                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
710
711         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
712
713         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
714         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
715         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
716         jtag_execute_queue();
717
718         /* we're starting a new trace, initialize capture status */
719         etm_ctx->capture_status = TRACE_RUNNING;
720
721         return ERROR_OK;
722 }
723
724 int etb_stop_capture(etm_context_t *etm_ctx)
725 {
726         etb_t *etb = etm_ctx->capture_driver_priv;
727         reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
728
729         etb_write_reg(etb_ctrl_reg, 0x0);
730         jtag_execute_queue();
731
732         /* trace stopped, just clear running flag, but preserve others */
733         etm_ctx->capture_status &= ~TRACE_RUNNING;
734
735         return ERROR_OK;
736 }
737
738 etm_capture_driver_t etb_capture_driver =
739 {
740         .name = "etb",
741         .register_commands = etb_register_commands,
742         .init = etb_init,
743         .status = etb_status,
744         .start_capture = etb_start_capture,
745         .stop_capture = etb_stop_capture,
746         .read_trace = etb_read_trace,
747 };