1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
32 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
34 * ETM modules collect instruction and/or data trace information, compress
35 * it, and transfer it to a debugging host through either a (buffered) trace
36 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
38 * There are several generations of these modules. Original versions have
39 * JTAG access through a dedicated scan chain. Recent versions have added
40 * access via coprocessor instructions, memory addressing, and the ARM Debug
41 * Interface v5 (ADIv5); and phased out direct JTAG access.
43 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
44 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
45 * implying non-JTAG connectivity options.
47 * Relevant documentation includes:
48 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
49 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
50 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
53 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
63 uint8_t size; /* low-N of 32 bits */
64 uint8_t mode; /* RO, WO, RW */
65 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
71 * (Or on some processors, through coprocessor operations.)
72 * Newer versions of ETM make some W/O registers R/W, and
73 * provide definitions for some previously-unused bits.
76 /* basic registers that are always there given the right ETM version */
77 static const struct etm_reg_info etm_core[] = {
78 /* NOTE: we "know" ETM_CONFIG is listed first */
79 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
81 /* ETM Trace Registers */
82 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
83 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
84 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
85 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
86 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
88 /* TraceEnable configuration */
89 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
90 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
91 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
92 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
94 /* ViewData configuration (data trace) */
95 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
96 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
97 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
98 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
100 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
102 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
103 { 0x79, 32, RO, 0x20, "ETM_id", },
106 static const struct etm_reg_info etm_fifofull[] = {
107 /* FIFOFULL configuration */
108 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
109 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
112 static const struct etm_reg_info etm_addr_comp[] = {
113 /* Address comparator register pairs */
114 #define ADDR_COMPARATOR(i) \
115 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
116 "ETM_addr_" #i "_comparator_value", }, \
117 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
118 "ETM_addr_" #i "_access_type", }
136 #undef ADDR_COMPARATOR
139 static const struct etm_reg_info etm_data_comp[] = {
140 /* Data Value Comparators (NOTE: odd addresses are reserved) */
141 #define DATA_COMPARATOR(i) \
142 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
143 "ETM_data_" #i "_comparator_value", }, \
144 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
145 "ETM_data_" #i "_comparator_mask", }
154 #undef DATA_COMPARATOR
157 static const struct etm_reg_info etm_counters[] = {
158 #define ETM_COUNTER(i) \
159 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
160 "ETM_counter_" #i "_reload_value", }, \
161 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
162 "ETM_counter_" #i "_enable", }, \
163 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
164 "ETM_counter_" #i "_reload_event", }, \
165 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
166 "ETM_counter_" #i "_value", }
174 static const struct etm_reg_info etm_sequencer[] = {
176 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
177 "ETM_sequencer_event" #i, }
178 ETM_SEQ(0), /* 1->2 */
179 ETM_SEQ(1), /* 2->1 */
180 ETM_SEQ(2), /* 2->3 */
181 ETM_SEQ(3), /* 3->1 */
182 ETM_SEQ(4), /* 3->2 */
183 ETM_SEQ(5), /* 1->3 */
186 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
189 static const struct etm_reg_info etm_outputs[] = {
190 #define ETM_OUTPUT(i) \
191 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
192 "ETM_external_output" #i, }
202 /* registers from 0x6c..0x7f were added after ETMv1.3 */
204 /* Context ID Comparators */
205 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
206 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
207 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
208 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
211 static int etm_reg_arch_type = -1;
213 static int etm_get_reg(reg_t *reg);
214 static int etm_read_reg_w_check(reg_t *reg,
215 uint8_t* check_value, uint8_t* check_mask);
216 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
217 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
218 static int etm_write_reg(reg_t *reg, uint32_t value);
220 static command_t *etm_cmd;
223 /* Look up register by ID ... most ETM instances only
224 * support a subset of the possible registers.
226 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
228 reg_cache_t *cache = etm_ctx->reg_cache;
231 for (i = 0; i < cache->num_regs; i++) {
232 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
234 if (reg->reg_info->addr == id)
235 return &cache->reg_list[i];
238 /* caller asking for nonexistent register is a bug! */
239 /* REVISIT say which of the N targets was involved */
240 LOG_ERROR("ETM: register 0x%02x not available", id);
244 static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
245 reg_cache_t *cache, etm_reg_t *ereg,
246 const struct etm_reg_info *r, unsigned nreg)
248 reg_t *reg = cache->reg_list;
250 reg += cache->num_regs;
251 ereg += cache->num_regs;
253 /* add up to "nreg" registers from "r", if supported by this
254 * version of the ETM, to the specified cache.
256 for (; nreg--; r++) {
258 /* this ETM may be too old to have some registers */
259 if (r->bcd_vers > bcd_vers)
264 reg->value = &ereg->value;
265 reg->arch_info = ereg;
266 reg->arch_type = etm_reg_arch_type;
271 ereg->jtag_info = jtag_info;
276 reg_cache_t *etm_build_reg_cache(target_t *target,
277 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
279 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
280 reg_t *reg_list = NULL;
281 etm_reg_t *arch_info = NULL;
282 unsigned bcd_vers, config;
284 /* register a register arch-type for etm registers only once */
285 if (etm_reg_arch_type == -1)
286 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
289 /* the actual registers are kept in two arrays */
290 reg_list = calloc(128, sizeof(reg_t));
291 arch_info = calloc(128, sizeof(etm_reg_t));
293 /* fill in values for the reg cache */
294 reg_cache->name = "etm registers";
295 reg_cache->next = NULL;
296 reg_cache->reg_list = reg_list;
297 reg_cache->num_regs = 0;
299 /* add ETM_CONFIG, then parse its values to see
300 * which other registers exist in this ETM
302 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
305 etm_get_reg(reg_list);
306 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
307 config = etm_ctx->config;
309 /* figure ETM version then add base registers */
310 if (config & (1 << 31)) {
312 LOG_WARNING("ETMv2+ support is incomplete");
314 /* REVISIT read ID register, distinguish ETMv3.3 etc;
315 * don't presume trace start/stop support is present;
316 * and include any context ID comparator registers.
319 switch (config >> 28) {
336 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
343 etm_ctx->bcd_vers = bcd_vers;
344 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
346 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
347 etm_core + 1, ARRAY_SIZE(etm_core) - 1);
349 /* address and data comparators; counters; outputs */
350 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
351 etm_addr_comp, 4 * (0x0f & (config >> 0)));
352 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
353 etm_data_comp, 2 * (0x0f & (config >> 4)));
354 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
355 etm_counters, 4 * (0x07 & (config >> 13)));
356 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
357 etm_outputs, (0x07 & (config >> 20)));
359 /* FIFOFULL presence is optional
360 * REVISIT for ETMv1.2 and later, don't bother adding this
361 * unless ETM_SYS_CONFIG says it's also *supported* ...
363 if (config & (1 << 23))
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_fifofull, ARRAY_SIZE(etm_fifofull));
367 /* sequencer is optional (for state-dependant triggering) */
368 if (config & (1 << 16))
369 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
370 etm_sequencer, ARRAY_SIZE(etm_sequencer));
372 /* REVISIT could realloc and likely save half the memory
373 * in the two chunks we allocated...
376 /* the ETM might have an ETB connected */
377 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
379 etb_t *etb = etm_ctx->capture_driver_priv;
383 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
390 reg_cache->next = etb_build_reg_cache(etb);
392 etb->reg_cache = reg_cache->next;
399 static int etm_read_reg(reg_t *reg)
401 return etm_read_reg_w_check(reg, NULL, NULL);
404 static int etm_store_reg(reg_t *reg)
406 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
409 int etm_setup(target_t *target)
412 uint32_t etm_ctrl_value;
413 struct arm *arm = target_to_arm(target);
414 etm_context_t *etm_ctx = arm->etm;
417 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
421 /* initialize some ETM control register settings */
422 etm_get_reg(etm_ctrl_reg);
423 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
425 /* clear the ETM powerdown bit (0) */
426 etm_ctrl_value &= ~0x1;
428 /* configure port width (6:4), mode (17:16) and clocking (13) */
429 etm_ctrl_value = (etm_ctrl_value &
430 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
433 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
434 etm_store_reg(etm_ctrl_reg);
436 if ((retval = jtag_execute_queue()) != ERROR_OK)
439 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
441 LOG_ERROR("ETM capture driver initialization failed");
447 static int etm_get_reg(reg_t *reg)
451 if ((retval = etm_read_reg(reg)) != ERROR_OK)
453 LOG_ERROR("BUG: error scheduling etm register read");
457 if ((retval = jtag_execute_queue()) != ERROR_OK)
459 LOG_ERROR("register read failed");
466 static int etm_read_reg_w_check(reg_t *reg,
467 uint8_t* check_value, uint8_t* check_mask)
469 etm_reg_t *etm_reg = reg->arch_info;
470 const struct etm_reg_info *r = etm_reg->reg_info;
471 uint8_t reg_addr = r->addr & 0x7f;
472 scan_field_t fields[3];
474 if (etm_reg->reg_info->mode == WO) {
475 LOG_ERROR("BUG: can't read write-only register %s", r->name);
476 return ERROR_INVALID_ARGUMENTS;
479 LOG_DEBUG("%s (%u)", r->name, reg_addr);
481 jtag_set_end_state(TAP_IDLE);
482 arm_jtag_scann(etm_reg->jtag_info, 0x6);
483 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
485 fields[0].tap = etm_reg->jtag_info->tap;
486 fields[0].num_bits = 32;
487 fields[0].out_value = reg->value;
488 fields[0].in_value = NULL;
489 fields[0].check_value = NULL;
490 fields[0].check_mask = NULL;
492 fields[1].tap = etm_reg->jtag_info->tap;
493 fields[1].num_bits = 7;
494 fields[1].out_value = malloc(1);
495 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
496 fields[1].in_value = NULL;
497 fields[1].check_value = NULL;
498 fields[1].check_mask = NULL;
500 fields[2].tap = etm_reg->jtag_info->tap;
501 fields[2].num_bits = 1;
502 fields[2].out_value = malloc(1);
503 buf_set_u32(fields[2].out_value, 0, 1, 0);
504 fields[2].in_value = NULL;
505 fields[2].check_value = NULL;
506 fields[2].check_mask = NULL;
508 jtag_add_dr_scan(3, fields, jtag_get_end_state());
510 fields[0].in_value = reg->value;
511 fields[0].check_value = check_value;
512 fields[0].check_mask = check_mask;
514 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
516 free(fields[1].out_value);
517 free(fields[2].out_value);
522 static int etm_set_reg(reg_t *reg, uint32_t value)
526 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
528 LOG_ERROR("BUG: error scheduling etm register write");
532 buf_set_u32(reg->value, 0, reg->size, value);
539 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
543 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
545 if ((retval = jtag_execute_queue()) != ERROR_OK)
547 LOG_ERROR("register write failed");
553 static int etm_write_reg(reg_t *reg, uint32_t value)
555 etm_reg_t *etm_reg = reg->arch_info;
556 const struct etm_reg_info *r = etm_reg->reg_info;
557 uint8_t reg_addr = r->addr & 0x7f;
558 scan_field_t fields[3];
560 if (etm_reg->reg_info->mode == RO) {
561 LOG_ERROR("BUG: can't write read--only register %s", r->name);
562 return ERROR_INVALID_ARGUMENTS;
565 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
567 jtag_set_end_state(TAP_IDLE);
568 arm_jtag_scann(etm_reg->jtag_info, 0x6);
569 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
571 fields[0].tap = etm_reg->jtag_info->tap;
572 fields[0].num_bits = 32;
574 fields[0].out_value = tmp1;
575 buf_set_u32(fields[0].out_value, 0, 32, value);
576 fields[0].in_value = NULL;
578 fields[1].tap = etm_reg->jtag_info->tap;
579 fields[1].num_bits = 7;
581 fields[1].out_value = &tmp2;
582 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
583 fields[1].in_value = NULL;
585 fields[2].tap = etm_reg->jtag_info->tap;
586 fields[2].num_bits = 1;
588 fields[2].out_value = &tmp3;
589 buf_set_u32(fields[2].out_value, 0, 1, 1);
590 fields[2].in_value = NULL;
592 jtag_add_dr_scan(3, fields, jtag_get_end_state());
598 /* ETM trace analysis functionality
601 extern etm_capture_driver_t etm_dummy_capture_driver;
602 #if BUILD_OOCD_TRACE == 1
603 extern etm_capture_driver_t oocd_trace_capture_driver;
606 static etm_capture_driver_t *etm_capture_drivers[] =
609 &etm_dummy_capture_driver,
610 #if BUILD_OOCD_TRACE == 1
611 &oocd_trace_capture_driver,
616 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
625 return ERROR_TRACE_IMAGE_UNAVAILABLE;
627 /* search for the section the current instruction belongs to */
628 for (i = 0; i < ctx->image->num_sections; i++)
630 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
631 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
640 /* current instruction couldn't be found in the image */
641 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
644 if (ctx->core_state == ARMV4_5_STATE_ARM)
647 if ((retval = image_read_section(ctx->image, section,
648 ctx->current_pc - ctx->image->sections[section].base_address,
649 4, buf, &size_read)) != ERROR_OK)
651 LOG_ERROR("error while reading instruction: %i", retval);
652 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
654 opcode = target_buffer_get_u32(ctx->target, buf);
655 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
657 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
660 if ((retval = image_read_section(ctx->image, section,
661 ctx->current_pc - ctx->image->sections[section].base_address,
662 2, buf, &size_read)) != ERROR_OK)
664 LOG_ERROR("error while reading instruction: %i", retval);
665 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
667 opcode = target_buffer_get_u16(ctx->target, buf);
668 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
670 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
672 LOG_ERROR("BUG: tracing of jazelle code not supported");
677 LOG_ERROR("BUG: unknown core state encountered");
684 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
686 while (ctx->data_index < ctx->trace_depth)
688 /* if the caller specified an address packet offset, skip until the
689 * we reach the n-th cycle marked with tracesync */
692 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
703 /* no tracedata output during a TD cycle
704 * or in a trigger cycle */
705 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
706 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
713 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
715 if (ctx->data_half == 0)
717 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
722 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
727 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
729 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
734 /* on a 4-bit port, a packet will be output during two consecutive cycles */
735 if (ctx->data_index > (ctx->trace_depth - 2))
738 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
739 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
740 ctx->data_index += 2;
749 static int etmv1_branch_address(etm_context_t *ctx)
757 /* quit analysis if less than two cycles are left in the trace
758 * because we can't extract the APO */
759 if (ctx->data_index > (ctx->trace_depth - 2))
762 /* a BE could be output during an APO cycle, skip the current
763 * and continue with the new one */
764 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
766 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
769 /* address packet offset encoded in the next two cycles' pipestat bits */
770 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
771 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
773 /* count number of tracesync cycles between current pipe_index and data_index
774 * i.e. the number of tracesyncs that data_index already passed by
775 * to subtract them from the APO */
776 for (i = ctx->pipe_index; i < ctx->data_index; i++)
778 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
782 /* extract up to four 7-bit packets */
784 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
786 ctx->last_branch &= ~(0x7f << shift);
787 ctx->last_branch |= (packet & 0x7f) << shift;
789 } while ((packet & 0x80) && (shift < 28));
791 /* one last packet holding 4 bits of the address, plus the branch reason code */
792 if ((shift == 28) && (packet & 0x80))
794 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
796 ctx->last_branch &= 0x0fffffff;
797 ctx->last_branch |= (packet & 0x0f) << 28;
798 ctx->last_branch_reason = (packet & 0x70) >> 4;
803 ctx->last_branch_reason = 0;
811 /* if a full address was output, we might have branched into Jazelle state */
812 if ((shift == 32) && (packet & 0x80))
814 ctx->core_state = ARMV4_5_STATE_JAZELLE;
818 /* if we didn't branch into Jazelle state, the current processor state is
819 * encoded in bit 0 of the branch target address */
820 if (ctx->last_branch & 0x1)
822 ctx->core_state = ARMV4_5_STATE_THUMB;
823 ctx->last_branch &= ~0x1;
827 ctx->core_state = ARMV4_5_STATE_ARM;
828 ctx->last_branch &= ~0x3;
835 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
841 for (j = 0; j < size; j++)
843 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
849 LOG_ERROR("TODO: add support for 64-bit values");
853 *data = target_buffer_get_u32(ctx->target, buf);
855 *data = target_buffer_get_u16(ctx->target, buf);
864 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
867 arm_instruction_t instruction;
869 /* read the trace data if it wasn't read already */
870 if (ctx->trace_depth == 0)
871 ctx->capture_driver->read_trace(ctx);
873 /* start at the beginning of the captured trace */
878 /* neither the PC nor the data pointer are valid */
882 while (ctx->pipe_index < ctx->trace_depth)
884 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
885 uint32_t next_pc = ctx->current_pc;
886 uint32_t old_data_index = ctx->data_index;
887 uint32_t old_data_half = ctx->data_half;
888 uint32_t old_index = ctx->pipe_index;
889 uint32_t last_instruction = ctx->last_instruction;
891 int current_pc_ok = ctx->pc_ok;
893 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
895 command_print(cmd_ctx, "--- trigger ---");
898 /* instructions execute in IE/D or BE/D cycles */
899 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
900 ctx->last_instruction = ctx->pipe_index;
902 /* if we don't have a valid pc skip until we reach an indirect branch */
903 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
909 /* any indirect branch could have interrupted instruction flow
910 * - the branch reason code could indicate a trace discontinuity
911 * - a branch to the exception vectors indicates an exception
913 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
915 /* backup current data index, to be able to consume the branch address
916 * before examining data address and values
918 old_data_index = ctx->data_index;
919 old_data_half = ctx->data_half;
921 ctx->last_instruction = ctx->pipe_index;
923 if ((retval = etmv1_branch_address(ctx)) != 0)
925 /* negative return value from etmv1_branch_address means we ran out of packets,
926 * quit analysing the trace */
930 /* a positive return values means the current branch was abandoned,
931 * and a new branch was encountered in cycle ctx->pipe_index + retval;
933 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
934 ctx->pipe_index += retval;
938 /* skip over APO cycles */
939 ctx->pipe_index += 2;
941 switch (ctx->last_branch_reason)
943 case 0x0: /* normal PC change */
944 next_pc = ctx->last_branch;
946 case 0x1: /* tracing enabled */
947 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
948 ctx->current_pc = ctx->last_branch;
952 case 0x2: /* trace restarted after FIFO overflow */
953 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
954 ctx->current_pc = ctx->last_branch;
958 case 0x3: /* exit from debug state */
959 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
960 ctx->current_pc = ctx->last_branch;
964 case 0x4: /* periodic synchronization point */
965 next_pc = ctx->last_branch;
966 /* if we had no valid PC prior to this synchronization point,
967 * we have to move on with the next trace cycle
971 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
972 ctx->current_pc = next_pc;
977 default: /* reserved */
978 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
982 /* if we got here the branch was a normal PC change
983 * (or a periodic synchronization point, which means the same for that matter)
984 * if we didn't accquire a complete PC continue with the next cycle
989 /* indirect branch to the exception vector means an exception occured */
990 if ((ctx->last_branch <= 0x20)
991 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
993 if ((ctx->last_branch & 0xff) == 0x10)
995 command_print(cmd_ctx, "data abort");
999 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1000 ctx->current_pc = ctx->last_branch;
1007 /* an instruction was executed (or not, depending on the condition flags)
1008 * retrieve it from the image for displaying */
1009 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1010 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1011 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1013 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1015 /* can't continue tracing with no image available */
1016 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1020 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1022 /* TODO: handle incomplete images
1023 * for now we just quit the analsysis*/
1028 cycles = old_index - last_instruction;
1031 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1033 uint32_t new_data_index = ctx->data_index;
1034 uint32_t new_data_half = ctx->data_half;
1036 /* in case of a branch with data, the branch target address was consumed before
1037 * we temporarily go back to the saved data index */
1038 if (pipestat == STAT_BD)
1040 ctx->data_index = old_data_index;
1041 ctx->data_half = old_data_half;
1044 if (ctx->tracemode & ETMV1_TRACE_ADDR)
1050 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1051 return ERROR_ETM_ANALYSIS_FAILED;
1052 ctx->last_ptr &= ~(0x7f << shift);
1053 ctx->last_ptr |= (packet & 0x7f) << shift;
1055 } while ((packet & 0x80) && (shift < 32));
1062 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1066 if (ctx->tracemode & ETMV1_TRACE_DATA)
1068 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1071 for (i = 0; i < 16; i++)
1073 if (instruction.info.load_store_multiple.register_list & (1 << i))
1076 if (etmv1_data(ctx, 4, &data) != 0)
1077 return ERROR_ETM_ANALYSIS_FAILED;
1078 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1082 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1085 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1086 return ERROR_ETM_ANALYSIS_FAILED;
1087 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1091 /* restore data index after consuming BD address and data */
1092 if (pipestat == STAT_BD)
1094 ctx->data_index = new_data_index;
1095 ctx->data_half = new_data_half;
1100 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1102 if (((instruction.type == ARM_B) ||
1103 (instruction.type == ARM_BL) ||
1104 (instruction.type == ARM_BLX)) &&
1105 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1107 next_pc = instruction.info.b_bl_bx_blx.target_address;
1111 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1114 else if (pipestat == STAT_IN)
1116 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1119 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1121 char cycles_text[32] = "";
1123 /* if the trace was captured with cycle accurate tracing enabled,
1124 * output the number of cycles since the last executed instruction
1126 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1128 snprintf(cycles_text, 32, " (%i %s)",
1130 (cycles == 1) ? "cycle" : "cycles");
1133 command_print(cmd_ctx, "%s%s%s",
1135 (pipestat == STAT_IN) ? " (not executed)" : "",
1138 ctx->current_pc = next_pc;
1140 /* packets for an instruction don't start on or before the preceding
1141 * functional pipestat (i.e. other than WT or TD)
1143 if (ctx->data_index <= ctx->pipe_index)
1145 ctx->data_index = ctx->pipe_index + 1;
1150 ctx->pipe_index += 1;
1156 static int handle_etm_tracemode_command_update(
1157 struct command_context_s *cmd_ctx,
1158 char **args, etmv1_tracemode_t *mode)
1160 etmv1_tracemode_t tracemode;
1162 /* what parts of data access are traced? */
1163 if (strcmp(args[0], "none") == 0)
1164 tracemode = ETMV1_TRACE_NONE;
1165 else if (strcmp(args[0], "data") == 0)
1166 tracemode = ETMV1_TRACE_DATA;
1167 else if (strcmp(args[0], "address") == 0)
1168 tracemode = ETMV1_TRACE_ADDR;
1169 else if (strcmp(args[0], "all") == 0)
1170 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1173 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1174 return ERROR_INVALID_ARGUMENTS;
1178 COMMAND_PARSE_NUMBER(u8, args[1], context_id);
1182 tracemode |= ETMV1_CONTEXTID_NONE;
1185 tracemode |= ETMV1_CONTEXTID_8;
1188 tracemode |= ETMV1_CONTEXTID_16;
1191 tracemode |= ETMV1_CONTEXTID_32;
1194 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1195 return ERROR_INVALID_ARGUMENTS;
1198 if (strcmp(args[2], "enable") == 0)
1199 tracemode |= ETMV1_CYCLE_ACCURATE;
1200 else if (strcmp(args[2], "disable") == 0)
1204 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1205 return ERROR_INVALID_ARGUMENTS;
1208 if (strcmp(args[3], "enable") == 0)
1209 tracemode |= ETMV1_BRANCH_OUTPUT;
1210 else if (strcmp(args[3], "disable") == 0)
1214 command_print(cmd_ctx, "invalid option '%s'", args[3]);
1215 return ERROR_INVALID_ARGUMENTS;
1219 * - CPRT tracing (coprocessor register transfers)
1220 * - debug request (causes debug entry on trigger)
1221 * - stall on FIFOFULL (preventing tracedata lossage)
1228 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx,
1229 char *cmd, char **args, int argc)
1231 target_t *target = get_current_target(cmd_ctx);
1232 struct arm *arm = target_to_arm(target);
1236 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1242 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1246 etmv1_tracemode_t tracemode = etm->tracemode;
1253 handle_etm_tracemode_command_update(cmd_ctx, args, &tracemode);
1256 command_print(cmd_ctx, "usage: configure trace mode "
1257 "<none | data | address | all> "
1258 "<context id bits> <cycle accurate> <branch output>");
1263 * todo: fail if parameters were invalid for this hardware,
1264 * or couldn't be written; display actual hardware state...
1267 command_print(cmd_ctx, "current tracemode configuration:");
1269 switch (tracemode & ETMV1_TRACE_MASK)
1271 case ETMV1_TRACE_NONE:
1272 command_print(cmd_ctx, "data tracing: none");
1274 case ETMV1_TRACE_DATA:
1275 command_print(cmd_ctx, "data tracing: data only");
1277 case ETMV1_TRACE_ADDR:
1278 command_print(cmd_ctx, "data tracing: address only");
1280 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1281 command_print(cmd_ctx, "data tracing: address and data");
1285 switch (tracemode & ETMV1_CONTEXTID_MASK)
1287 case ETMV1_CONTEXTID_NONE:
1288 command_print(cmd_ctx, "contextid tracing: none");
1290 case ETMV1_CONTEXTID_8:
1291 command_print(cmd_ctx, "contextid tracing: 8 bit");
1293 case ETMV1_CONTEXTID_16:
1294 command_print(cmd_ctx, "contextid tracing: 16 bit");
1296 case ETMV1_CONTEXTID_32:
1297 command_print(cmd_ctx, "contextid tracing: 32 bit");
1301 if (tracemode & ETMV1_CYCLE_ACCURATE)
1303 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1307 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1310 if (tracemode & ETMV1_BRANCH_OUTPUT)
1312 command_print(cmd_ctx, "full branch address output enabled");
1316 command_print(cmd_ctx, "full branch address output disabled");
1319 /* only update ETM_CTRL register if tracemode changed */
1320 if (etm->tracemode != tracemode)
1322 reg_t *etm_ctrl_reg;
1324 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1328 etm_get_reg(etm_ctrl_reg);
1330 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1331 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1332 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1333 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1334 etm_store_reg(etm_ctrl_reg);
1336 etm->tracemode = tracemode;
1338 /* invalidate old trace data */
1339 etm->capture_status = TRACE_IDLE;
1340 if (etm->trace_depth > 0)
1342 free(etm->trace_data);
1343 etm->trace_data = NULL;
1345 etm->trace_depth = 0;
1351 static int handle_etm_config_command(struct command_context_s *cmd_ctx,
1352 char *cmd, char **args, int argc)
1356 etm_portmode_t portmode = 0x0;
1357 struct etm *etm_ctx;
1361 return ERROR_COMMAND_SYNTAX_ERROR;
1363 target = get_target(args[0]);
1366 LOG_ERROR("target '%s' not defined", args[0]);
1370 arm = target_to_arm(target);
1372 command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
1373 target->cmd_name, target_get_name(target));
1378 COMMAND_PARSE_NUMBER(u8, args[1], port_width);
1382 portmode |= ETM_PORT_4BIT;
1385 portmode |= ETM_PORT_8BIT;
1388 portmode |= ETM_PORT_16BIT;
1391 command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1395 if (strcmp("normal", args[2]) == 0)
1397 portmode |= ETM_PORT_NORMAL;
1399 else if (strcmp("multiplexed", args[2]) == 0)
1401 portmode |= ETM_PORT_MUXED;
1403 else if (strcmp("demultiplexed", args[2]) == 0)
1405 portmode |= ETM_PORT_DEMUXED;
1409 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1413 if (strcmp("half", args[3]) == 0)
1415 portmode |= ETM_PORT_HALF_CLOCK;
1417 else if (strcmp("full", args[3]) == 0)
1419 portmode |= ETM_PORT_FULL_CLOCK;
1423 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1427 etm_ctx = calloc(1, sizeof(etm_context_t));
1429 LOG_DEBUG("out of memory");
1433 for (i = 0; etm_capture_drivers[i]; i++)
1435 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1438 if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1444 etm_ctx->capture_driver = etm_capture_drivers[i];
1450 if (!etm_capture_drivers[i])
1452 /* no supported capture driver found, don't register an ETM */
1454 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1458 etm_ctx->target = target;
1459 etm_ctx->trigger_percent = 50;
1460 etm_ctx->trace_data = NULL;
1461 etm_ctx->portmode = portmode;
1462 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1466 return etm_register_user_commands(cmd_ctx);
1469 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1470 char *cmd, char **args, int argc)
1475 reg_t *etm_sys_config_reg;
1478 target = get_current_target(cmd_ctx);
1479 arm = target_to_arm(target);
1482 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1489 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1493 command_print(cmd_ctx, "ETM v%d.%d",
1494 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1495 command_print(cmd_ctx, "pairs of address comparators: %i",
1496 (int) (etm->config >> 0) & 0x0f);
1497 command_print(cmd_ctx, "data comparators: %i",
1498 (int) (etm->config >> 4) & 0x0f);
1499 command_print(cmd_ctx, "memory map decoders: %i",
1500 (int) (etm->config >> 8) & 0x1f);
1501 command_print(cmd_ctx, "number of counters: %i",
1502 (int) (etm->config >> 13) & 0x07);
1503 command_print(cmd_ctx, "sequencer %spresent",
1504 (int) (etm->config & (1 << 16)) ? "" : "not ");
1505 command_print(cmd_ctx, "number of ext. inputs: %i",
1506 (int) (etm->config >> 17) & 0x07);
1507 command_print(cmd_ctx, "number of ext. outputs: %i",
1508 (int) (etm->config >> 20) & 0x07);
1509 command_print(cmd_ctx, "FIFO full %spresent",
1510 (int) (etm->config & (1 << 23)) ? "" : "not ");
1511 if (etm->bcd_vers < 0x20)
1512 command_print(cmd_ctx, "protocol version: %i",
1513 (int) (etm->config >> 28) & 0x07);
1515 command_print(cmd_ctx, "trace start/stop %spresent",
1516 (etm->config & (1 << 26)) ? "" : "not ");
1517 command_print(cmd_ctx, "number of context comparators: %i",
1518 (int) (etm->config >> 24) & 0x03);
1521 /* SYS_CONFIG isn't present before ETMv1.2 */
1522 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1523 if (!etm_sys_config_reg)
1526 etm_get_reg(etm_sys_config_reg);
1528 switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1540 LOG_ERROR("Illegal max_port_size");
1543 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1545 command_print(cmd_ctx, "half-rate clocking %ssupported",
1546 (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1547 command_print(cmd_ctx, "full-rate clocking %ssupported",
1548 (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1549 command_print(cmd_ctx, "normal trace format %ssupported",
1550 (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1551 command_print(cmd_ctx, "multiplex trace format %ssupported",
1552 (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1553 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1554 (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1555 command_print(cmd_ctx, "FIFO full %ssupported",
1556 (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1561 static int handle_etm_status_command(struct command_context_s *cmd_ctx,
1562 char *cmd, char **args, int argc)
1567 trace_status_t trace_status;
1569 target = get_current_target(cmd_ctx);
1570 arm = target_to_arm(target);
1573 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1580 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1585 if (etm->bcd_vers >= 0x11) {
1588 reg = etm_reg_lookup(etm, ETM_STATUS);
1591 if (etm_get_reg(reg) == ERROR_OK) {
1592 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1594 command_print(cmd_ctx, "etm: %s%s%s%s",
1595 /* bit(1) == progbit */
1596 (etm->bcd_vers >= 0x12)
1598 ? "disabled" : "enabled")
1600 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1601 ? " triggered" : "",
1602 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1603 ? " start/stop" : "",
1604 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1605 ? " untraced-overflow" : "");
1606 } /* else ignore and try showing trace port status */
1609 /* Trace Port Driver status */
1610 trace_status = etm->capture_driver->status(etm);
1611 if (trace_status == TRACE_IDLE)
1613 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1617 static char *completed = " completed";
1618 static char *running = " is running";
1619 static char *overflowed = ", overflowed";
1620 static char *triggered = ", triggered";
1622 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1623 etm->capture_driver->name,
1624 (trace_status & TRACE_RUNNING) ? running : completed,
1625 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1626 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1628 if (etm->trace_depth > 0)
1630 command_print(cmd_ctx, "%i frames of trace data read",
1631 (int)(etm->trace_depth));
1638 static int handle_etm_image_command(struct command_context_s *cmd_ctx,
1639 char *cmd, char **args, int argc)
1643 etm_context_t *etm_ctx;
1647 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1651 target = get_current_target(cmd_ctx);
1652 arm = target_to_arm(target);
1655 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1662 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1668 image_close(etm_ctx->image);
1669 free(etm_ctx->image);
1670 command_print(cmd_ctx, "previously loaded image found and closed");
1673 etm_ctx->image = malloc(sizeof(image_t));
1674 etm_ctx->image->base_address_set = 0;
1675 etm_ctx->image->start_address_set = 0;
1677 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1680 etm_ctx->image->base_address_set = 1;
1681 COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
1685 etm_ctx->image->base_address_set = 0;
1688 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1690 free(etm_ctx->image);
1691 etm_ctx->image = NULL;
1698 static int handle_etm_dump_command(struct command_context_s *cmd_ctx,
1699 char *cmd, char **args, int argc)
1704 etm_context_t *etm_ctx;
1709 command_print(cmd_ctx, "usage: etm dump <file>");
1713 target = get_current_target(cmd_ctx);
1714 arm = target_to_arm(target);
1717 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1724 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1728 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1730 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1734 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1736 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1737 command_print(cmd_ctx, "trace capture not completed");
1741 /* read the trace data if it wasn't read already */
1742 if (etm_ctx->trace_depth == 0)
1743 etm_ctx->capture_driver->read_trace(etm_ctx);
1745 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1750 fileio_write_u32(&file, etm_ctx->capture_status);
1751 fileio_write_u32(&file, etm_ctx->portmode);
1752 fileio_write_u32(&file, etm_ctx->tracemode);
1753 fileio_write_u32(&file, etm_ctx->trace_depth);
1755 for (i = 0; i < etm_ctx->trace_depth; i++)
1757 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1758 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1759 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1762 fileio_close(&file);
1767 static int handle_etm_load_command(struct command_context_s *cmd_ctx,
1768 char *cmd, char **args, int argc)
1773 etm_context_t *etm_ctx;
1778 command_print(cmd_ctx, "usage: etm load <file>");
1782 target = get_current_target(cmd_ctx);
1783 arm = target_to_arm(target);
1786 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1793 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1797 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1799 command_print(cmd_ctx, "trace capture running, stop first");
1803 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1810 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1811 fileio_close(&file);
1815 if (etm_ctx->trace_depth > 0)
1817 free(etm_ctx->trace_data);
1818 etm_ctx->trace_data = NULL;
1823 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1824 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1825 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1826 fileio_read_u32(&file, &etm_ctx->trace_depth);
1828 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1829 if (etm_ctx->trace_data == NULL)
1831 command_print(cmd_ctx, "not enough memory to perform operation");
1832 fileio_close(&file);
1836 for (i = 0; i < etm_ctx->trace_depth; i++)
1838 uint32_t pipestat, packet, flags;
1839 fileio_read_u32(&file, &pipestat);
1840 fileio_read_u32(&file, &packet);
1841 fileio_read_u32(&file, &flags);
1842 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1843 etm_ctx->trace_data[i].packet = packet & 0xffff;
1844 etm_ctx->trace_data[i].flags = flags;
1847 fileio_close(&file);
1852 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx,
1853 char *cmd, char **args, int argc)
1857 etm_context_t *etm_ctx;
1859 target = get_current_target(cmd_ctx);
1860 arm = target_to_arm(target);
1863 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1870 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1877 COMMAND_PARSE_NUMBER(u32, args[0], new_value);
1879 if ((new_value < 2) || (new_value > 100))
1881 command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1885 etm_ctx->trigger_percent = new_value;
1889 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1894 static int handle_etm_start_command(struct command_context_s *cmd_ctx,
1895 char *cmd, char **args, int argc)
1899 etm_context_t *etm_ctx;
1900 reg_t *etm_ctrl_reg;
1902 target = get_current_target(cmd_ctx);
1903 arm = target_to_arm(target);
1906 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1913 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1917 /* invalidate old tracing data */
1918 etm_ctx->capture_status = TRACE_IDLE;
1919 if (etm_ctx->trace_depth > 0)
1921 free(etm_ctx->trace_data);
1922 etm_ctx->trace_data = NULL;
1924 etm_ctx->trace_depth = 0;
1926 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1930 etm_get_reg(etm_ctrl_reg);
1932 /* Clear programming bit (10), set port selection bit (11) */
1933 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1935 etm_store_reg(etm_ctrl_reg);
1936 jtag_execute_queue();
1938 etm_ctx->capture_driver->start_capture(etm_ctx);
1943 static int handle_etm_stop_command(struct command_context_s *cmd_ctx,
1944 char *cmd, char **args, int argc)
1948 etm_context_t *etm_ctx;
1949 reg_t *etm_ctrl_reg;
1951 target = get_current_target(cmd_ctx);
1952 arm = target_to_arm(target);
1955 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1962 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1966 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1970 etm_get_reg(etm_ctrl_reg);
1972 /* Set programming bit (10), clear port selection bit (11) */
1973 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1975 etm_store_reg(etm_ctrl_reg);
1976 jtag_execute_queue();
1978 etm_ctx->capture_driver->stop_capture(etm_ctx);
1983 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx,
1984 char *cmd, char **args, int argc)
1988 etm_context_t *etm_ctx;
1991 target = get_current_target(cmd_ctx);
1992 arm = target_to_arm(target);
1995 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2002 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2006 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2010 case ERROR_ETM_ANALYSIS_FAILED:
2011 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2013 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2014 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2016 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2017 command_print(cmd_ctx, "no image available for trace analysis");
2020 command_print(cmd_ctx, "unknown error: %i", retval);
2027 int etm_register_commands(struct command_context_s *cmd_ctx)
2029 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2031 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2032 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2037 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2039 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2040 COMMAND_EXEC, "configure/display trace mode: "
2041 "<none | data | address | all> "
2042 "<context_id_bits> <cycle_accurate> <branch_output>");
2044 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2045 COMMAND_EXEC, "display info about the current target's ETM");
2047 register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2048 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2049 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2050 COMMAND_EXEC, "display current target's ETM status");
2051 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2052 COMMAND_EXEC, "start ETM trace collection");
2053 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2054 COMMAND_EXEC, "stop ETM trace collection");
2056 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2057 COMMAND_EXEC, "anaylze collected ETM trace");
2059 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2060 COMMAND_EXEC, "load image from <file> [base address]");
2062 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2063 COMMAND_EXEC, "dump captured trace data <file>");
2064 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2065 COMMAND_EXEC, "load trace data for analysis <file>");