git.sur5r.net Git - openocd/blob - src/target/etm.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "etm.h"
  27 #include "etb.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31 #include "arm_disassembler.h"
  32 #include "arm_simulator.h"
  33
  34 #include "log.h"
  35 #include "arm_jtag.h"
  36 #include "types.h"
  37 #include "binarybuffer.h"
  38 #include "target.h"
  39 #include "register.h"
  40 #include "jtag.h"
  41 #include "fileio.h"
  42
  43 #include <stdlib.h>
  44
  45 /* ETM register access functionality
  46  *
  47  */
  48
  49 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
  50 {
  51         {"R", 1},
  52         {"W", 1},
  53         {"reserved", 26},
  54         {"version", 4}
  55 };
  56
  57 int etm_reg_arch_info[] =
  58 {
  59         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  60         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  61         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  62         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
  63         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  64         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  65         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
  66         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
  67         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  68         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  69         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  70         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  71         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
  72         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  73 };
  74
  75 int etm_reg_arch_size_info[] =
  76 {
  77         32, 32, 17, 8, 3, 9, 32, 16,
  78         17, 26, 25, 8, 17, 32, 32, 17,
  79         32, 32, 32, 32, 32, 32, 32, 32,
  80         32, 32, 32, 32, 32, 32, 32, 32,
  81         7, 7, 7, 7, 7, 7, 7, 7,
  82         7, 7, 7, 7, 7, 7, 7, 7,
  83         32, 32, 32, 32, 32, 32, 32, 32,
  84         32, 32, 32, 32, 32, 32, 32, 32,
  85         32, 32, 32, 32, 32, 32, 32, 32,
  86         32, 32, 32, 32, 32, 32, 32, 32,
  87         16, 16, 16, 16, 18, 18, 18, 18,
  88         17, 17, 17, 17, 16, 16, 16, 16,
  89         17, 17, 17, 17, 17, 17, 2,
  90         17, 17, 17, 17, 32, 32, 32, 32
  91 };
  92
  93 char* etm_reg_list[] =
  94 {
  95         "ETM_CTRL",
  96         "ETM_CONFIG",
  97         "ETM_TRIG_EVENT",
  98         "ETM_MMD_CTRL",
  99         "ETM_STATUS",
 100         "ETM_SYS_CONFIG",
 101         "ETM_TRACE_RESOURCE_CTRL",
 102         "ETM_TRACE_EN_CTRL2",
 103         "ETM_TRACE_EN_EVENT",
 104         "ETM_TRACE_EN_CTRL1",
 105         "ETM_FIFOFULL_REGION",
 106         "ETM_FIFOFULL_LEVEL",
 107         "ETM_VIEWDATA_EVENT",
 108         "ETM_VIEWDATA_CTRL1",
 109         "ETM_VIEWDATA_CTRL2",
 110         "ETM_VIEWDATA_CTRL3",
 111         "ETM_ADDR_COMPARATOR_VALUE1",
 112         "ETM_ADDR_COMPARATOR_VALUE2",
 113         "ETM_ADDR_COMPARATOR_VALUE3",
 114         "ETM_ADDR_COMPARATOR_VALUE4",
 115         "ETM_ADDR_COMPARATOR_VALUE5",
 116         "ETM_ADDR_COMPARATOR_VALUE6",
 117         "ETM_ADDR_COMPARATOR_VALUE7",
 118         "ETM_ADDR_COMPARATOR_VALUE8",
 119         "ETM_ADDR_COMPARATOR_VALUE9",
 120         "ETM_ADDR_COMPARATOR_VALUE10",
 121         "ETM_ADDR_COMPARATOR_VALUE11",
 122         "ETM_ADDR_COMPARATOR_VALUE12",
 123         "ETM_ADDR_COMPARATOR_VALUE13",
 124         "ETM_ADDR_COMPARATOR_VALUE14",
 125         "ETM_ADDR_COMPARATOR_VALUE15",
 126         "ETM_ADDR_COMPARATOR_VALUE16",
 127         "ETM_ADDR_ACCESS_TYPE1",
 128         "ETM_ADDR_ACCESS_TYPE2",
 129         "ETM_ADDR_ACCESS_TYPE3",
 130         "ETM_ADDR_ACCESS_TYPE4",
 131         "ETM_ADDR_ACCESS_TYPE5",
 132         "ETM_ADDR_ACCESS_TYPE6",
 133         "ETM_ADDR_ACCESS_TYPE7",
 134         "ETM_ADDR_ACCESS_TYPE8",
 135         "ETM_ADDR_ACCESS_TYPE9",
 136         "ETM_ADDR_ACCESS_TYPE10",
 137         "ETM_ADDR_ACCESS_TYPE11",
 138         "ETM_ADDR_ACCESS_TYPE12",
 139         "ETM_ADDR_ACCESS_TYPE13",
 140         "ETM_ADDR_ACCESS_TYPE14",
 141         "ETM_ADDR_ACCESS_TYPE15",
 142         "ETM_ADDR_ACCESS_TYPE16",
 143         "ETM_DATA_COMPARATOR_VALUE1",
 144         "ETM_DATA_COMPARATOR_VALUE2",
 145         "ETM_DATA_COMPARATOR_VALUE3",
 146         "ETM_DATA_COMPARATOR_VALUE4",
 147         "ETM_DATA_COMPARATOR_VALUE5",
 148         "ETM_DATA_COMPARATOR_VALUE6",
 149         "ETM_DATA_COMPARATOR_VALUE7",
 150         "ETM_DATA_COMPARATOR_VALUE8",
 151         "ETM_DATA_COMPARATOR_VALUE9",
 152         "ETM_DATA_COMPARATOR_VALUE10",
 153         "ETM_DATA_COMPARATOR_VALUE11",
 154         "ETM_DATA_COMPARATOR_VALUE12",
 155         "ETM_DATA_COMPARATOR_VALUE13",
 156         "ETM_DATA_COMPARATOR_VALUE14",
 157         "ETM_DATA_COMPARATOR_VALUE15",
 158         "ETM_DATA_COMPARATOR_VALUE16",
 159         "ETM_DATA_COMPARATOR_MASK1",
 160         "ETM_DATA_COMPARATOR_MASK2",
 161         "ETM_DATA_COMPARATOR_MASK3",
 162         "ETM_DATA_COMPARATOR_MASK4",
 163         "ETM_DATA_COMPARATOR_MASK5",
 164         "ETM_DATA_COMPARATOR_MASK6",
 165         "ETM_DATA_COMPARATOR_MASK7",
 166         "ETM_DATA_COMPARATOR_MASK8",
 167         "ETM_DATA_COMPARATOR_MASK9",
 168         "ETM_DATA_COMPARATOR_MASK10",
 169         "ETM_DATA_COMPARATOR_MASK11",
 170         "ETM_DATA_COMPARATOR_MASK12",
 171         "ETM_DATA_COMPARATOR_MASK13",
 172         "ETM_DATA_COMPARATOR_MASK14",
 173         "ETM_DATA_COMPARATOR_MASK15",
 174         "ETM_DATA_COMPARATOR_MASK16",
 175         "ETM_COUNTER_INITAL_VALUE1",
 176         "ETM_COUNTER_INITAL_VALUE2",
 177         "ETM_COUNTER_INITAL_VALUE3",
 178         "ETM_COUNTER_INITAL_VALUE4",
 179         "ETM_COUNTER_ENABLE1",
 180         "ETM_COUNTER_ENABLE2",
 181         "ETM_COUNTER_ENABLE3",
 182         "ETM_COUNTER_ENABLE4",
 183         "ETM_COUNTER_RELOAD_VALUE1",
 184         "ETM_COUNTER_RELOAD_VALUE2",
 185         "ETM_COUNTER_RELOAD_VALUE3",
 186         "ETM_COUNTER_RELOAD_VALUE4",
 187         "ETM_COUNTER_VALUE1",
 188         "ETM_COUNTER_VALUE2",
 189         "ETM_COUNTER_VALUE3",
 190         "ETM_COUNTER_VALUE4",
 191         "ETM_SEQUENCER_CTRL1",
 192         "ETM_SEQUENCER_CTRL2",
 193         "ETM_SEQUENCER_CTRL3",
 194         "ETM_SEQUENCER_CTRL4",
 195         "ETM_SEQUENCER_CTRL5",
 196         "ETM_SEQUENCER_CTRL6",
 197         "ETM_SEQUENCER_STATE",
 198         "ETM_EXTERNAL_OUTPUT1",
 199         "ETM_EXTERNAL_OUTPUT2",
 200         "ETM_EXTERNAL_OUTPUT3",
 201         "ETM_EXTERNAL_OUTPUT4",
 202         "ETM_CONTEXTID_COMPARATOR_VALUE1",
 203         "ETM_CONTEXTID_COMPARATOR_VALUE2",
 204         "ETM_CONTEXTID_COMPARATOR_VALUE3",
 205         "ETM_CONTEXTID_COMPARATOR_MASK"
 206 };
 207
 208 int etm_reg_arch_type = -1;
 209
 210 int etm_get_reg(reg_t *reg);
 211 int etm_set_reg(reg_t *reg, u32 value);
 212 int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
 213
 214 int etm_write_reg(reg_t *reg, u32 value);
 215 int etm_read_reg(reg_t *reg);
 216
 217 command_t *etm_cmd = NULL;
 218
 219 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 220 {
 221         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 222         reg_t *reg_list = NULL;
 223         etm_reg_t *arch_info = NULL;
 224         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
 225         int i;
 226         u32 etm_ctrl_value;
 227
 228         /* register a register arch-type for etm registers only once */
 229         if (etm_reg_arch_type == -1)
 230                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
 231
 232         /* the actual registers are kept in two arrays */
 233         reg_list = calloc(num_regs, sizeof(reg_t));
 234         arch_info = calloc(num_regs, sizeof(etm_reg_t));
 235
 236         /* fill in values for the reg cache */
 237         reg_cache->name = "etm registers";
 238         reg_cache->next = NULL;
 239         reg_cache->reg_list = reg_list;
 240         reg_cache->num_regs = num_regs;
 241
 242         /* set up registers */
 243         for (i = 0; i < num_regs; i++)
 244         {
 245                 reg_list[i].name = etm_reg_list[i];
 246                 reg_list[i].size = 32;
 247                 reg_list[i].dirty = 0;
 248                 reg_list[i].valid = 0;
 249                 reg_list[i].bitfield_desc = NULL;
 250                 reg_list[i].num_bitfields = 0;
 251                 reg_list[i].value = calloc(1, 4);
 252                 reg_list[i].arch_info = &arch_info[i];
 253                 reg_list[i].arch_type = etm_reg_arch_type;
 254                 reg_list[i].size = etm_reg_arch_size_info[i];
 255                 arch_info[i].addr = etm_reg_arch_info[i];
 256                 arch_info[i].jtag_info = jtag_info;
 257         }
 258
 259         /* initialize some ETM control register settings */
 260         etm_get_reg(&reg_list[ETM_CTRL]);
 261         etm_ctrl_value = buf_get_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size);
 262
 263         /* clear the ETM powerdown bit (0) */
 264         etm_ctrl_value &= ~0x1;
 265
 266         /* configure port width (6:4), mode (17:16) and clocking (13) */
 267         etm_ctrl_value = (etm_ctrl_value &
 268                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 269                 | etm_ctx->portmode;
 270
 271         buf_set_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size, etm_ctrl_value);
 272         etm_store_reg(&reg_list[ETM_CTRL]);
 273
 274         /* the ETM might have an ETB connected */
 275         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 276         {
 277                 etb_t *etb = etm_ctx->capture_driver_priv;
 278
 279                 if (!etb)
 280                 {
 281                         ERROR("etb selected as etm capture driver, but no ETB configured");
 282                         return ERROR_OK;
 283                 }
 284
 285                 reg_cache->next = etb_build_reg_cache(etb);
 286
 287                 etb->reg_cache = reg_cache->next;
 288
 289                 if (etm_ctx->capture_driver->init(etm_ctx) != ERROR_OK)
 290                 {
 291                         ERROR("ETM capture driver initialization failed");
 292                         exit(-1);
 293                 }
 294         }
 295
 296         return reg_cache;
 297 }
 298
 299 int etm_get_reg(reg_t *reg)
 300 {
 301         if (etm_read_reg(reg) != ERROR_OK)
 302         {
 303                 ERROR("BUG: error scheduling etm register read");
 304                 exit(-1);
 305         }
 306
 307         if (jtag_execute_queue() != ERROR_OK)
 308         {
 309                 ERROR("register read failed");
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 316 {
 317         etm_reg_t *etm_reg = reg->arch_info;
 318         u8 reg_addr = etm_reg->addr & 0x7f;
 319         scan_field_t fields[3];
 320
 321         DEBUG("%i", etm_reg->addr);
 322
 323         jtag_add_end_state(TAP_RTI);
 324         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 325         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 326
 327         fields[0].device = etm_reg->jtag_info->chain_pos;
 328         fields[0].num_bits = 32;
 329         fields[0].out_value = reg->value;
 330         fields[0].out_mask = NULL;
 331         fields[0].in_value = NULL;
 332         fields[0].in_check_value = NULL;
 333         fields[0].in_check_mask = NULL;
 334         fields[0].in_handler = NULL;
 335         fields[0].in_handler_priv = NULL;
 336
 337         fields[1].device = etm_reg->jtag_info->chain_pos;
 338         fields[1].num_bits = 7;
 339         fields[1].out_value = malloc(1);
 340         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 341         fields[1].out_mask = NULL;
 342         fields[1].in_value = NULL;
 343         fields[1].in_check_value = NULL;
 344         fields[1].in_check_mask = NULL;
 345         fields[1].in_handler = NULL;
 346         fields[1].in_handler_priv = NULL;
 347
 348         fields[2].device = etm_reg->jtag_info->chain_pos;
 349         fields[2].num_bits = 1;
 350         fields[2].out_value = malloc(1);
 351         buf_set_u32(fields[2].out_value, 0, 1, 0);
 352         fields[2].out_mask = NULL;
 353         fields[2].in_value = NULL;
 354         fields[2].in_check_value = NULL;
 355         fields[2].in_check_mask = NULL;
 356         fields[2].in_handler = NULL;
 357         fields[2].in_handler_priv = NULL;
 358
 359         jtag_add_dr_scan(3, fields, -1, NULL);
 360
 361         fields[0].in_value = reg->value;
 362         fields[0].in_check_value = check_value;
 363         fields[0].in_check_mask = check_mask;
 364
 365         jtag_add_dr_scan(3, fields, -1, NULL);
 366
 367         free(fields[1].out_value);
 368         free(fields[2].out_value);
 369
 370         return ERROR_OK;
 371 }
 372
 373 int etm_read_reg(reg_t *reg)
 374 {
 375         return etm_read_reg_w_check(reg, NULL, NULL);
 376 }
 377
 378 int etm_set_reg(reg_t *reg, u32 value)
 379 {
 380         if (etm_write_reg(reg, value) != ERROR_OK)
 381         {
 382                 ERROR("BUG: error scheduling etm register write");
 383                 exit(-1);
 384         }
 385
 386         buf_set_u32(reg->value, 0, reg->size, value);
 387         reg->valid = 1;
 388         reg->dirty = 0;
 389
 390         return ERROR_OK;
 391 }
 392
 393 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 394 {
 395         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 396
 397         if (jtag_execute_queue() != ERROR_OK)
 398         {
 399                 ERROR("register write failed");
 400                 exit(-1);
 401         }
 402         return ERROR_OK;
 403 }
 404
 405 int etm_write_reg(reg_t *reg, u32 value)
 406 {
 407         etm_reg_t *etm_reg = reg->arch_info;
 408         u8 reg_addr = etm_reg->addr & 0x7f;
 409         scan_field_t fields[3];
 410
 411         DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 412
 413         jtag_add_end_state(TAP_RTI);
 414         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 415         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 416
 417         fields[0].device = etm_reg->jtag_info->chain_pos;
 418         fields[0].num_bits = 32;
 419         fields[0].out_value = malloc(4);
 420         buf_set_u32(fields[0].out_value, 0, 32, value);
 421         fields[0].out_mask = NULL;
 422         fields[0].in_value = NULL;
 423         fields[0].in_check_value = NULL;
 424         fields[0].in_check_mask = NULL;
 425         fields[0].in_handler = NULL;
 426         fields[0].in_handler_priv = NULL;
 427
 428         fields[1].device = etm_reg->jtag_info->chain_pos;
 429         fields[1].num_bits = 7;
 430         fields[1].out_value = malloc(1);
 431         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 432         fields[1].out_mask = NULL;
 433         fields[1].in_value = NULL;
 434         fields[1].in_check_value = NULL;
 435         fields[1].in_check_mask = NULL;
 436         fields[1].in_handler = NULL;
 437         fields[1].in_handler_priv = NULL;
 438
 439         fields[2].device = etm_reg->jtag_info->chain_pos;
 440         fields[2].num_bits = 1;
 441         fields[2].out_value = malloc(1);
 442         buf_set_u32(fields[2].out_value, 0, 1, 1);
 443         fields[2].out_mask = NULL;
 444         fields[2].in_value = NULL;
 445         fields[2].in_check_value = NULL;
 446         fields[2].in_check_mask = NULL;
 447         fields[2].in_handler = NULL;
 448         fields[2].in_handler_priv = NULL;
 449
 450         jtag_add_dr_scan(3, fields, -1, NULL);
 451
 452         free(fields[0].out_value);
 453         free(fields[1].out_value);
 454         free(fields[2].out_value);
 455
 456         return ERROR_OK;
 457 }
 458
 459 int etm_store_reg(reg_t *reg)
 460 {
 461         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 462 }
 463
 464 /* ETM trace analysis functionality
 465  *
 466  */
 467 extern etm_capture_driver_t etb_capture_driver;
 468
 469 etm_capture_driver_t *etm_capture_drivers[] =
 470 {
 471         &etb_capture_driver,
 472         NULL
 473 };
 474
 475 char *etmv1v1_branch_reason_strings[] =
 476 {
 477         "normal PC change",
 478         "tracing enabled",
 479         "trace restarted after overflow",
 480         "exit from debug",
 481         "periodic synchronization",
 482         "reserved",
 483         "reserved",
 484         "reserved",
 485 };
 486
 487 int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 488 {
 489         int i;
 490         int section = -1;
 491         u32 size_read;
 492         u32 opcode;
 493         int retval;
 494
 495         if (!ctx->image)
 496                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 497
 498         /* search for the section the current instruction belongs to */
 499         for (i = 0; i < ctx->image->num_sections; i++)
 500         {
 501                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 502                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 503                 {
 504                         section = i;
 505                         break;
 506                 }
 507         }
 508
 509         if (section == -1)
 510         {
 511                 /* current instruction couldn't be found in the image */
 512                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 513         }
 514
 515         if (ctx->core_state == ARMV4_5_STATE_ARM)
 516         {
 517                 u8 buf[4];
 518                 if ((retval = image_read_section(ctx->image, section,
 519                         ctx->current_pc - ctx->image->sections[section].base_address,
 520                         4, buf, &size_read)) != ERROR_OK)
 521                 {
 522                         ERROR("error while reading instruction: %i", retval);
 523                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 524                 }
 525                 opcode = target_buffer_get_u32(ctx->target, buf);
 526                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 527         }
 528         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 529         {
 530                 u8 buf[2];
 531                 if ((retval = image_read_section(ctx->image, section,
 532                         ctx->current_pc - ctx->image->sections[section].base_address,
 533                         2, buf, &size_read)) != ERROR_OK)
 534                 {
 535                         ERROR("error while reading instruction: %i", retval);
 536                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 537                 }
 538                 opcode = target_buffer_get_u16(ctx->target, buf);
 539                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 540         }
 541         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 542         {
 543                 ERROR("BUG: tracing of jazelle code not supported");
 544                 exit(-1);
 545         }
 546         else
 547         {
 548                 ERROR("BUG: unknown core state encountered");
 549                 exit(-1);
 550         }
 551
 552         return ERROR_OK;
 553 }
 554
 555 int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 556 {
 557         while (ctx->data_index < ctx->trace_depth)
 558         {
 559                 /* if the caller specified an address packet offset, skip until the
 560                  * we reach the n-th cycle marked with tracesync */
 561                 if (apo > 0)
 562                 {
 563                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 564                                 apo--;
 565
 566                         if (apo > 0)
 567                         {
 568                                 ctx->data_index++;
 569                                 ctx->data_half = 0;
 570                         }
 571                         continue;
 572                 }
 573
 574                 /* no tracedata output during a TD cycle
 575                  * or in a trigger cycle */
 576                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 577                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 578                 {
 579                         ctx->data_index++;
 580                         ctx->data_half = 0;
 581                         continue;
 582                 }
 583
 584                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 585                 {
 586                         if (ctx->data_half == 0)
 587                         {
 588                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 589                                 ctx->data_half = 1;
 590                         }
 591                         else
 592                         {
 593                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 594                                 ctx->data_half = 0;
 595                                 ctx->data_index++;
 596                         }
 597                 }
 598                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 599                 {
 600                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 601                         ctx->data_index++;
 602                 }
 603                 else
 604                 {
 605                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 606                         if (ctx->data_index > (ctx->trace_depth - 2))
 607                                 return -1;
 608
 609                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 610                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 611                         ctx->data_index += 2;
 612                 }
 613
 614                 return 0;
 615         }
 616
 617         return -1;
 618 }
 619
 620 int etmv1_branch_address(etm_context_t *ctx)
 621 {
 622         int retval;
 623         u8 packet;
 624         int shift = 0;
 625         int apo;
 626         int i;
 627
 628         /* quit analysis if less than two cycles are left in the trace
 629          * because we can't extract the APO */
 630         if (ctx->data_index > (ctx->trace_depth - 2))
 631                 return -1;
 632
 633         /* a BE could be output during an APO cycle, skip the current
 634          * and continue with the new one */
 635         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 636                 return 1;
 637         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 638                 return 2;
 639
 640         /* address packet offset encoded in the next two cycles' pipestat bits */
 641         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 642         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 643
 644         /* count number of tracesync cycles between current pipe_index and data_index
 645          * i.e. the number of tracesyncs that data_index already passed by
 646          * to subtract them from the APO */
 647         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 648         {
 649                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 650                         apo--;
 651         }
 652
 653         /* extract up to four 7-bit packets */
 654         do {
 655                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 656                         return -1;
 657                 ctx->last_branch &= ~(0x7f << shift);
 658                 ctx->last_branch |= (packet & 0x7f) << shift;
 659                 shift += 7;
 660         } while ((packet & 0x80) && (shift < 28));
 661
 662         /* one last packet holding 4 bits of the address, plus the branch reason code */
 663         if ((shift == 28) && (packet & 0x80))
 664         {
 665                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 666                         return -1;
 667                 ctx->last_branch &= 0x0fffffff;
 668                 ctx->last_branch |= (packet & 0x0f) << 28;
 669                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 670                 shift += 4;
 671         }
 672         else
 673         {
 674                 ctx->last_branch_reason = 0;
 675         }
 676
 677         if (shift == 32)
 678         {
 679                 ctx->pc_ok = 1;
 680         }
 681
 682         /* if a full address was output, we might have branched into Jazelle state */
 683         if ((shift == 32) && (packet & 0x80))
 684         {
 685                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 686         }
 687         else
 688         {
 689                 /* if we didn't branch into Jazelle state, the current processor state is
 690                  * encoded in bit 0 of the branch target address */
 691                 if (ctx->last_branch & 0x1)
 692                 {
 693                         ctx->core_state = ARMV4_5_STATE_THUMB;
 694                         ctx->last_branch &= ~0x1;
 695                 }
 696                 else
 697                 {
 698                         ctx->core_state = ARMV4_5_STATE_ARM;
 699                         ctx->last_branch &= ~0x3;
 700                 }
 701         }
 702
 703         return 0;
 704 }
 705
 706 int etmv1_data(etm_context_t *ctx, int size, u32 *data)
 707 {
 708         int j;
 709         u8 buf[4];
 710         int retval;
 711
 712         for (j = 0; j < size; j++)
 713         {
 714                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 715                         return -1;
 716         }
 717
 718         if (size == 8)
 719                 ERROR("TODO: add support for 64-bit values");
 720         else if (size == 4)
 721                 *data = target_buffer_get_u32(ctx->target, buf);
 722         else if (size == 2)
 723                 *data = target_buffer_get_u16(ctx->target, buf);
 724         else if (size == 1)
 725                 *data = buf[0];
 726
 727         return 0;
 728 }
 729
 730 int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 731 {
 732         int retval;
 733         arm_instruction_t instruction;
 734
 735         /* read the trace data if it wasn't read already */
 736         if (ctx->trace_depth == 0)
 737                 ctx->capture_driver->read_trace(ctx);
 738
 739         /* start at the beginning of the captured trace */
 740         ctx->pipe_index = 0;
 741         ctx->data_index = 0;
 742         ctx->data_half = 0;
 743
 744         /* neither the PC nor the data pointer are valid */
 745         ctx->pc_ok = 0;
 746         ctx->ptr_ok = 0;
 747
 748         while (ctx->pipe_index < ctx->trace_depth)
 749         {
 750                 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 751                 u32 next_pc = ctx->current_pc;
 752                 u32 old_data_index = ctx->data_index;
 753                 u32 old_data_half = ctx->data_half;
 754
 755                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 756                 {
 757                         command_print(cmd_ctx, "--- trigger ---");
 758                 }
 759
 760                 /* if we don't have a valid pc skip until we reach an indirect branch */
 761                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 762                 {
 763                         ctx->pipe_index++;
 764                         continue;
 765                 }
 766
 767                 /* any indirect branch could have interrupted instruction flow
 768                  * - the branch reason code could indicate a trace discontinuity
 769                  * - a branch to the exception vectors indicates an exception
 770                  */
 771                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 772                 {
 773                         /* backup current data index, to be able to consume the branch address
 774                          * before examining data address and values
 775                          */
 776                         old_data_index = ctx->data_index;
 777                         old_data_half = ctx->data_half;
 778
 779                         if ((retval = etmv1_branch_address(ctx)) != 0)
 780                         {
 781                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 782                                  * quit analysing the trace */
 783                                 if (retval < 0)
 784                                         break;
 785
 786                                 /* a positive return values means the current branch was abandoned,
 787                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 788                                  */
 789                                 WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 790                                 ctx->pipe_index += retval;
 791                                 continue;
 792                         }
 793
 794                         /* skip over APO cycles */
 795                         ctx->pipe_index += 2;
 796
 797                         switch (ctx->last_branch_reason)
 798                         {
 799                                 case 0x0:       /* normal PC change */
 800                                         next_pc = ctx->last_branch;
 801                                         break;
 802                                 case 0x1:       /* tracing enabled */
 803                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
 804                                         ctx->current_pc = ctx->last_branch;
 805                                         ctx->pipe_index++;
 806                                         continue;
 807                                         break;
 808                                 case 0x2:       /* trace restarted after FIFO overflow */
 809                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
 810                                         ctx->current_pc = ctx->last_branch;
 811                                         ctx->pipe_index++;
 812                                         continue;
 813                                         break;
 814                                 case 0x3:       /* exit from debug state */
 815                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
 816                                         ctx->current_pc = ctx->last_branch;
 817                                         ctx->pipe_index++;
 818                                         continue;
 819                                         break;
 820                                 case 0x4:       /* periodic synchronization point */
 821                                         next_pc = ctx->last_branch;
 822                                         break;
 823                                 default:        /* reserved */
 824                                         ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
 825                                         exit(-1);
 826                                         break;
 827                         }
 828
 829                         /* if we got here the branch was a normal PC change
 830                          * (or a periodic synchronization point, which means the same for that matter)
 831                          * if we didn't accquire a complete PC continue with the next cycle
 832                          */
 833                         if (!ctx->pc_ok)
 834                                 continue;
 835
 836                         /* indirect branch to the exception vector means an exception occured */
 837                         if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20))
 838                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 839                         {
 840                                 if ((ctx->last_branch & 0xff) == 0x10)
 841                                 {
 842                                         command_print(cmd_ctx, "data abort");
 843                                 }
 844                                 else
 845                                 {
 846                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
 847                                         ctx->current_pc = ctx->last_branch;
 848                                         ctx->pipe_index++;
 849                                         continue;
 850                                 }
 851                         }
 852                 }
 853
 854                 /* an instruction was executed (or not, depending on the condition flags)
 855                  * retrieve it from the image for displaying */
 856                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
 857                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
 858                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
 859                 {
 860                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
 861                         {
 862                                 /* can't continue tracing with no image available */
 863                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
 864                                 {
 865                                         return retval;
 866                                 }
 867                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
 868                                 {
 869                                         /* TODO: handle incomplete images */
 870                                 }
 871                         }
 872                 }
 873
 874                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 875                 {
 876                         u32 new_data_index = ctx->data_index;
 877                         u32 new_data_half = ctx->data_half;
 878
 879                         /* in case of a branch with data, the branch target address was consumed before
 880                          * we temporarily go back to the saved data index */
 881                         if (pipestat == STAT_BD)
 882                         {
 883                                 ctx->data_index = old_data_index;
 884                                 ctx->data_half = old_data_half;
 885                         }
 886
 887                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
 888                         {
 889                                 u8 packet;
 890                                 int shift = 0;
 891
 892                                 do {
 893                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 894                                                 return -1;
 895                                         ctx->last_ptr &= ~(0x7f << shift);
 896                                         ctx->last_ptr |= (packet & 0x7f) << shift;
 897                                         shift += 7;
 898                                 } while ((packet & 0x80) && (shift < 32));
 899
 900                                 if (shift >= 32)
 901                                         ctx->ptr_ok = 1;
 902
 903                                 if (ctx->ptr_ok)
 904                                 {
 905                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
 906                                 }
 907                         }
 908
 909                         if (ctx->tracemode & ETMV1_TRACE_DATA)
 910                         {
 911                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
 912                                 {
 913                                         int i;
 914                                         for (i = 0; i < 16; i++)
 915                                         {
 916                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 917                                                 {
 918                                                         u32 data;
 919                                                         if (etmv1_data(ctx, 4, &data) != 0)
 920                                                                 return -1;
 921                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 922                                                 }
 923                                         }
 924                                 }
 925                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 926                                 {
 927                                         u32 data;
 928                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 929                                                 return -1;
 930                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 931                                 }
 932                         }
 933
 934                         /* restore data index after consuming BD address and data */
 935                         if (pipestat == STAT_BD)
 936                         {
 937                                 ctx->data_index = new_data_index;
 938                                 ctx->data_half = new_data_half;
 939                         }
 940                 }
 941
 942                 /* adjust PC */
 943                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 944                 {
 945                         if (((instruction.type == ARM_B) ||
 946                                 (instruction.type == ARM_BL) ||
 947                                 (instruction.type == ARM_BLX)) &&
 948                                 (instruction.info.b_bl_bx_blx.target_address != -1))
 949                         {
 950                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
 951                         }
 952                         else
 953                         {
 954                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 955                         }
 956                 }
 957                 else if (pipestat == STAT_IN)
 958                 {
 959                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 960                 }
 961
 962                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
 963                 {
 964                         command_print(cmd_ctx, "%s%s",
 965                                 instruction.text, (pipestat == STAT_IN) ? " (not executed)" : "");
 966
 967                         ctx->current_pc = next_pc;
 968
 969                         /* packets for an instruction don't start on or before the preceding
 970                          * functional pipestat (i.e. other than WT or TD)
 971                          */
 972                         if (ctx->data_index <= ctx->pipe_index)
 973                         {
 974                                 ctx->data_index = ctx->pipe_index + 1;
 975                                 ctx->data_half = 0;
 976                         }
 977                 }
 978
 979                 ctx->pipe_index += 1;
 980         }
 981
 982         return ERROR_OK;
 983 }
 984
 985 int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 986 {
 987         target_t *target;
 988         armv4_5_common_t *armv4_5;
 989         arm7_9_common_t *arm7_9;
 990         etmv1_tracemode_t tracemode;
 991
 992         target = get_current_target(cmd_ctx);
 993
 994         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 995         {
 996                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 997                 return ERROR_OK;
 998         }
 999
1000         if (!arm7_9->etm_ctx)
1001         {
1002                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1003                 return ERROR_OK;
1004         }
1005
1006         tracemode = arm7_9->etm_ctx->tracemode;
1007
1008         if (argc == 3)
1009         {
1010                 if (strcmp(args[0], "none") == 0)
1011                 {
1012                         tracemode = ETMV1_TRACE_NONE;
1013                 }
1014                 else if (strcmp(args[0], "data") == 0)
1015                 {
1016                         tracemode = ETMV1_TRACE_DATA;
1017                 }
1018                 else if (strcmp(args[0], "address") == 0)
1019                 {
1020                         tracemode = ETMV1_TRACE_ADDR;
1021                 }
1022                 else if (strcmp(args[0], "all") == 0)
1023                 {
1024                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1025                 }
1026                 else
1027                 {
1028                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1029                         return ERROR_OK;
1030                 }
1031
1032                 switch (strtol(args[1], NULL, 0))
1033                 {
1034                         case 0:
1035                                 tracemode |= ETMV1_CONTEXTID_NONE;
1036                                 break;
1037                         case 8:
1038                                 tracemode |= ETMV1_CONTEXTID_8;
1039                                 break;
1040                         case 16:
1041                                 tracemode |= ETMV1_CONTEXTID_16;
1042                                 break;
1043                         case 32:
1044                                 tracemode |= ETMV1_CONTEXTID_32;
1045                                 break;
1046                         default:
1047                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1048                                 return ERROR_OK;
1049                 }
1050
1051                 if (strcmp(args[2], "enable") == 0)
1052                 {
1053                         tracemode |= ETMV1_CYCLE_ACCURATE;
1054                 }
1055                 else if (strcmp(args[2], "disable") == 0)
1056                 {
1057                         tracemode |= 0;
1058                 }
1059                 else
1060                 {
1061                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1062                         return ERROR_OK;
1063                 }
1064         }
1065         else if (argc != 0)
1066         {
1067                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <enable|disable cycle accurate>");
1068                 return ERROR_OK;
1069         }
1070
1071         command_print(cmd_ctx, "current tracemode configuration:");
1072
1073         switch (tracemode & ETMV1_TRACE_MASK)
1074         {
1075                 case ETMV1_TRACE_NONE:
1076                         command_print(cmd_ctx, "data tracing: none");
1077                         break;
1078                 case ETMV1_TRACE_DATA:
1079                         command_print(cmd_ctx, "data tracing: data only");
1080                         break;
1081                 case ETMV1_TRACE_ADDR:
1082                         command_print(cmd_ctx, "data tracing: address only");
1083                         break;
1084                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1085                         command_print(cmd_ctx, "data tracing: address and data");
1086                         break;
1087         }
1088
1089         switch (tracemode & ETMV1_CONTEXTID_MASK)
1090         {
1091                 case ETMV1_CONTEXTID_NONE:
1092                         command_print(cmd_ctx, "contextid tracing: none");
1093                         break;
1094                 case ETMV1_CONTEXTID_8:
1095                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1096                         break;
1097                 case ETMV1_CONTEXTID_16:
1098                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1099                         break;
1100                 case ETMV1_CONTEXTID_32:
1101                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1102                         break;
1103         }
1104
1105         if (tracemode & ETMV1_CYCLE_ACCURATE)
1106         {
1107                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1108         }
1109         else
1110         {
1111                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1112         }
1113
1114         /* only update ETM_CTRL register if tracemode changed */
1115         if (arm7_9->etm_ctx->tracemode != tracemode)
1116         {
1117                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1118
1119                 etm_get_reg(etm_ctrl_reg);
1120
1121                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1122                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1123                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1124
1125                 etm_store_reg(etm_ctrl_reg);
1126
1127                 arm7_9->etm_ctx->tracemode = tracemode;
1128
1129                 /* invalidate old trace data */
1130                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1131                 if (arm7_9->etm_ctx->trace_depth > 0)
1132                 {
1133                         free(arm7_9->etm_ctx->trace_data);
1134                 }
1135                 arm7_9->etm_ctx->trace_depth = 0;
1136         }
1137
1138         return ERROR_OK;
1139 }
1140
1141 int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1142 {
1143         target_t *target;
1144         armv4_5_common_t *armv4_5;
1145         arm7_9_common_t *arm7_9;
1146         etm_portmode_t portmode = 0x0;
1147         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1148         int i;
1149
1150         if (argc != 5)
1151         {
1152                 ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1153                 exit(-1);
1154         }
1155
1156         target = get_target_by_num(strtoul(args[0], NULL, 0));
1157
1158         if (!target)
1159         {
1160                 ERROR("target number '%s' not defined", args[0]);
1161                 exit(-1);
1162         }
1163
1164         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1165         {
1166                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1167                 return ERROR_OK;
1168         }
1169
1170         switch (strtoul(args[1], NULL, 0))
1171         {
1172                 case 4:
1173                         portmode |= ETM_PORT_4BIT;
1174                         break;
1175                 case 8:
1176                         portmode |= ETM_PORT_8BIT;
1177                         break;
1178                 case 16:
1179                         portmode |= ETM_PORT_16BIT;
1180                         break;
1181                 default:
1182                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1183                         return ERROR_OK;
1184         }
1185
1186         if (strcmp("normal", args[2]) == 0)
1187         {
1188                 portmode |= ETM_PORT_NORMAL;
1189         }
1190         else if (strcmp("multiplexed", args[2]) == 0)
1191         {
1192                 portmode |= ETM_PORT_MUXED;
1193         }
1194         else if (strcmp("demultiplexed", args[2]) == 0)
1195         {
1196                 portmode |= ETM_PORT_DEMUXED;
1197         }
1198         else
1199         {
1200                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1201                 return ERROR_OK;
1202         }
1203
1204         if (strcmp("half", args[3]) == 0)
1205         {
1206                 portmode |= ETM_PORT_HALF_CLOCK;
1207         }
1208         else if (strcmp("full", args[3]) == 0)
1209         {
1210                 portmode |= ETM_PORT_FULL_CLOCK;
1211         }
1212         else
1213         {
1214                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1215                 return ERROR_OK;
1216         }
1217
1218         for (i=0; etm_capture_drivers[i]; i++)
1219         {
1220                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1221                 {
1222                         if (etm_capture_drivers[i]->register_commands(cmd_ctx) != ERROR_OK)
1223                         {
1224                                 free(etm_ctx);
1225                                 exit(-1);
1226                         }
1227
1228                         etm_ctx->capture_driver = etm_capture_drivers[i];
1229
1230                         break;
1231                 }
1232         }
1233
1234         etm_ctx->target = target;
1235         etm_ctx->trace_data = NULL;
1236         etm_ctx->trace_depth = 0;
1237         etm_ctx->portmode = portmode;
1238         etm_ctx->tracemode = 0x0;
1239         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1240         etm_ctx->image = NULL;
1241         etm_ctx->pipe_index = 0;
1242         etm_ctx->data_index = 0;
1243         etm_ctx->current_pc = 0x0;
1244         etm_ctx->pc_ok = 0;
1245         etm_ctx->last_branch = 0x0;
1246         etm_ctx->last_branch_reason = 0x0;
1247         etm_ctx->last_ptr = 0x0;
1248         etm_ctx->ptr_ok = 0x0;
1249         etm_ctx->context_id = 0x0;
1250
1251         arm7_9->etm_ctx = etm_ctx;
1252
1253         etm_register_user_commands(cmd_ctx);
1254
1255         return ERROR_OK;
1256 }
1257
1258 int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1259 {
1260         target_t *target;
1261         armv4_5_common_t *armv4_5;
1262         arm7_9_common_t *arm7_9;
1263         trace_status_t trace_status;
1264
1265         target = get_current_target(cmd_ctx);
1266
1267         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1268         {
1269                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1270                 return ERROR_OK;
1271         }
1272
1273         if (!arm7_9->etm_ctx)
1274         {
1275                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1276                 return ERROR_OK;
1277         }
1278
1279         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1280
1281         if (trace_status == TRACE_IDLE)
1282         {
1283                 command_print(cmd_ctx, "tracing is idle");
1284         }
1285         else
1286         {
1287                 static char *completed = " completed";
1288                 static char *running = " is running";
1289                 static char *overflowed = ", trace overflowed";
1290                 static char *triggered = ", trace triggered";
1291
1292                 command_print(cmd_ctx, "trace collection%s%s%s",
1293                         (trace_status & TRACE_RUNNING) ? running : completed,
1294                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1295                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1296
1297                 if (arm7_9->etm_ctx->trace_depth > 0)
1298                 {
1299                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1300                 }
1301         }
1302
1303         return ERROR_OK;
1304 }
1305
1306 int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1307 {
1308         target_t *target;
1309         armv4_5_common_t *armv4_5;
1310         arm7_9_common_t *arm7_9;
1311         etm_context_t *etm_ctx;
1312         int i;
1313
1314         if (argc < 1)
1315         {
1316                 command_print(cmd_ctx, "usage: etm image <file> ['bin'|'ihex'|'elf'] [base address]");
1317                 return ERROR_OK;
1318         }
1319
1320         target = get_current_target(cmd_ctx);
1321
1322         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1323         {
1324                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1325                 return ERROR_OK;
1326         }
1327
1328         if (!(etm_ctx = arm7_9->etm_ctx))
1329         {
1330                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1331                 return ERROR_OK;
1332         }
1333
1334         if (etm_ctx->image)
1335         {
1336                 image_close(etm_ctx->image);
1337                 free(etm_ctx->image);
1338                 command_print(cmd_ctx, "previously loaded image found and closed");
1339         }
1340
1341         etm_ctx->image = malloc(sizeof(image_t));
1342         etm_ctx->image->base_address_set = 0;
1343         etm_ctx->image->start_address_set = 0;
1344
1345         for (i = 1; i < argc; i++)
1346         {
1347                 /* optional argument could be image type */
1348                 if (identify_image_type(&etm_ctx->image->type, args[i], args[0]) == ERROR_IMAGE_TYPE_UNKNOWN)
1349                 {
1350                         /* if it wasn't a valid image type, treat it as the base address */
1351                         etm_ctx->image->base_address_set = 1;
1352                         etm_ctx->image->base_address = strtoul(args[i], NULL, 0);
1353                 }
1354         }
1355
1356         if (image_open(etm_ctx->image, args[0], FILEIO_READ) != ERROR_OK)
1357         {
1358                 command_print(cmd_ctx, "image opening error: %s", etm_ctx->image->error_str);
1359                 free(etm_ctx->image);
1360                 etm_ctx->image = NULL;
1361                 return ERROR_OK;
1362         }
1363
1364         return ERROR_OK;
1365 }
1366
1367 int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1368 {
1369         fileio_t file;
1370         target_t *target;
1371         armv4_5_common_t *armv4_5;
1372         arm7_9_common_t *arm7_9;
1373         etm_context_t *etm_ctx;
1374         int i;
1375
1376         if (argc != 1)
1377         {
1378                 command_print(cmd_ctx, "usage: etm dump <file>");
1379                 return ERROR_OK;
1380         }
1381
1382         target = get_current_target(cmd_ctx);
1383
1384         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1385         {
1386                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1387                 return ERROR_OK;
1388         }
1389
1390         if (!(etm_ctx = arm7_9->etm_ctx))
1391         {
1392                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1393                 return ERROR_OK;
1394         }
1395
1396         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1397         {
1398                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1399                 return ERROR_OK;
1400         }
1401
1402         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1403         {
1404                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1405                 command_print(cmd_ctx, "trace capture not completed");
1406                 return ERROR_OK;
1407         }
1408
1409         /* read the trace data if it wasn't read already */
1410         if (etm_ctx->trace_depth == 0)
1411                 etm_ctx->capture_driver->read_trace(etm_ctx);
1412
1413         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1414         {
1415                 command_print(cmd_ctx, "file open error: %s", file.error_str);
1416                 return ERROR_OK;
1417         }
1418
1419         fileio_write_u32(&file, etm_ctx->capture_status);
1420         fileio_write_u32(&file, etm_ctx->portmode);
1421         fileio_write_u32(&file, etm_ctx->tracemode);
1422         fileio_write_u32(&file, etm_ctx->trace_depth);
1423
1424         for (i = 0; i < etm_ctx->trace_depth; i++)
1425         {
1426                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1427                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1428                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1429         }
1430
1431         fileio_close(&file);
1432
1433         return ERROR_OK;
1434 }
1435
1436 int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1437 {
1438         fileio_t file;
1439         target_t *target;
1440         armv4_5_common_t *armv4_5;
1441         arm7_9_common_t *arm7_9;
1442         etm_context_t *etm_ctx;
1443         int i;
1444
1445         if (argc != 1)
1446         {
1447                 command_print(cmd_ctx, "usage: etm load <file>");
1448                 return ERROR_OK;
1449         }
1450
1451         target = get_current_target(cmd_ctx);
1452
1453         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1454         {
1455                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1456                 return ERROR_OK;
1457         }
1458
1459         if (!(etm_ctx = arm7_9->etm_ctx))
1460         {
1461                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1462                 return ERROR_OK;
1463         }
1464
1465         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1466         {
1467                 command_print(cmd_ctx, "trace capture running, stop first");
1468                 return ERROR_OK;
1469         }
1470
1471         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1472         {
1473                 command_print(cmd_ctx, "file open error: %s", file.error_str);
1474                 return ERROR_OK;
1475         }
1476
1477         if (file.size % 4)
1478         {
1479                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1480                 return ERROR_OK;
1481         }
1482
1483         if (etm_ctx->trace_depth > 0)
1484         {
1485                 free(etm_ctx->trace_data);
1486         }
1487
1488         fileio_read_u32(&file, &etm_ctx->capture_status);
1489         fileio_read_u32(&file, &etm_ctx->portmode);
1490         fileio_read_u32(&file, &etm_ctx->tracemode);
1491         fileio_read_u32(&file, &etm_ctx->trace_depth);
1492
1493         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1494
1495         for (i = 0; i < etm_ctx->trace_depth; i++)
1496         {
1497                 fileio_read_u32(&file, &etm_ctx->trace_data[i].pipestat);
1498                 fileio_read_u32(&file, &etm_ctx->trace_data[i].packet);
1499                 fileio_read_u32(&file, &etm_ctx->trace_data[i].flags);
1500         }
1501
1502         fileio_close(&file);
1503
1504         return ERROR_OK;
1505 }
1506
1507 int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1508 {
1509         target_t *target;
1510         armv4_5_common_t *armv4_5;
1511         arm7_9_common_t *arm7_9;
1512         etm_context_t *etm_ctx;
1513         reg_t *etm_ctrl_reg;
1514
1515         target = get_current_target(cmd_ctx);
1516
1517         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1518         {
1519                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1520                 return ERROR_OK;
1521         }
1522
1523         if (!(etm_ctx = arm7_9->etm_ctx))
1524         {
1525                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1526                 return ERROR_OK;
1527         }
1528
1529         /* invalidate old tracing data */
1530         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1531         if (arm7_9->etm_ctx->trace_depth > 0)
1532         {
1533                 free(arm7_9->etm_ctx->trace_data);
1534         }
1535         arm7_9->etm_ctx->trace_depth = 0;
1536
1537         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1538         etm_get_reg(etm_ctrl_reg);
1539
1540         /* Clear programming bit (10), set port selection bit (11) */
1541         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1542
1543         etm_store_reg(etm_ctrl_reg);
1544         jtag_execute_queue();
1545
1546         etm_ctx->capture_driver->start_capture(etm_ctx);
1547
1548         return ERROR_OK;
1549 }
1550
1551 int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1552 {
1553         target_t *target;
1554         armv4_5_common_t *armv4_5;
1555         arm7_9_common_t *arm7_9;
1556         etm_context_t *etm_ctx;
1557         reg_t *etm_ctrl_reg;
1558
1559         target = get_current_target(cmd_ctx);
1560
1561         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1562         {
1563                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1564                 return ERROR_OK;
1565         }
1566
1567         if (!(etm_ctx = arm7_9->etm_ctx))
1568         {
1569                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1570                 return ERROR_OK;
1571         }
1572
1573         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1574         etm_get_reg(etm_ctrl_reg);
1575
1576         /* Set programming bit (10), clear port selection bit (11) */
1577         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1578
1579         etm_store_reg(etm_ctrl_reg);
1580         jtag_execute_queue();
1581
1582         etm_ctx->capture_driver->stop_capture(etm_ctx);
1583
1584         return ERROR_OK;
1585 }
1586
1587 int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1588 {
1589         target_t *target;
1590         armv4_5_common_t *armv4_5;
1591         arm7_9_common_t *arm7_9;
1592         etm_context_t *etm_ctx;
1593
1594         target = get_current_target(cmd_ctx);
1595
1596         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1597         {
1598                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1599                 return ERROR_OK;
1600         }
1601
1602         if (!(etm_ctx = arm7_9->etm_ctx))
1603         {
1604                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1605                 return ERROR_OK;
1606         }
1607
1608         etmv1_analyze_trace(etm_ctx, cmd_ctx);
1609
1610         return ERROR_OK;
1611 }
1612
1613 int etm_register_commands(struct command_context_s *cmd_ctx)
1614 {
1615         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1616
1617         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, NULL);
1618
1619         return ERROR_OK;
1620 }
1621
1622 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1623 {
1624         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1625                 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <enable|disable cycle accurate>");
1626
1627         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1628                 COMMAND_EXEC, "display current target's ETM status");
1629         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1630                 COMMAND_EXEC, "start ETM trace collection");
1631         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1632                 COMMAND_EXEC, "stop ETM trace collection");
1633
1634         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1635                 COMMAND_EXEC, "anaylze collected ETM trace");
1636
1637         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1638                 COMMAND_EXEC, "load image from <file> [base address]");
1639
1640         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1641                 COMMAND_EXEC, "dump captured trace data <file>");
1642         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1643                 COMMAND_EXEC, "load trace data for analysis <file>");
1644
1645         return ERROR_OK;
1646 }