1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
32 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
34 * ETM modules collect instruction and/or data trace information, compress
35 * it, and transfer it to a debugging host through either a (buffered) trace
36 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
38 * There are several generations of these modules. Original versions have
39 * JTAG access through a dedicated scan chain. Recent versions have added
40 * access via coprocessor instructions, memory addressing, and the ARM Debug
41 * Interface v5 (ADIv5); and phased out direct JTAG access.
43 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
44 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
45 * implying non-JTAG connectivity options.
47 * Relevant documentation includes:
48 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
49 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
50 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
53 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
63 uint8_t size; /* low-N of 32 bits */
64 uint8_t mode; /* RO, WO, RW */
65 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
74 static const struct etm_reg_info reg[] = {
75 /* ETM Trace Registers */
76 { ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
77 { ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
78 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
79 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_ASIC_CTRL", },
80 { ETM_STATUS, 3, RO, 0x11, "ETM_STATUS", },
81 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_SYS_CONFIG", },
83 /* TraceEnable configuration */
84 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
85 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
86 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
87 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
89 /* FIFOFULL configuration */
90 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
91 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
93 /* ViewData configuration (data trace) */
94 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
95 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
96 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
97 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
99 /* Address comparator register pairs */
100 #define ADDR_COMPARATOR(i) \
101 { ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
102 "ETM_ADDR_COMPARATOR_VALUE" #i, }, \
103 { ETM_ADDR_ACCESS_TYPE + (i), 7, WO, 0x10, \
104 "ETM_ADDR_ACCESS_TYPE" #i, }
122 #undef ADDR_COMPARATOR
124 /* Data Value Comparators (NOTE: odd addresses are reserved) */
125 #define DATA_COMPARATOR(i) \
126 { ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
127 "ETM_DATA_COMPARATOR_VALUE" #i, }, \
128 { ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
129 "ETM_DATA_COMPARATOR_MASK" #i, }
138 #undef DATA_COMPARATOR
142 { ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
143 "ETM_COUNTER_RELOAD_VALUE" #i, }, \
144 { ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
145 "ETM_COUNTER_ENABLE" #i, }, \
146 { ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
147 "ETM_COUNTER_RELOAD_EVENT" #i, }, \
148 { ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
149 "ETM_COUNTER_VALUE" #i, }
158 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
159 "ETM_SEQUENCER_EVENT" #i, }
168 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_SEQUENCER_STATE", },
171 { ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
172 "ETM_EXTERNAL_OUTPUT" #i, }
181 /* registers from 0x6c..0x7f were added after ETMv1.3 */
183 /* Context ID Comparators */
184 { 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
185 { 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
186 { 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
187 { 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
189 { 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
190 { 0x79, 32, RO, 0x20, "ETM_ID", },
194 static int etm_reg_arch_type = -1;
196 static int etm_get_reg(reg_t *reg);
197 static int etm_read_reg_w_check(reg_t *reg,
198 uint8_t* check_value, uint8_t* check_mask);
199 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
200 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
201 static int etm_write_reg(reg_t *reg, uint32_t value);
203 static command_t *etm_cmd;
206 /* Look up register by ID ... most ETM instances only
207 * support a subset of the possible registers.
209 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
211 reg_cache_t *cache = etm_ctx->reg_cache;
214 for (i = 0; i < cache->num_regs; i++) {
215 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
217 if (reg->reg_info->addr == id)
218 return &cache->reg_list[i];
221 /* caller asking for nonexistent register is a bug! */
222 /* REVISIT say which of the N targets was involved */
223 LOG_ERROR("ETM: register 0x%02x not available", id);
227 reg_cache_t *etm_build_reg_cache(target_t *target,
228 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
230 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
231 reg_t *reg_list = NULL;
232 etm_reg_t *arch_info = NULL;
233 int num_regs = ARRAY_SIZE(reg);
236 /* register a register arch-type for etm registers only once */
237 if (etm_reg_arch_type == -1)
238 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
240 /* the actual registers are kept in two arrays */
241 reg_list = calloc(num_regs, sizeof(reg_t));
242 arch_info = calloc(num_regs, sizeof(etm_reg_t));
244 /* fill in values for the reg cache */
245 reg_cache->name = "etm registers";
246 reg_cache->next = NULL;
247 reg_cache->reg_list = reg_list;
248 reg_cache->num_regs = num_regs;
250 /* set up registers */
251 for (i = 0; i < num_regs; i++)
253 const struct etm_reg_info *r = reg + i;
255 reg_list[i].name = r->name;
256 reg_list[i].size = r->size;
257 reg_list[i].value = &arch_info[i].value;
258 reg_list[i].arch_info = &arch_info[i];
259 reg_list[i].arch_type = etm_reg_arch_type;
261 arch_info[i].reg_info = r;
262 arch_info[i].jtag_info = jtag_info;
265 /* the ETM might have an ETB connected */
266 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
268 etb_t *etb = etm_ctx->capture_driver_priv;
272 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
278 reg_cache->next = etb_build_reg_cache(etb);
280 etb->reg_cache = reg_cache->next;
287 static int etm_read_reg(reg_t *reg)
289 return etm_read_reg_w_check(reg, NULL, NULL);
292 static int etm_store_reg(reg_t *reg)
294 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
297 int etm_setup(target_t *target)
300 uint32_t etm_ctrl_value;
301 armv4_5_common_t *armv4_5 = target->arch_info;
302 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
303 etm_context_t *etm_ctx = arm7_9->etm_ctx;
306 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
310 /* initialize some ETM control register settings */
311 etm_get_reg(etm_ctrl_reg);
312 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
314 /* clear the ETM powerdown bit (0) */
315 etm_ctrl_value &= ~0x1;
317 /* configure port width (6:4), mode (17:16) and clocking (13) */
318 etm_ctrl_value = (etm_ctrl_value &
319 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
322 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
323 etm_store_reg(etm_ctrl_reg);
325 if ((retval = jtag_execute_queue()) != ERROR_OK)
328 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
330 LOG_ERROR("ETM capture driver initialization failed");
336 static int etm_get_reg(reg_t *reg)
340 if ((retval = etm_read_reg(reg)) != ERROR_OK)
342 LOG_ERROR("BUG: error scheduling etm register read");
346 if ((retval = jtag_execute_queue()) != ERROR_OK)
348 LOG_ERROR("register read failed");
355 static int etm_read_reg_w_check(reg_t *reg,
356 uint8_t* check_value, uint8_t* check_mask)
358 etm_reg_t *etm_reg = reg->arch_info;
359 const struct etm_reg_info *r = etm_reg->reg_info;
360 uint8_t reg_addr = r->addr & 0x7f;
361 scan_field_t fields[3];
363 if (etm_reg->reg_info->mode == WO) {
364 LOG_ERROR("BUG: can't read write-only register %s", r->name);
365 return ERROR_INVALID_ARGUMENTS;
368 LOG_DEBUG("%s (%u)", r->name, reg_addr);
370 jtag_set_end_state(TAP_IDLE);
371 arm_jtag_scann(etm_reg->jtag_info, 0x6);
372 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
374 fields[0].tap = etm_reg->jtag_info->tap;
375 fields[0].num_bits = 32;
376 fields[0].out_value = reg->value;
377 fields[0].in_value = NULL;
378 fields[0].check_value = NULL;
379 fields[0].check_mask = NULL;
381 fields[1].tap = etm_reg->jtag_info->tap;
382 fields[1].num_bits = 7;
383 fields[1].out_value = malloc(1);
384 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
385 fields[1].in_value = NULL;
386 fields[1].check_value = NULL;
387 fields[1].check_mask = NULL;
389 fields[2].tap = etm_reg->jtag_info->tap;
390 fields[2].num_bits = 1;
391 fields[2].out_value = malloc(1);
392 buf_set_u32(fields[2].out_value, 0, 1, 0);
393 fields[2].in_value = NULL;
394 fields[2].check_value = NULL;
395 fields[2].check_mask = NULL;
397 jtag_add_dr_scan(3, fields, jtag_get_end_state());
399 fields[0].in_value = reg->value;
400 fields[0].check_value = check_value;
401 fields[0].check_mask = check_mask;
403 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
405 free(fields[1].out_value);
406 free(fields[2].out_value);
411 static int etm_set_reg(reg_t *reg, uint32_t value)
415 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
417 LOG_ERROR("BUG: error scheduling etm register write");
421 buf_set_u32(reg->value, 0, reg->size, value);
428 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
432 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
434 if ((retval = jtag_execute_queue()) != ERROR_OK)
436 LOG_ERROR("register write failed");
442 static int etm_write_reg(reg_t *reg, uint32_t value)
444 etm_reg_t *etm_reg = reg->arch_info;
445 const struct etm_reg_info *r = etm_reg->reg_info;
446 uint8_t reg_addr = r->addr & 0x7f;
447 scan_field_t fields[3];
449 if (etm_reg->reg_info->mode == RO) {
450 LOG_ERROR("BUG: can't write read--only register %s", r->name);
451 return ERROR_INVALID_ARGUMENTS;
454 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
456 jtag_set_end_state(TAP_IDLE);
457 arm_jtag_scann(etm_reg->jtag_info, 0x6);
458 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
460 fields[0].tap = etm_reg->jtag_info->tap;
461 fields[0].num_bits = 32;
463 fields[0].out_value = tmp1;
464 buf_set_u32(fields[0].out_value, 0, 32, value);
465 fields[0].in_value = NULL;
467 fields[1].tap = etm_reg->jtag_info->tap;
468 fields[1].num_bits = 7;
470 fields[1].out_value = &tmp2;
471 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
472 fields[1].in_value = NULL;
474 fields[2].tap = etm_reg->jtag_info->tap;
475 fields[2].num_bits = 1;
477 fields[2].out_value = &tmp3;
478 buf_set_u32(fields[2].out_value, 0, 1, 1);
479 fields[2].in_value = NULL;
481 jtag_add_dr_scan(3, fields, jtag_get_end_state());
487 /* ETM trace analysis functionality
490 extern etm_capture_driver_t etm_dummy_capture_driver;
491 #if BUILD_OOCD_TRACE == 1
492 extern etm_capture_driver_t oocd_trace_capture_driver;
495 static etm_capture_driver_t *etm_capture_drivers[] =
498 &etm_dummy_capture_driver,
499 #if BUILD_OOCD_TRACE == 1
500 &oocd_trace_capture_driver,
505 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
514 return ERROR_TRACE_IMAGE_UNAVAILABLE;
516 /* search for the section the current instruction belongs to */
517 for (i = 0; i < ctx->image->num_sections; i++)
519 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
520 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
529 /* current instruction couldn't be found in the image */
530 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
533 if (ctx->core_state == ARMV4_5_STATE_ARM)
536 if ((retval = image_read_section(ctx->image, section,
537 ctx->current_pc - ctx->image->sections[section].base_address,
538 4, buf, &size_read)) != ERROR_OK)
540 LOG_ERROR("error while reading instruction: %i", retval);
541 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
543 opcode = target_buffer_get_u32(ctx->target, buf);
544 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
546 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
549 if ((retval = image_read_section(ctx->image, section,
550 ctx->current_pc - ctx->image->sections[section].base_address,
551 2, buf, &size_read)) != ERROR_OK)
553 LOG_ERROR("error while reading instruction: %i", retval);
554 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
556 opcode = target_buffer_get_u16(ctx->target, buf);
557 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
559 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
561 LOG_ERROR("BUG: tracing of jazelle code not supported");
566 LOG_ERROR("BUG: unknown core state encountered");
573 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
575 while (ctx->data_index < ctx->trace_depth)
577 /* if the caller specified an address packet offset, skip until the
578 * we reach the n-th cycle marked with tracesync */
581 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
592 /* no tracedata output during a TD cycle
593 * or in a trigger cycle */
594 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
595 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
602 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
604 if (ctx->data_half == 0)
606 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
611 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
616 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
618 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
623 /* on a 4-bit port, a packet will be output during two consecutive cycles */
624 if (ctx->data_index > (ctx->trace_depth - 2))
627 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
628 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
629 ctx->data_index += 2;
638 static int etmv1_branch_address(etm_context_t *ctx)
646 /* quit analysis if less than two cycles are left in the trace
647 * because we can't extract the APO */
648 if (ctx->data_index > (ctx->trace_depth - 2))
651 /* a BE could be output during an APO cycle, skip the current
652 * and continue with the new one */
653 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
655 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
658 /* address packet offset encoded in the next two cycles' pipestat bits */
659 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
660 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
662 /* count number of tracesync cycles between current pipe_index and data_index
663 * i.e. the number of tracesyncs that data_index already passed by
664 * to subtract them from the APO */
665 for (i = ctx->pipe_index; i < ctx->data_index; i++)
667 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
671 /* extract up to four 7-bit packets */
673 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
675 ctx->last_branch &= ~(0x7f << shift);
676 ctx->last_branch |= (packet & 0x7f) << shift;
678 } while ((packet & 0x80) && (shift < 28));
680 /* one last packet holding 4 bits of the address, plus the branch reason code */
681 if ((shift == 28) && (packet & 0x80))
683 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
685 ctx->last_branch &= 0x0fffffff;
686 ctx->last_branch |= (packet & 0x0f) << 28;
687 ctx->last_branch_reason = (packet & 0x70) >> 4;
692 ctx->last_branch_reason = 0;
700 /* if a full address was output, we might have branched into Jazelle state */
701 if ((shift == 32) && (packet & 0x80))
703 ctx->core_state = ARMV4_5_STATE_JAZELLE;
707 /* if we didn't branch into Jazelle state, the current processor state is
708 * encoded in bit 0 of the branch target address */
709 if (ctx->last_branch & 0x1)
711 ctx->core_state = ARMV4_5_STATE_THUMB;
712 ctx->last_branch &= ~0x1;
716 ctx->core_state = ARMV4_5_STATE_ARM;
717 ctx->last_branch &= ~0x3;
724 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
730 for (j = 0; j < size; j++)
732 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
738 LOG_ERROR("TODO: add support for 64-bit values");
742 *data = target_buffer_get_u32(ctx->target, buf);
744 *data = target_buffer_get_u16(ctx->target, buf);
753 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
756 arm_instruction_t instruction;
758 /* read the trace data if it wasn't read already */
759 if (ctx->trace_depth == 0)
760 ctx->capture_driver->read_trace(ctx);
762 /* start at the beginning of the captured trace */
767 /* neither the PC nor the data pointer are valid */
771 while (ctx->pipe_index < ctx->trace_depth)
773 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
774 uint32_t next_pc = ctx->current_pc;
775 uint32_t old_data_index = ctx->data_index;
776 uint32_t old_data_half = ctx->data_half;
777 uint32_t old_index = ctx->pipe_index;
778 uint32_t last_instruction = ctx->last_instruction;
780 int current_pc_ok = ctx->pc_ok;
782 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
784 command_print(cmd_ctx, "--- trigger ---");
787 /* instructions execute in IE/D or BE/D cycles */
788 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
789 ctx->last_instruction = ctx->pipe_index;
791 /* if we don't have a valid pc skip until we reach an indirect branch */
792 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
798 /* any indirect branch could have interrupted instruction flow
799 * - the branch reason code could indicate a trace discontinuity
800 * - a branch to the exception vectors indicates an exception
802 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
804 /* backup current data index, to be able to consume the branch address
805 * before examining data address and values
807 old_data_index = ctx->data_index;
808 old_data_half = ctx->data_half;
810 ctx->last_instruction = ctx->pipe_index;
812 if ((retval = etmv1_branch_address(ctx)) != 0)
814 /* negative return value from etmv1_branch_address means we ran out of packets,
815 * quit analysing the trace */
819 /* a positive return values means the current branch was abandoned,
820 * and a new branch was encountered in cycle ctx->pipe_index + retval;
822 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
823 ctx->pipe_index += retval;
827 /* skip over APO cycles */
828 ctx->pipe_index += 2;
830 switch (ctx->last_branch_reason)
832 case 0x0: /* normal PC change */
833 next_pc = ctx->last_branch;
835 case 0x1: /* tracing enabled */
836 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
837 ctx->current_pc = ctx->last_branch;
841 case 0x2: /* trace restarted after FIFO overflow */
842 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
843 ctx->current_pc = ctx->last_branch;
847 case 0x3: /* exit from debug state */
848 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
849 ctx->current_pc = ctx->last_branch;
853 case 0x4: /* periodic synchronization point */
854 next_pc = ctx->last_branch;
855 /* if we had no valid PC prior to this synchronization point,
856 * we have to move on with the next trace cycle
860 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
861 ctx->current_pc = next_pc;
866 default: /* reserved */
867 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
872 /* if we got here the branch was a normal PC change
873 * (or a periodic synchronization point, which means the same for that matter)
874 * if we didn't accquire a complete PC continue with the next cycle
879 /* indirect branch to the exception vector means an exception occured */
880 if ((ctx->last_branch <= 0x20)
881 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
883 if ((ctx->last_branch & 0xff) == 0x10)
885 command_print(cmd_ctx, "data abort");
889 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
890 ctx->current_pc = ctx->last_branch;
897 /* an instruction was executed (or not, depending on the condition flags)
898 * retrieve it from the image for displaying */
899 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
900 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
901 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
903 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
905 /* can't continue tracing with no image available */
906 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
910 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
912 /* TODO: handle incomplete images
913 * for now we just quit the analsysis*/
918 cycles = old_index - last_instruction;
921 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
923 uint32_t new_data_index = ctx->data_index;
924 uint32_t new_data_half = ctx->data_half;
926 /* in case of a branch with data, the branch target address was consumed before
927 * we temporarily go back to the saved data index */
928 if (pipestat == STAT_BD)
930 ctx->data_index = old_data_index;
931 ctx->data_half = old_data_half;
934 if (ctx->tracemode & ETMV1_TRACE_ADDR)
940 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
941 return ERROR_ETM_ANALYSIS_FAILED;
942 ctx->last_ptr &= ~(0x7f << shift);
943 ctx->last_ptr |= (packet & 0x7f) << shift;
945 } while ((packet & 0x80) && (shift < 32));
952 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
956 if (ctx->tracemode & ETMV1_TRACE_DATA)
958 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
961 for (i = 0; i < 16; i++)
963 if (instruction.info.load_store_multiple.register_list & (1 << i))
966 if (etmv1_data(ctx, 4, &data) != 0)
967 return ERROR_ETM_ANALYSIS_FAILED;
968 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
972 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
975 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
976 return ERROR_ETM_ANALYSIS_FAILED;
977 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
981 /* restore data index after consuming BD address and data */
982 if (pipestat == STAT_BD)
984 ctx->data_index = new_data_index;
985 ctx->data_half = new_data_half;
990 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
992 if (((instruction.type == ARM_B) ||
993 (instruction.type == ARM_BL) ||
994 (instruction.type == ARM_BLX)) &&
995 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
997 next_pc = instruction.info.b_bl_bx_blx.target_address;
1001 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1004 else if (pipestat == STAT_IN)
1006 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1009 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1011 char cycles_text[32] = "";
1013 /* if the trace was captured with cycle accurate tracing enabled,
1014 * output the number of cycles since the last executed instruction
1016 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1018 snprintf(cycles_text, 32, " (%i %s)",
1020 (cycles == 1) ? "cycle" : "cycles");
1023 command_print(cmd_ctx, "%s%s%s",
1025 (pipestat == STAT_IN) ? " (not executed)" : "",
1028 ctx->current_pc = next_pc;
1030 /* packets for an instruction don't start on or before the preceding
1031 * functional pipestat (i.e. other than WT or TD)
1033 if (ctx->data_index <= ctx->pipe_index)
1035 ctx->data_index = ctx->pipe_index + 1;
1040 ctx->pipe_index += 1;
1046 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1049 armv4_5_common_t *armv4_5;
1050 arm7_9_common_t *arm7_9;
1051 etmv1_tracemode_t tracemode;
1053 target = get_current_target(cmd_ctx);
1055 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1057 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1061 if (!arm7_9->etm_ctx)
1063 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1067 tracemode = arm7_9->etm_ctx->tracemode;
1071 if (strcmp(args[0], "none") == 0)
1073 tracemode = ETMV1_TRACE_NONE;
1075 else if (strcmp(args[0], "data") == 0)
1077 tracemode = ETMV1_TRACE_DATA;
1079 else if (strcmp(args[0], "address") == 0)
1081 tracemode = ETMV1_TRACE_ADDR;
1083 else if (strcmp(args[0], "all") == 0)
1085 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1089 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1093 switch (strtol(args[1], NULL, 0))
1096 tracemode |= ETMV1_CONTEXTID_NONE;
1099 tracemode |= ETMV1_CONTEXTID_8;
1102 tracemode |= ETMV1_CONTEXTID_16;
1105 tracemode |= ETMV1_CONTEXTID_32;
1108 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1112 if (strcmp(args[2], "enable") == 0)
1114 tracemode |= ETMV1_CYCLE_ACCURATE;
1116 else if (strcmp(args[2], "disable") == 0)
1122 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1126 if (strcmp(args[3], "enable") == 0)
1128 tracemode |= ETMV1_BRANCH_OUTPUT;
1130 else if (strcmp(args[3], "disable") == 0)
1136 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1142 command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1146 command_print(cmd_ctx, "current tracemode configuration:");
1148 switch (tracemode & ETMV1_TRACE_MASK)
1150 case ETMV1_TRACE_NONE:
1151 command_print(cmd_ctx, "data tracing: none");
1153 case ETMV1_TRACE_DATA:
1154 command_print(cmd_ctx, "data tracing: data only");
1156 case ETMV1_TRACE_ADDR:
1157 command_print(cmd_ctx, "data tracing: address only");
1159 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1160 command_print(cmd_ctx, "data tracing: address and data");
1164 switch (tracemode & ETMV1_CONTEXTID_MASK)
1166 case ETMV1_CONTEXTID_NONE:
1167 command_print(cmd_ctx, "contextid tracing: none");
1169 case ETMV1_CONTEXTID_8:
1170 command_print(cmd_ctx, "contextid tracing: 8 bit");
1172 case ETMV1_CONTEXTID_16:
1173 command_print(cmd_ctx, "contextid tracing: 16 bit");
1175 case ETMV1_CONTEXTID_32:
1176 command_print(cmd_ctx, "contextid tracing: 32 bit");
1180 if (tracemode & ETMV1_CYCLE_ACCURATE)
1182 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1186 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1189 if (tracemode & ETMV1_BRANCH_OUTPUT)
1191 command_print(cmd_ctx, "full branch address output enabled");
1195 command_print(cmd_ctx, "full branch address output disabled");
1198 /* only update ETM_CTRL register if tracemode changed */
1199 if (arm7_9->etm_ctx->tracemode != tracemode)
1201 reg_t *etm_ctrl_reg;
1203 etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
1207 etm_get_reg(etm_ctrl_reg);
1209 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1210 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1211 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1212 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1213 etm_store_reg(etm_ctrl_reg);
1215 arm7_9->etm_ctx->tracemode = tracemode;
1217 /* invalidate old trace data */
1218 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1219 if (arm7_9->etm_ctx->trace_depth > 0)
1221 free(arm7_9->etm_ctx->trace_data);
1222 arm7_9->etm_ctx->trace_data = NULL;
1224 arm7_9->etm_ctx->trace_depth = 0;
1230 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1233 armv4_5_common_t *armv4_5;
1234 arm7_9_common_t *arm7_9;
1235 etm_portmode_t portmode = 0x0;
1236 etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1242 return ERROR_COMMAND_SYNTAX_ERROR;
1245 target = get_target(args[0]);
1248 LOG_ERROR("target '%s' not defined", args[0]);
1253 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1255 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1260 switch (strtoul(args[1], NULL, 0))
1263 portmode |= ETM_PORT_4BIT;
1266 portmode |= ETM_PORT_8BIT;
1269 portmode |= ETM_PORT_16BIT;
1272 command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1277 if (strcmp("normal", args[2]) == 0)
1279 portmode |= ETM_PORT_NORMAL;
1281 else if (strcmp("multiplexed", args[2]) == 0)
1283 portmode |= ETM_PORT_MUXED;
1285 else if (strcmp("demultiplexed", args[2]) == 0)
1287 portmode |= ETM_PORT_DEMUXED;
1291 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1296 if (strcmp("half", args[3]) == 0)
1298 portmode |= ETM_PORT_HALF_CLOCK;
1300 else if (strcmp("full", args[3]) == 0)
1302 portmode |= ETM_PORT_FULL_CLOCK;
1306 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1311 for (i = 0; etm_capture_drivers[i]; i++)
1313 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1316 if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1322 etm_ctx->capture_driver = etm_capture_drivers[i];
1328 if (!etm_capture_drivers[i])
1330 /* no supported capture driver found, don't register an ETM */
1332 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1336 etm_ctx->target = target;
1337 etm_ctx->trigger_percent = 50;
1338 etm_ctx->trace_data = NULL;
1339 etm_ctx->trace_depth = 0;
1340 etm_ctx->portmode = portmode;
1341 etm_ctx->tracemode = 0x0;
1342 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1343 etm_ctx->image = NULL;
1344 etm_ctx->pipe_index = 0;
1345 etm_ctx->data_index = 0;
1346 etm_ctx->current_pc = 0x0;
1348 etm_ctx->last_branch = 0x0;
1349 etm_ctx->last_branch_reason = 0x0;
1350 etm_ctx->last_ptr = 0x0;
1351 etm_ctx->ptr_ok = 0x0;
1352 etm_ctx->last_instruction = 0;
1354 arm7_9->etm_ctx = etm_ctx;
1356 return etm_register_user_commands(cmd_ctx);
1359 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1360 char *cmd, char **args, int argc)
1363 armv4_5_common_t *armv4_5;
1364 arm7_9_common_t *arm7_9;
1365 reg_t *etm_config_reg;
1366 reg_t *etm_sys_config_reg;
1370 target = get_current_target(cmd_ctx);
1372 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1374 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1378 if (!arm7_9->etm_ctx)
1380 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1384 etm_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CONFIG);
1385 if (!etm_config_reg)
1387 etm_sys_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_SYS_CONFIG);
1388 if (!etm_sys_config_reg)
1391 etm_get_reg(etm_config_reg);
1392 command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
1393 command_print(cmd_ctx, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg->value, 4, 4));
1394 command_print(cmd_ctx, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg->value, 8, 5));
1395 command_print(cmd_ctx, "number of counters: %i", (int)buf_get_u32(etm_config_reg->value, 13, 3));
1396 command_print(cmd_ctx, "sequencer %spresent",
1397 (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1398 command_print(cmd_ctx, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg->value, 17, 3));
1399 command_print(cmd_ctx, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg->value, 20, 3));
1400 command_print(cmd_ctx, "FIFO full %spresent",
1401 (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1402 command_print(cmd_ctx, "protocol version: %i", (int)buf_get_u32(etm_config_reg->value, 28, 3));
1404 etm_get_reg(etm_sys_config_reg);
1406 switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1418 LOG_ERROR("Illegal max_port_size");
1421 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1423 command_print(cmd_ctx, "half-rate clocking %ssupported",
1424 (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1425 command_print(cmd_ctx, "full-rate clocking %ssupported",
1426 (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1427 command_print(cmd_ctx, "normal trace format %ssupported",
1428 (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1429 command_print(cmd_ctx, "multiplex trace format %ssupported",
1430 (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1431 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1432 (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1433 command_print(cmd_ctx, "FIFO full %ssupported",
1434 (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1439 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1442 armv4_5_common_t *armv4_5;
1443 arm7_9_common_t *arm7_9;
1444 trace_status_t trace_status;
1446 target = get_current_target(cmd_ctx);
1448 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1450 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1454 if (!arm7_9->etm_ctx)
1456 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1460 trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1462 if (trace_status == TRACE_IDLE)
1464 command_print(cmd_ctx, "tracing is idle");
1468 static char *completed = " completed";
1469 static char *running = " is running";
1470 static char *overflowed = ", trace overflowed";
1471 static char *triggered = ", trace triggered";
1473 command_print(cmd_ctx, "trace collection%s%s%s",
1474 (trace_status & TRACE_RUNNING) ? running : completed,
1475 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1476 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1478 if (arm7_9->etm_ctx->trace_depth > 0)
1480 command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth));
1487 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1490 armv4_5_common_t *armv4_5;
1491 arm7_9_common_t *arm7_9;
1492 etm_context_t *etm_ctx;
1496 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1500 target = get_current_target(cmd_ctx);
1502 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1504 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1508 if (!(etm_ctx = arm7_9->etm_ctx))
1510 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1516 image_close(etm_ctx->image);
1517 free(etm_ctx->image);
1518 command_print(cmd_ctx, "previously loaded image found and closed");
1521 etm_ctx->image = malloc(sizeof(image_t));
1522 etm_ctx->image->base_address_set = 0;
1523 etm_ctx->image->start_address_set = 0;
1525 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1528 etm_ctx->image->base_address_set = 1;
1529 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1533 etm_ctx->image->base_address_set = 0;
1536 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1538 free(etm_ctx->image);
1539 etm_ctx->image = NULL;
1546 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1550 armv4_5_common_t *armv4_5;
1551 arm7_9_common_t *arm7_9;
1552 etm_context_t *etm_ctx;
1557 command_print(cmd_ctx, "usage: etm dump <file>");
1561 target = get_current_target(cmd_ctx);
1563 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1565 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1569 if (!(etm_ctx = arm7_9->etm_ctx))
1571 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1575 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1577 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1581 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1583 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1584 command_print(cmd_ctx, "trace capture not completed");
1588 /* read the trace data if it wasn't read already */
1589 if (etm_ctx->trace_depth == 0)
1590 etm_ctx->capture_driver->read_trace(etm_ctx);
1592 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1597 fileio_write_u32(&file, etm_ctx->capture_status);
1598 fileio_write_u32(&file, etm_ctx->portmode);
1599 fileio_write_u32(&file, etm_ctx->tracemode);
1600 fileio_write_u32(&file, etm_ctx->trace_depth);
1602 for (i = 0; i < etm_ctx->trace_depth; i++)
1604 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1605 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1606 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1609 fileio_close(&file);
1614 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1618 armv4_5_common_t *armv4_5;
1619 arm7_9_common_t *arm7_9;
1620 etm_context_t *etm_ctx;
1625 command_print(cmd_ctx, "usage: etm load <file>");
1629 target = get_current_target(cmd_ctx);
1631 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1633 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1637 if (!(etm_ctx = arm7_9->etm_ctx))
1639 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1643 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1645 command_print(cmd_ctx, "trace capture running, stop first");
1649 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1656 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1657 fileio_close(&file);
1661 if (etm_ctx->trace_depth > 0)
1663 free(etm_ctx->trace_data);
1664 etm_ctx->trace_data = NULL;
1669 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1670 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1671 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1672 fileio_read_u32(&file, &etm_ctx->trace_depth);
1674 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1675 if (etm_ctx->trace_data == NULL)
1677 command_print(cmd_ctx, "not enough memory to perform operation");
1678 fileio_close(&file);
1682 for (i = 0; i < etm_ctx->trace_depth; i++)
1684 uint32_t pipestat, packet, flags;
1685 fileio_read_u32(&file, &pipestat);
1686 fileio_read_u32(&file, &packet);
1687 fileio_read_u32(&file, &flags);
1688 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1689 etm_ctx->trace_data[i].packet = packet & 0xffff;
1690 etm_ctx->trace_data[i].flags = flags;
1693 fileio_close(&file);
1698 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1701 armv4_5_common_t *armv4_5;
1702 arm7_9_common_t *arm7_9;
1703 etm_context_t *etm_ctx;
1705 target = get_current_target(cmd_ctx);
1707 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1709 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1713 if (!(etm_ctx = arm7_9->etm_ctx))
1715 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1721 uint32_t new_value = strtoul(args[0], NULL, 0);
1723 if ((new_value < 2) || (new_value > 100))
1725 command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1729 etm_ctx->trigger_percent = new_value;
1733 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1738 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1741 armv4_5_common_t *armv4_5;
1742 arm7_9_common_t *arm7_9;
1743 etm_context_t *etm_ctx;
1744 reg_t *etm_ctrl_reg;
1746 target = get_current_target(cmd_ctx);
1748 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1750 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1754 if (!(etm_ctx = arm7_9->etm_ctx))
1756 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1760 /* invalidate old tracing data */
1761 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1762 if (arm7_9->etm_ctx->trace_depth > 0)
1764 free(arm7_9->etm_ctx->trace_data);
1765 arm7_9->etm_ctx->trace_data = NULL;
1767 arm7_9->etm_ctx->trace_depth = 0;
1769 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1773 etm_get_reg(etm_ctrl_reg);
1775 /* Clear programming bit (10), set port selection bit (11) */
1776 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1778 etm_store_reg(etm_ctrl_reg);
1779 jtag_execute_queue();
1781 etm_ctx->capture_driver->start_capture(etm_ctx);
1786 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1789 armv4_5_common_t *armv4_5;
1790 arm7_9_common_t *arm7_9;
1791 etm_context_t *etm_ctx;
1792 reg_t *etm_ctrl_reg;
1794 target = get_current_target(cmd_ctx);
1796 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1798 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1802 if (!(etm_ctx = arm7_9->etm_ctx))
1804 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1808 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1812 etm_get_reg(etm_ctrl_reg);
1814 /* Set programming bit (10), clear port selection bit (11) */
1815 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1817 etm_store_reg(etm_ctrl_reg);
1818 jtag_execute_queue();
1820 etm_ctx->capture_driver->stop_capture(etm_ctx);
1825 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1828 armv4_5_common_t *armv4_5;
1829 arm7_9_common_t *arm7_9;
1830 etm_context_t *etm_ctx;
1833 target = get_current_target(cmd_ctx);
1835 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1837 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1841 if (!(etm_ctx = arm7_9->etm_ctx))
1843 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1847 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1851 case ERROR_ETM_ANALYSIS_FAILED:
1852 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1854 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1855 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1857 case ERROR_TRACE_IMAGE_UNAVAILABLE:
1858 command_print(cmd_ctx, "no image available for trace analysis");
1861 command_print(cmd_ctx, "unknown error: %i", retval);
1868 int etm_register_commands(struct command_context_s *cmd_ctx)
1870 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1872 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
1873 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1878 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
1880 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1881 COMMAND_EXEC, "configure/display trace mode: "
1882 "<none | data | address | all> "
1883 "<context_id_bits> <cycle_accurate> <branch_output>");
1885 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1886 COMMAND_EXEC, "display info about the current target's ETM");
1888 register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
1889 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1890 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1891 COMMAND_EXEC, "display current target's ETM status");
1892 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1893 COMMAND_EXEC, "start ETM trace collection");
1894 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1895 COMMAND_EXEC, "stop ETM trace collection");
1897 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1898 COMMAND_EXEC, "anaylze collected ETM trace");
1900 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1901 COMMAND_EXEC, "load image from <file> [base address]");
1903 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1904 COMMAND_EXEC, "dump captured trace data <file>");
1905 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1906 COMMAND_EXEC, "load trace data for analysis <file>");