1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
31 /* ETM register access functionality
36 static bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
45 static int etm_reg_arch_info[] =
47 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
48 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
49 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
50 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
51 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
52 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
53 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
54 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
55 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
56 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
57 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
58 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
59 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
60 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
63 static int etm_reg_arch_size_info[] =
65 32, 32, 17, 8, 3, 9, 32, 16,
66 17, 26, 25, 8, 17, 32, 32, 17,
67 32, 32, 32, 32, 32, 32, 32, 32,
68 32, 32, 32, 32, 32, 32, 32, 32,
69 7, 7, 7, 7, 7, 7, 7, 7,
70 7, 7, 7, 7, 7, 7, 7, 7,
71 32, 32, 32, 32, 32, 32, 32, 32,
72 32, 32, 32, 32, 32, 32, 32, 32,
73 32, 32, 32, 32, 32, 32, 32, 32,
74 32, 32, 32, 32, 32, 32, 32, 32,
75 16, 16, 16, 16, 18, 18, 18, 18,
76 17, 17, 17, 17, 16, 16, 16, 16,
77 17, 17, 17, 17, 17, 17, 2,
78 17, 17, 17, 17, 32, 32, 32, 32
81 static char* etm_reg_list[] =
89 "ETM_TRACE_RESOURCE_CTRL",
93 "ETM_FIFOFULL_REGION",
99 "ETM_ADDR_COMPARATOR_VALUE1",
100 "ETM_ADDR_COMPARATOR_VALUE2",
101 "ETM_ADDR_COMPARATOR_VALUE3",
102 "ETM_ADDR_COMPARATOR_VALUE4",
103 "ETM_ADDR_COMPARATOR_VALUE5",
104 "ETM_ADDR_COMPARATOR_VALUE6",
105 "ETM_ADDR_COMPARATOR_VALUE7",
106 "ETM_ADDR_COMPARATOR_VALUE8",
107 "ETM_ADDR_COMPARATOR_VALUE9",
108 "ETM_ADDR_COMPARATOR_VALUE10",
109 "ETM_ADDR_COMPARATOR_VALUE11",
110 "ETM_ADDR_COMPARATOR_VALUE12",
111 "ETM_ADDR_COMPARATOR_VALUE13",
112 "ETM_ADDR_COMPARATOR_VALUE14",
113 "ETM_ADDR_COMPARATOR_VALUE15",
114 "ETM_ADDR_COMPARATOR_VALUE16",
115 "ETM_ADDR_ACCESS_TYPE1",
116 "ETM_ADDR_ACCESS_TYPE2",
117 "ETM_ADDR_ACCESS_TYPE3",
118 "ETM_ADDR_ACCESS_TYPE4",
119 "ETM_ADDR_ACCESS_TYPE5",
120 "ETM_ADDR_ACCESS_TYPE6",
121 "ETM_ADDR_ACCESS_TYPE7",
122 "ETM_ADDR_ACCESS_TYPE8",
123 "ETM_ADDR_ACCESS_TYPE9",
124 "ETM_ADDR_ACCESS_TYPE10",
125 "ETM_ADDR_ACCESS_TYPE11",
126 "ETM_ADDR_ACCESS_TYPE12",
127 "ETM_ADDR_ACCESS_TYPE13",
128 "ETM_ADDR_ACCESS_TYPE14",
129 "ETM_ADDR_ACCESS_TYPE15",
130 "ETM_ADDR_ACCESS_TYPE16",
131 "ETM_DATA_COMPARATOR_VALUE1",
132 "ETM_DATA_COMPARATOR_VALUE2",
133 "ETM_DATA_COMPARATOR_VALUE3",
134 "ETM_DATA_COMPARATOR_VALUE4",
135 "ETM_DATA_COMPARATOR_VALUE5",
136 "ETM_DATA_COMPARATOR_VALUE6",
137 "ETM_DATA_COMPARATOR_VALUE7",
138 "ETM_DATA_COMPARATOR_VALUE8",
139 "ETM_DATA_COMPARATOR_VALUE9",
140 "ETM_DATA_COMPARATOR_VALUE10",
141 "ETM_DATA_COMPARATOR_VALUE11",
142 "ETM_DATA_COMPARATOR_VALUE12",
143 "ETM_DATA_COMPARATOR_VALUE13",
144 "ETM_DATA_COMPARATOR_VALUE14",
145 "ETM_DATA_COMPARATOR_VALUE15",
146 "ETM_DATA_COMPARATOR_VALUE16",
147 "ETM_DATA_COMPARATOR_MASK1",
148 "ETM_DATA_COMPARATOR_MASK2",
149 "ETM_DATA_COMPARATOR_MASK3",
150 "ETM_DATA_COMPARATOR_MASK4",
151 "ETM_DATA_COMPARATOR_MASK5",
152 "ETM_DATA_COMPARATOR_MASK6",
153 "ETM_DATA_COMPARATOR_MASK7",
154 "ETM_DATA_COMPARATOR_MASK8",
155 "ETM_DATA_COMPARATOR_MASK9",
156 "ETM_DATA_COMPARATOR_MASK10",
157 "ETM_DATA_COMPARATOR_MASK11",
158 "ETM_DATA_COMPARATOR_MASK12",
159 "ETM_DATA_COMPARATOR_MASK13",
160 "ETM_DATA_COMPARATOR_MASK14",
161 "ETM_DATA_COMPARATOR_MASK15",
162 "ETM_DATA_COMPARATOR_MASK16",
163 "ETM_COUNTER_INITAL_VALUE1",
164 "ETM_COUNTER_INITAL_VALUE2",
165 "ETM_COUNTER_INITAL_VALUE3",
166 "ETM_COUNTER_INITAL_VALUE4",
167 "ETM_COUNTER_ENABLE1",
168 "ETM_COUNTER_ENABLE2",
169 "ETM_COUNTER_ENABLE3",
170 "ETM_COUNTER_ENABLE4",
171 "ETM_COUNTER_RELOAD_VALUE1",
172 "ETM_COUNTER_RELOAD_VALUE2",
173 "ETM_COUNTER_RELOAD_VALUE3",
174 "ETM_COUNTER_RELOAD_VALUE4",
175 "ETM_COUNTER_VALUE1",
176 "ETM_COUNTER_VALUE2",
177 "ETM_COUNTER_VALUE3",
178 "ETM_COUNTER_VALUE4",
179 "ETM_SEQUENCER_CTRL1",
180 "ETM_SEQUENCER_CTRL2",
181 "ETM_SEQUENCER_CTRL3",
182 "ETM_SEQUENCER_CTRL4",
183 "ETM_SEQUENCER_CTRL5",
184 "ETM_SEQUENCER_CTRL6",
185 "ETM_SEQUENCER_STATE",
186 "ETM_EXTERNAL_OUTPUT1",
187 "ETM_EXTERNAL_OUTPUT2",
188 "ETM_EXTERNAL_OUTPUT3",
189 "ETM_EXTERNAL_OUTPUT4",
190 "ETM_CONTEXTID_COMPARATOR_VALUE1",
191 "ETM_CONTEXTID_COMPARATOR_VALUE2",
192 "ETM_CONTEXTID_COMPARATOR_VALUE3",
193 "ETM_CONTEXTID_COMPARATOR_MASK"
196 static int etm_reg_arch_type = -1;
198 static int etm_get_reg(reg_t *reg);
200 static command_t *etm_cmd = NULL;
202 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
204 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
205 reg_t *reg_list = NULL;
206 etm_reg_t *arch_info = NULL;
207 int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
210 /* register a register arch-type for etm registers only once */
211 if (etm_reg_arch_type == -1)
212 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
214 /* the actual registers are kept in two arrays */
215 reg_list = calloc(num_regs, sizeof(reg_t));
216 arch_info = calloc(num_regs, sizeof(etm_reg_t));
218 /* fill in values for the reg cache */
219 reg_cache->name = "etm registers";
220 reg_cache->next = NULL;
221 reg_cache->reg_list = reg_list;
222 reg_cache->num_regs = num_regs;
224 /* set up registers */
225 for (i = 0; i < num_regs; i++)
227 reg_list[i].name = etm_reg_list[i];
228 reg_list[i].size = 32;
229 reg_list[i].dirty = 0;
230 reg_list[i].valid = 0;
231 reg_list[i].bitfield_desc = NULL;
232 reg_list[i].num_bitfields = 0;
233 reg_list[i].value = calloc(1, 4);
234 reg_list[i].arch_info = &arch_info[i];
235 reg_list[i].arch_type = etm_reg_arch_type;
236 reg_list[i].size = etm_reg_arch_size_info[i];
237 arch_info[i].addr = etm_reg_arch_info[i];
238 arch_info[i].jtag_info = jtag_info;
241 /* the ETM might have an ETB connected */
242 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
244 etb_t *etb = etm_ctx->capture_driver_priv;
248 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
252 reg_cache->next = etb_build_reg_cache(etb);
254 etb->reg_cache = reg_cache->next;
261 int etm_setup(target_t *target)
265 armv4_5_common_t *armv4_5 = target->arch_info;
266 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
267 etm_context_t *etm_ctx = arm7_9->etm_ctx;
268 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
270 /* initialize some ETM control register settings */
271 etm_get_reg(etm_ctrl_reg);
272 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
274 /* clear the ETM powerdown bit (0) */
275 etm_ctrl_value &= ~0x1;
277 /* configure port width (6:4), mode (17:16) and clocking (13) */
278 etm_ctrl_value = (etm_ctrl_value &
279 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
282 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
283 etm_store_reg(etm_ctrl_reg);
285 if ((retval=jtag_execute_queue())!=ERROR_OK)
288 if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
290 LOG_ERROR("ETM capture driver initialization failed");
296 int etm_get_reg(reg_t *reg)
300 if ((retval = etm_read_reg(reg)) != ERROR_OK)
302 LOG_ERROR("BUG: error scheduling etm register read");
306 if ((retval = jtag_execute_queue()) != ERROR_OK)
308 LOG_ERROR("register read failed");
315 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
317 etm_reg_t *etm_reg = reg->arch_info;
318 u8 reg_addr = etm_reg->addr & 0x7f;
319 scan_field_t fields[3];
321 LOG_DEBUG("%i", etm_reg->addr);
323 jtag_add_end_state(TAP_IDLE);
324 arm_jtag_scann(etm_reg->jtag_info, 0x6);
325 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
327 fields[0].tap = etm_reg->jtag_info->tap;
328 fields[0].num_bits = 32;
329 fields[0].out_value = reg->value;
330 fields[0].in_value = NULL;
332 fields[1].tap = etm_reg->jtag_info->tap;
333 fields[1].num_bits = 7;
334 fields[1].out_value = malloc(1);
335 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
336 fields[1].in_value = NULL;
338 fields[2].tap = etm_reg->jtag_info->tap;
339 fields[2].num_bits = 1;
340 fields[2].out_value = malloc(1);
341 buf_set_u32(fields[2].out_value, 0, 1, 0);
342 fields[2].in_value = NULL;
344 jtag_add_dr_scan(3, fields, TAP_INVALID);
346 fields[0].in_value = reg->value;
348 jtag_add_dr_scan(3, fields, TAP_INVALID);
350 jtag_check_value_mask(fields+0, check_value, check_mask);
352 free(fields[1].out_value);
353 free(fields[2].out_value);
358 int etm_read_reg(reg_t *reg)
360 return etm_read_reg_w_check(reg, NULL, NULL);
363 int etm_set_reg(reg_t *reg, u32 value)
367 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
369 LOG_ERROR("BUG: error scheduling etm register write");
373 buf_set_u32(reg->value, 0, reg->size, value);
380 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
384 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
386 if ((retval = jtag_execute_queue()) != ERROR_OK)
388 LOG_ERROR("register write failed");
394 int etm_write_reg(reg_t *reg, u32 value)
396 etm_reg_t *etm_reg = reg->arch_info;
397 u8 reg_addr = etm_reg->addr & 0x7f;
398 scan_field_t fields[3];
400 LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
402 jtag_add_end_state(TAP_IDLE);
403 arm_jtag_scann(etm_reg->jtag_info, 0x6);
404 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
406 fields[0].tap = etm_reg->jtag_info->tap;
407 fields[0].num_bits = 32;
408 fields[0].out_value = malloc(4);
409 buf_set_u32(fields[0].out_value, 0, 32, value);
411 fields[0].in_value = NULL;
413 fields[1].tap = etm_reg->jtag_info->tap;
414 fields[1].num_bits = 7;
415 fields[1].out_value = malloc(1);
416 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
418 fields[1].in_value = NULL;
420 fields[2].tap = etm_reg->jtag_info->tap;
421 fields[2].num_bits = 1;
422 fields[2].out_value = malloc(1);
423 buf_set_u32(fields[2].out_value, 0, 1, 1);
425 fields[2].in_value = NULL;
427 jtag_add_dr_scan(3, fields, TAP_INVALID);
429 free(fields[0].out_value);
430 free(fields[1].out_value);
431 free(fields[2].out_value);
436 int etm_store_reg(reg_t *reg)
438 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
441 /* ETM trace analysis functionality
444 extern etm_capture_driver_t etm_dummy_capture_driver;
445 #if BUILD_OOCD_TRACE == 1
446 extern etm_capture_driver_t oocd_trace_capture_driver;
449 static etm_capture_driver_t *etm_capture_drivers[] =
452 &etm_dummy_capture_driver,
453 #if BUILD_OOCD_TRACE == 1
454 &oocd_trace_capture_driver,
459 char *etmv1v1_branch_reason_strings[] =
463 "trace restarted after overflow",
465 "periodic synchronization",
471 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
480 return ERROR_TRACE_IMAGE_UNAVAILABLE;
482 /* search for the section the current instruction belongs to */
483 for (i = 0; i < ctx->image->num_sections; i++)
485 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
486 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
495 /* current instruction couldn't be found in the image */
496 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
499 if (ctx->core_state == ARMV4_5_STATE_ARM)
502 if ((retval = image_read_section(ctx->image, section,
503 ctx->current_pc - ctx->image->sections[section].base_address,
504 4, buf, &size_read)) != ERROR_OK)
506 LOG_ERROR("error while reading instruction: %i", retval);
507 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
509 opcode = target_buffer_get_u32(ctx->target, buf);
510 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
512 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
515 if ((retval = image_read_section(ctx->image, section,
516 ctx->current_pc - ctx->image->sections[section].base_address,
517 2, buf, &size_read)) != ERROR_OK)
519 LOG_ERROR("error while reading instruction: %i", retval);
520 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
522 opcode = target_buffer_get_u16(ctx->target, buf);
523 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
525 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
527 LOG_ERROR("BUG: tracing of jazelle code not supported");
532 LOG_ERROR("BUG: unknown core state encountered");
539 static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
541 while (ctx->data_index < ctx->trace_depth)
543 /* if the caller specified an address packet offset, skip until the
544 * we reach the n-th cycle marked with tracesync */
547 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
558 /* no tracedata output during a TD cycle
559 * or in a trigger cycle */
560 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
561 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
568 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
570 if (ctx->data_half == 0)
572 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
577 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
582 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
584 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
589 /* on a 4-bit port, a packet will be output during two consecutive cycles */
590 if (ctx->data_index > (ctx->trace_depth - 2))
593 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
594 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
595 ctx->data_index += 2;
604 static int etmv1_branch_address(etm_context_t *ctx)
612 /* quit analysis if less than two cycles are left in the trace
613 * because we can't extract the APO */
614 if (ctx->data_index > (ctx->trace_depth - 2))
617 /* a BE could be output during an APO cycle, skip the current
618 * and continue with the new one */
619 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
621 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
624 /* address packet offset encoded in the next two cycles' pipestat bits */
625 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
626 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
628 /* count number of tracesync cycles between current pipe_index and data_index
629 * i.e. the number of tracesyncs that data_index already passed by
630 * to subtract them from the APO */
631 for (i = ctx->pipe_index; i < ctx->data_index; i++)
633 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
637 /* extract up to four 7-bit packets */
639 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
641 ctx->last_branch &= ~(0x7f << shift);
642 ctx->last_branch |= (packet & 0x7f) << shift;
644 } while ((packet & 0x80) && (shift < 28));
646 /* one last packet holding 4 bits of the address, plus the branch reason code */
647 if ((shift == 28) && (packet & 0x80))
649 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
651 ctx->last_branch &= 0x0fffffff;
652 ctx->last_branch |= (packet & 0x0f) << 28;
653 ctx->last_branch_reason = (packet & 0x70) >> 4;
658 ctx->last_branch_reason = 0;
666 /* if a full address was output, we might have branched into Jazelle state */
667 if ((shift == 32) && (packet & 0x80))
669 ctx->core_state = ARMV4_5_STATE_JAZELLE;
673 /* if we didn't branch into Jazelle state, the current processor state is
674 * encoded in bit 0 of the branch target address */
675 if (ctx->last_branch & 0x1)
677 ctx->core_state = ARMV4_5_STATE_THUMB;
678 ctx->last_branch &= ~0x1;
682 ctx->core_state = ARMV4_5_STATE_ARM;
683 ctx->last_branch &= ~0x3;
690 static int etmv1_data(etm_context_t *ctx, int size, u32 *data)
696 for (j = 0; j < size; j++)
698 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
704 LOG_ERROR("TODO: add support for 64-bit values");
708 *data = target_buffer_get_u32(ctx->target, buf);
710 *data = target_buffer_get_u16(ctx->target, buf);
719 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
722 arm_instruction_t instruction;
724 /* read the trace data if it wasn't read already */
725 if (ctx->trace_depth == 0)
726 ctx->capture_driver->read_trace(ctx);
728 /* start at the beginning of the captured trace */
733 /* neither the PC nor the data pointer are valid */
737 while (ctx->pipe_index < ctx->trace_depth)
739 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
740 u32 next_pc = ctx->current_pc;
741 u32 old_data_index = ctx->data_index;
742 u32 old_data_half = ctx->data_half;
743 u32 old_index = ctx->pipe_index;
744 u32 last_instruction = ctx->last_instruction;
746 int current_pc_ok = ctx->pc_ok;
748 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
750 command_print(cmd_ctx, "--- trigger ---");
753 /* instructions execute in IE/D or BE/D cycles */
754 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
755 ctx->last_instruction = ctx->pipe_index;
757 /* if we don't have a valid pc skip until we reach an indirect branch */
758 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
764 /* any indirect branch could have interrupted instruction flow
765 * - the branch reason code could indicate a trace discontinuity
766 * - a branch to the exception vectors indicates an exception
768 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
770 /* backup current data index, to be able to consume the branch address
771 * before examining data address and values
773 old_data_index = ctx->data_index;
774 old_data_half = ctx->data_half;
776 ctx->last_instruction = ctx->pipe_index;
778 if ((retval = etmv1_branch_address(ctx)) != 0)
780 /* negative return value from etmv1_branch_address means we ran out of packets,
781 * quit analysing the trace */
785 /* a positive return values means the current branch was abandoned,
786 * and a new branch was encountered in cycle ctx->pipe_index + retval;
788 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
789 ctx->pipe_index += retval;
793 /* skip over APO cycles */
794 ctx->pipe_index += 2;
796 switch (ctx->last_branch_reason)
798 case 0x0: /* normal PC change */
799 next_pc = ctx->last_branch;
801 case 0x1: /* tracing enabled */
802 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
803 ctx->current_pc = ctx->last_branch;
807 case 0x2: /* trace restarted after FIFO overflow */
808 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
809 ctx->current_pc = ctx->last_branch;
813 case 0x3: /* exit from debug state */
814 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
815 ctx->current_pc = ctx->last_branch;
819 case 0x4: /* periodic synchronization point */
820 next_pc = ctx->last_branch;
821 /* if we had no valid PC prior to this synchronization point,
822 * we have to move on with the next trace cycle
826 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
827 ctx->current_pc = next_pc;
832 default: /* reserved */
833 LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
838 /* if we got here the branch was a normal PC change
839 * (or a periodic synchronization point, which means the same for that matter)
840 * if we didn't accquire a complete PC continue with the next cycle
845 /* indirect branch to the exception vector means an exception occured */
846 if ((ctx->last_branch <= 0x20)
847 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
849 if ((ctx->last_branch & 0xff) == 0x10)
851 command_print(cmd_ctx, "data abort");
855 command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
856 ctx->current_pc = ctx->last_branch;
863 /* an instruction was executed (or not, depending on the condition flags)
864 * retrieve it from the image for displaying */
865 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
866 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
867 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
869 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
871 /* can't continue tracing with no image available */
872 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
876 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
878 /* TODO: handle incomplete images
879 * for now we just quit the analsysis*/
884 cycles = old_index - last_instruction;
887 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
889 u32 new_data_index = ctx->data_index;
890 u32 new_data_half = ctx->data_half;
892 /* in case of a branch with data, the branch target address was consumed before
893 * we temporarily go back to the saved data index */
894 if (pipestat == STAT_BD)
896 ctx->data_index = old_data_index;
897 ctx->data_half = old_data_half;
900 if (ctx->tracemode & ETMV1_TRACE_ADDR)
906 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
907 return ERROR_ETM_ANALYSIS_FAILED;
908 ctx->last_ptr &= ~(0x7f << shift);
909 ctx->last_ptr |= (packet & 0x7f) << shift;
911 } while ((packet & 0x80) && (shift < 32));
918 command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
922 if (ctx->tracemode & ETMV1_TRACE_DATA)
924 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
927 for (i = 0; i < 16; i++)
929 if (instruction.info.load_store_multiple.register_list & (1 << i))
932 if (etmv1_data(ctx, 4, &data) != 0)
933 return ERROR_ETM_ANALYSIS_FAILED;
934 command_print(cmd_ctx, "data: 0x%8.8x", data);
938 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
941 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
942 return ERROR_ETM_ANALYSIS_FAILED;
943 command_print(cmd_ctx, "data: 0x%8.8x", data);
947 /* restore data index after consuming BD address and data */
948 if (pipestat == STAT_BD)
950 ctx->data_index = new_data_index;
951 ctx->data_half = new_data_half;
956 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
958 if (((instruction.type == ARM_B) ||
959 (instruction.type == ARM_BL) ||
960 (instruction.type == ARM_BLX)) &&
961 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
963 next_pc = instruction.info.b_bl_bx_blx.target_address;
967 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
970 else if (pipestat == STAT_IN)
972 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
975 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
977 char cycles_text[32] = "";
979 /* if the trace was captured with cycle accurate tracing enabled,
980 * output the number of cycles since the last executed instruction
982 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
984 snprintf(cycles_text, 32, " (%i %s)",
986 (cycles == 1) ? "cycle" : "cycles");
989 command_print(cmd_ctx, "%s%s%s",
991 (pipestat == STAT_IN) ? " (not executed)" : "",
994 ctx->current_pc = next_pc;
996 /* packets for an instruction don't start on or before the preceding
997 * functional pipestat (i.e. other than WT or TD)
999 if (ctx->data_index <= ctx->pipe_index)
1001 ctx->data_index = ctx->pipe_index + 1;
1006 ctx->pipe_index += 1;
1012 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1015 armv4_5_common_t *armv4_5;
1016 arm7_9_common_t *arm7_9;
1017 etmv1_tracemode_t tracemode;
1019 target = get_current_target(cmd_ctx);
1021 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1023 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1027 if (!arm7_9->etm_ctx)
1029 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1033 tracemode = arm7_9->etm_ctx->tracemode;
1037 if (strcmp(args[0], "none") == 0)
1039 tracemode = ETMV1_TRACE_NONE;
1041 else if (strcmp(args[0], "data") == 0)
1043 tracemode = ETMV1_TRACE_DATA;
1045 else if (strcmp(args[0], "address") == 0)
1047 tracemode = ETMV1_TRACE_ADDR;
1049 else if (strcmp(args[0], "all") == 0)
1051 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1055 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1059 switch (strtol(args[1], NULL, 0))
1062 tracemode |= ETMV1_CONTEXTID_NONE;
1065 tracemode |= ETMV1_CONTEXTID_8;
1068 tracemode |= ETMV1_CONTEXTID_16;
1071 tracemode |= ETMV1_CONTEXTID_32;
1074 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1078 if (strcmp(args[2], "enable") == 0)
1080 tracemode |= ETMV1_CYCLE_ACCURATE;
1082 else if (strcmp(args[2], "disable") == 0)
1088 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1092 if (strcmp(args[3], "enable") == 0)
1094 tracemode |= ETMV1_BRANCH_OUTPUT;
1096 else if (strcmp(args[3], "disable") == 0)
1102 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1108 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1112 command_print(cmd_ctx, "current tracemode configuration:");
1114 switch (tracemode & ETMV1_TRACE_MASK)
1116 case ETMV1_TRACE_NONE:
1117 command_print(cmd_ctx, "data tracing: none");
1119 case ETMV1_TRACE_DATA:
1120 command_print(cmd_ctx, "data tracing: data only");
1122 case ETMV1_TRACE_ADDR:
1123 command_print(cmd_ctx, "data tracing: address only");
1125 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1126 command_print(cmd_ctx, "data tracing: address and data");
1130 switch (tracemode & ETMV1_CONTEXTID_MASK)
1132 case ETMV1_CONTEXTID_NONE:
1133 command_print(cmd_ctx, "contextid tracing: none");
1135 case ETMV1_CONTEXTID_8:
1136 command_print(cmd_ctx, "contextid tracing: 8 bit");
1138 case ETMV1_CONTEXTID_16:
1139 command_print(cmd_ctx, "contextid tracing: 16 bit");
1141 case ETMV1_CONTEXTID_32:
1142 command_print(cmd_ctx, "contextid tracing: 32 bit");
1146 if (tracemode & ETMV1_CYCLE_ACCURATE)
1148 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1152 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1155 if (tracemode & ETMV1_BRANCH_OUTPUT)
1157 command_print(cmd_ctx, "full branch address output enabled");
1161 command_print(cmd_ctx, "full branch address output disabled");
1164 /* only update ETM_CTRL register if tracemode changed */
1165 if (arm7_9->etm_ctx->tracemode != tracemode)
1167 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1169 etm_get_reg(etm_ctrl_reg);
1171 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1172 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1173 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1174 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1175 etm_store_reg(etm_ctrl_reg);
1177 arm7_9->etm_ctx->tracemode = tracemode;
1179 /* invalidate old trace data */
1180 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1181 if (arm7_9->etm_ctx->trace_depth > 0)
1183 free(arm7_9->etm_ctx->trace_data);
1184 arm7_9->etm_ctx->trace_data = NULL;
1186 arm7_9->etm_ctx->trace_depth = 0;
1192 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1195 armv4_5_common_t *armv4_5;
1196 arm7_9_common_t *arm7_9;
1197 etm_portmode_t portmode = 0x0;
1198 etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1203 return ERROR_COMMAND_SYNTAX_ERROR;
1206 target = get_target_by_num(strtoul(args[0], NULL, 0));
1210 LOG_ERROR("target number '%s' not defined", args[0]);
1214 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1216 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1220 switch (strtoul(args[1], NULL, 0))
1223 portmode |= ETM_PORT_4BIT;
1226 portmode |= ETM_PORT_8BIT;
1229 portmode |= ETM_PORT_16BIT;
1232 command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1236 if (strcmp("normal", args[2]) == 0)
1238 portmode |= ETM_PORT_NORMAL;
1240 else if (strcmp("multiplexed", args[2]) == 0)
1242 portmode |= ETM_PORT_MUXED;
1244 else if (strcmp("demultiplexed", args[2]) == 0)
1246 portmode |= ETM_PORT_DEMUXED;
1250 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1254 if (strcmp("half", args[3]) == 0)
1256 portmode |= ETM_PORT_HALF_CLOCK;
1258 else if (strcmp("full", args[3]) == 0)
1260 portmode |= ETM_PORT_FULL_CLOCK;
1264 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1268 for (i=0; etm_capture_drivers[i]; i++)
1270 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1273 if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1279 etm_ctx->capture_driver = etm_capture_drivers[i];
1285 if (!etm_capture_drivers[i])
1287 /* no supported capture driver found, don't register an ETM */
1289 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1293 etm_ctx->target = target;
1294 etm_ctx->trigger_percent = 50;
1295 etm_ctx->trace_data = NULL;
1296 etm_ctx->trace_depth = 0;
1297 etm_ctx->portmode = portmode;
1298 etm_ctx->tracemode = 0x0;
1299 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1300 etm_ctx->image = NULL;
1301 etm_ctx->pipe_index = 0;
1302 etm_ctx->data_index = 0;
1303 etm_ctx->current_pc = 0x0;
1305 etm_ctx->last_branch = 0x0;
1306 etm_ctx->last_branch_reason = 0x0;
1307 etm_ctx->last_ptr = 0x0;
1308 etm_ctx->ptr_ok = 0x0;
1309 etm_ctx->context_id = 0x0;
1310 etm_ctx->last_instruction = 0;
1312 arm7_9->etm_ctx = etm_ctx;
1314 return etm_register_user_commands(cmd_ctx);
1317 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1320 armv4_5_common_t *armv4_5;
1321 arm7_9_common_t *arm7_9;
1322 reg_t *etm_config_reg;
1323 reg_t *etm_sys_config_reg;
1327 target = get_current_target(cmd_ctx);
1329 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1331 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1335 if (!arm7_9->etm_ctx)
1337 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1341 etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1342 etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1344 etm_get_reg(etm_config_reg);
1345 command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1346 command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1347 command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1348 command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1349 command_print(cmd_ctx, "sequencer %spresent",
1350 (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1351 command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1352 command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1353 command_print(cmd_ctx, "FIFO full %spresent",
1354 (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1355 command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1357 etm_get_reg(etm_sys_config_reg);
1359 switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1371 LOG_ERROR("Illegal max_port_size");
1374 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1376 command_print(cmd_ctx, "half-rate clocking %ssupported",
1377 (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1378 command_print(cmd_ctx, "full-rate clocking %ssupported",
1379 (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1380 command_print(cmd_ctx, "normal trace format %ssupported",
1381 (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1382 command_print(cmd_ctx, "multiplex trace format %ssupported",
1383 (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1384 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1385 (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1386 command_print(cmd_ctx, "FIFO full %ssupported",
1387 (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1392 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1395 armv4_5_common_t *armv4_5;
1396 arm7_9_common_t *arm7_9;
1397 trace_status_t trace_status;
1399 target = get_current_target(cmd_ctx);
1401 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1403 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1407 if (!arm7_9->etm_ctx)
1409 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1413 trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1415 if (trace_status == TRACE_IDLE)
1417 command_print(cmd_ctx, "tracing is idle");
1421 static char *completed = " completed";
1422 static char *running = " is running";
1423 static char *overflowed = ", trace overflowed";
1424 static char *triggered = ", trace triggered";
1426 command_print(cmd_ctx, "trace collection%s%s%s",
1427 (trace_status & TRACE_RUNNING) ? running : completed,
1428 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1429 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1431 if (arm7_9->etm_ctx->trace_depth > 0)
1433 command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1440 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1443 armv4_5_common_t *armv4_5;
1444 arm7_9_common_t *arm7_9;
1445 etm_context_t *etm_ctx;
1449 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1453 target = get_current_target(cmd_ctx);
1455 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1457 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1461 if (!(etm_ctx = arm7_9->etm_ctx))
1463 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1469 image_close(etm_ctx->image);
1470 free(etm_ctx->image);
1471 command_print(cmd_ctx, "previously loaded image found and closed");
1474 etm_ctx->image = malloc(sizeof(image_t));
1475 etm_ctx->image->base_address_set = 0;
1476 etm_ctx->image->start_address_set = 0;
1478 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1481 etm_ctx->image->base_address_set = 1;
1482 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1486 etm_ctx->image->base_address_set = 0;
1489 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1491 free(etm_ctx->image);
1492 etm_ctx->image = NULL;
1499 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1503 armv4_5_common_t *armv4_5;
1504 arm7_9_common_t *arm7_9;
1505 etm_context_t *etm_ctx;
1510 command_print(cmd_ctx, "usage: etm dump <file>");
1514 target = get_current_target(cmd_ctx);
1516 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1518 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1522 if (!(etm_ctx = arm7_9->etm_ctx))
1524 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1528 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1530 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1534 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1536 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1537 command_print(cmd_ctx, "trace capture not completed");
1541 /* read the trace data if it wasn't read already */
1542 if (etm_ctx->trace_depth == 0)
1543 etm_ctx->capture_driver->read_trace(etm_ctx);
1545 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1550 fileio_write_u32(&file, etm_ctx->capture_status);
1551 fileio_write_u32(&file, etm_ctx->portmode);
1552 fileio_write_u32(&file, etm_ctx->tracemode);
1553 fileio_write_u32(&file, etm_ctx->trace_depth);
1555 for (i = 0; i < etm_ctx->trace_depth; i++)
1557 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1558 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1559 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1562 fileio_close(&file);
1567 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1571 armv4_5_common_t *armv4_5;
1572 arm7_9_common_t *arm7_9;
1573 etm_context_t *etm_ctx;
1578 command_print(cmd_ctx, "usage: etm load <file>");
1582 target = get_current_target(cmd_ctx);
1584 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1586 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1590 if (!(etm_ctx = arm7_9->etm_ctx))
1592 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1596 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1598 command_print(cmd_ctx, "trace capture running, stop first");
1602 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1609 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1610 fileio_close(&file);
1614 if (etm_ctx->trace_depth > 0)
1616 free(etm_ctx->trace_data);
1617 etm_ctx->trace_data = NULL;
1620 fileio_read_u32(&file, &etm_ctx->capture_status);
1621 fileio_read_u32(&file, &etm_ctx->portmode);
1622 fileio_read_u32(&file, &etm_ctx->tracemode);
1623 fileio_read_u32(&file, &etm_ctx->trace_depth);
1625 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1626 if (etm_ctx->trace_data == NULL)
1628 command_print(cmd_ctx, "not enough memory to perform operation");
1629 fileio_close(&file);
1633 for (i = 0; i < etm_ctx->trace_depth; i++)
1635 u32 pipestat, packet, flags;
1636 fileio_read_u32(&file, &pipestat);
1637 fileio_read_u32(&file, &packet);
1638 fileio_read_u32(&file, &flags);
1639 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1640 etm_ctx->trace_data[i].packet = packet & 0xffff;
1641 etm_ctx->trace_data[i].flags = flags;
1644 fileio_close(&file);
1649 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1652 armv4_5_common_t *armv4_5;
1653 arm7_9_common_t *arm7_9;
1654 etm_context_t *etm_ctx;
1656 target = get_current_target(cmd_ctx);
1658 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1660 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1664 if (!(etm_ctx = arm7_9->etm_ctx))
1666 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1672 u32 new_value = strtoul(args[0], NULL, 0);
1674 if ((new_value < 2) || (new_value > 100))
1676 command_print(cmd_ctx, "valid settings are 2% to 100%");
1680 etm_ctx->trigger_percent = new_value;
1684 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1689 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1692 armv4_5_common_t *armv4_5;
1693 arm7_9_common_t *arm7_9;
1694 etm_context_t *etm_ctx;
1695 reg_t *etm_ctrl_reg;
1697 target = get_current_target(cmd_ctx);
1699 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1701 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1705 if (!(etm_ctx = arm7_9->etm_ctx))
1707 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1711 /* invalidate old tracing data */
1712 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1713 if (arm7_9->etm_ctx->trace_depth > 0)
1715 free(arm7_9->etm_ctx->trace_data);
1716 arm7_9->etm_ctx->trace_data = NULL;
1718 arm7_9->etm_ctx->trace_depth = 0;
1720 etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1721 etm_get_reg(etm_ctrl_reg);
1723 /* Clear programming bit (10), set port selection bit (11) */
1724 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1726 etm_store_reg(etm_ctrl_reg);
1727 jtag_execute_queue();
1729 etm_ctx->capture_driver->start_capture(etm_ctx);
1734 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1737 armv4_5_common_t *armv4_5;
1738 arm7_9_common_t *arm7_9;
1739 etm_context_t *etm_ctx;
1740 reg_t *etm_ctrl_reg;
1742 target = get_current_target(cmd_ctx);
1744 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1746 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1750 if (!(etm_ctx = arm7_9->etm_ctx))
1752 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1756 etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1757 etm_get_reg(etm_ctrl_reg);
1759 /* Set programming bit (10), clear port selection bit (11) */
1760 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1762 etm_store_reg(etm_ctrl_reg);
1763 jtag_execute_queue();
1765 etm_ctx->capture_driver->stop_capture(etm_ctx);
1770 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1773 armv4_5_common_t *armv4_5;
1774 arm7_9_common_t *arm7_9;
1775 etm_context_t *etm_ctx;
1778 target = get_current_target(cmd_ctx);
1780 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1782 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1786 if (!(etm_ctx = arm7_9->etm_ctx))
1788 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1792 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1796 case ERROR_ETM_ANALYSIS_FAILED:
1797 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1799 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1800 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1802 case ERROR_TRACE_IMAGE_UNAVAILABLE:
1803 command_print(cmd_ctx, "no image available for trace analysis");
1806 command_print(cmd_ctx, "unknown error: %i", retval);
1813 int etm_register_commands(struct command_context_s *cmd_ctx)
1815 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1817 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1822 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1824 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1825 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1827 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1828 COMMAND_EXEC, "display info about the current target's ETM");
1830 register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
1831 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1832 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1833 COMMAND_EXEC, "display current target's ETM status");
1834 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1835 COMMAND_EXEC, "start ETM trace collection");
1836 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1837 COMMAND_EXEC, "stop ETM trace collection");
1839 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1840 COMMAND_EXEC, "anaylze collected ETM trace");
1842 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1843 COMMAND_EXEC, "load image from <file> [base address]");
1845 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1846 COMMAND_EXEC, "dump captured trace data <file>");
1847 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1848 COMMAND_EXEC, "load trace data for analysis <file>");