1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
33 char* mips32_core_reg_list[] =
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
39 "status", "lo", "hi", "badvaddr", "cause", "pc"
42 mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
85 u8 mips32_gdb_dummy_fsr_value[] = {0, 0, 0, 0};
87 reg_t mips32_gdb_dummy_fsr_reg =
89 "GDB dummy floating-point status register", mips32_gdb_dummy_fsr_value, 0, 1, 32, NULL, 0, NULL, 0
92 u8 mips32_gdb_dummy_fir_value[] = {0, 0, 0, 0};
94 reg_t mips32_gdb_dummy_fir_reg =
96 "GDB dummy floating-point register", mips32_gdb_dummy_fir_value, 0, 1, 32, NULL, 0, NULL, 0
99 int mips32_core_reg_arch_type = -1;
101 int mips32_get_core_reg(reg_t *reg)
104 mips32_core_reg_t *mips32_reg = reg->arch_info;
105 target_t *target = mips32_reg->target;
106 mips32_common_t *mips32_target = target->arch_info;
108 if (target->state != TARGET_HALTED)
110 return ERROR_TARGET_NOT_HALTED;
113 retval = mips32_target->read_core_reg(target, mips32_reg->num);
118 int mips32_set_core_reg(reg_t *reg, u8 *buf)
120 mips32_core_reg_t *mips32_reg = reg->arch_info;
121 target_t *target = mips32_reg->target;
122 u32 value = buf_get_u32(buf, 0, 32);
124 if (target->state != TARGET_HALTED)
126 return ERROR_TARGET_NOT_HALTED;
129 buf_set_u32(reg->value, 0, 32, value);
136 int mips32_read_core_reg(struct target_s *target, int num)
139 mips32_core_reg_t *mips_core_reg;
141 /* get pointers to arch-specific information */
142 mips32_common_t *mips32 = target->arch_info;
144 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
145 return ERROR_INVALID_ARGUMENTS;
147 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
148 reg_value = mips32->core_regs[num];
149 buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
150 mips32->core_cache->reg_list[num].valid = 1;
151 mips32->core_cache->reg_list[num].dirty = 0;
156 int mips32_write_core_reg(struct target_s *target, int num)
159 mips32_core_reg_t *mips_core_reg;
161 /* get pointers to arch-specific information */
162 mips32_common_t *mips32 = target->arch_info;
164 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
165 return ERROR_INVALID_ARGUMENTS;
167 reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
168 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
169 mips32->core_regs[num] = reg_value;
170 LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
171 mips32->core_cache->reg_list[num].valid = 1;
172 mips32->core_cache->reg_list[num].dirty = 0;
177 int mips32_invalidate_core_regs(target_t *target)
179 /* get pointers to arch-specific information */
180 mips32_common_t *mips32 = target->arch_info;
183 for (i = 0; i < mips32->core_cache->num_regs; i++)
185 mips32->core_cache->reg_list[i].valid = 0;
186 mips32->core_cache->reg_list[i].dirty = 0;
192 int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
194 /* get pointers to arch-specific information */
195 mips32_common_t *mips32 = target->arch_info;
198 /* include fsr/fir reg */
199 *reg_list_size = MIPS32NUMCOREREGS + 2;
200 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
202 for (i = 0; i < MIPS32NUMCOREREGS; i++)
204 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
207 /* add dummy floating points regs */
208 (*reg_list)[38] = &mips32_gdb_dummy_fsr_reg;
209 (*reg_list)[39] = &mips32_gdb_dummy_fir_reg;
214 int mips32_save_context(target_t *target)
218 /* get pointers to arch-specific information */
219 mips32_common_t *mips32 = target->arch_info;
220 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
222 /* read core registers */
223 mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
225 for (i = 0; i < MIPS32NUMCOREREGS; i++)
227 if (!mips32->core_cache->reg_list[i].valid)
229 mips32->read_core_reg(target, i);
236 int mips32_restore_context(target_t *target)
240 /* get pointers to arch-specific information */
241 mips32_common_t *mips32 = target->arch_info;
242 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
244 for (i = 0; i < MIPS32NUMCOREREGS; i++)
246 if (mips32->core_cache->reg_list[i].dirty)
248 mips32->write_core_reg(target, i);
252 /* write core regs */
253 mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
258 int mips32_arch_state(struct target_s *target)
260 mips32_common_t *mips32 = target->arch_info;
262 if (mips32->common_magic != MIPS32_COMMON_MAGIC)
264 LOG_ERROR("BUG: called for a non-MIPS32 target");
268 LOG_USER("target halted due to %s, pc: 0x%8.8x",
269 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
270 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
275 reg_cache_t *mips32_build_reg_cache(target_t *target)
277 /* get pointers to arch-specific information */
278 mips32_common_t *mips32 = target->arch_info;
280 int num_regs = MIPS32NUMCOREREGS;
281 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
282 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
283 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
284 mips32_core_reg_t *arch_info = malloc(sizeof(mips32_core_reg_t) * num_regs);
287 if (mips32_core_reg_arch_type == -1)
288 mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
290 /* Build the process context cache */
291 cache->name = "mips32 registers";
293 cache->reg_list = reg_list;
294 cache->num_regs = num_regs;
296 mips32->core_cache = cache;
298 for (i = 0; i < num_regs; i++)
300 arch_info[i] = mips32_core_reg_list_arch_info[i];
301 arch_info[i].target = target;
302 arch_info[i].mips32_common = mips32;
303 reg_list[i].name = mips32_core_reg_list[i];
304 reg_list[i].size = 32;
305 reg_list[i].value = calloc(1, 4);
306 reg_list[i].dirty = 0;
307 reg_list[i].valid = 0;
308 reg_list[i].bitfield_desc = NULL;
309 reg_list[i].num_bitfields = 0;
310 reg_list[i].arch_type = mips32_core_reg_arch_type;
311 reg_list[i].arch_info = &arch_info[i];
317 int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant)
319 target->arch_info = mips32;
320 mips32->common_magic = MIPS32_COMMON_MAGIC;
322 mips32->ejtag_info.chain_pos = chain_pos;
323 mips32->read_core_reg = mips32_read_core_reg;
324 mips32->write_core_reg = mips32_write_core_reg;
329 int mips32_register_commands(struct command_context_s *cmd_ctx)
334 int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)