1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ***************************************************************************/
28 #include "mips32_dmaacc.h"
29 #include <helper/time_support.h>
31 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info,
32 uint32_t addr, int count, uint8_t *buf);
33 static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info,
34 uint32_t addr, int count, uint16_t *buf);
35 static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info,
36 uint32_t addr, int count, uint32_t *buf);
38 static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info,
39 uint32_t addr, int count, const uint8_t *buf);
40 static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info,
41 uint32_t addr, int count, const uint16_t *buf);
42 static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info,
43 uint32_t addr, int count, const uint32_t *buf);
46 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
47 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
48 * (and any others that support EJTAG DMA transfers).
49 * Note: This only supports memory read/write. Since the BCM5352 doesn't
50 * appear to support PRACC accesses, all debug functions except halt
51 * do not work. Still, this does allow erasing/writing flash as well as
52 * displaying/modifying memory and memory mapped registers.
55 static int ejtag_dma_dstrt_poll(struct mips_ejtag *ejtag_info)
58 int64_t start = timeval_ms();
61 if (timeval_ms() - start > 1000) {
62 LOG_ERROR("DMA time out");
65 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
66 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
67 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
71 static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
75 int retries = RETRY_ATTEMPTS;
81 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
82 mips_ejtag_drscan_32(ejtag_info, &v);
84 /* Initiate DMA Read & set DSTRT */
85 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
86 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
87 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
89 /* Wait for DSTRT to Clear */
90 ejtag_dma_dstrt_poll(ejtag_info);
93 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
94 mips_ejtag_drscan_32(ejtag_info, data);
96 /* Clear DMA & Check DERR */
97 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
98 ejtag_ctrl = ejtag_info->ejtag_ctrl;
99 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
100 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
102 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
103 goto begin_ejtag_dma_read;
105 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
106 return ERROR_JTAG_DEVICE_ERROR;
112 static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data)
116 int retries = RETRY_ATTEMPTS;
118 begin_ejtag_dma_read_h:
122 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
123 mips_ejtag_drscan_32(ejtag_info, &v);
125 /* Initiate DMA Read & set DSTRT */
126 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
127 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD |
128 EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
129 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
131 /* Wait for DSTRT to Clear */
132 ejtag_dma_dstrt_poll(ejtag_info);
135 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
136 mips_ejtag_drscan_32(ejtag_info, &v);
138 /* Clear DMA & Check DERR */
139 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
140 ejtag_ctrl = ejtag_info->ejtag_ctrl;
141 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
142 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
144 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
145 goto begin_ejtag_dma_read_h;
147 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
148 return ERROR_JTAG_DEVICE_ERROR;
151 /* Handle the bigendian/littleendian */
153 *data = (v >> 16) & 0xffff;
155 *data = (v & 0x0000ffff);
160 static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data)
164 int retries = RETRY_ATTEMPTS;
166 begin_ejtag_dma_read_b:
170 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
171 mips_ejtag_drscan_32(ejtag_info, &v);
173 /* Initiate DMA Read & set DSTRT */
174 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
175 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
176 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
178 /* Wait for DSTRT to Clear */
179 ejtag_dma_dstrt_poll(ejtag_info);
182 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
183 mips_ejtag_drscan_32(ejtag_info, &v);
185 /* Clear DMA & Check DERR */
186 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
187 ejtag_ctrl = ejtag_info->ejtag_ctrl;
188 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
189 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
191 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
192 goto begin_ejtag_dma_read_b;
194 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
195 return ERROR_JTAG_DEVICE_ERROR;
198 /* Handle the bigendian/littleendian */
199 switch (addr & 0x3) {
204 *data = (v >> 8) & 0xff;
207 *data = (v >> 16) & 0xff;
210 *data = (v >> 24) & 0xff;
217 static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
221 int retries = RETRY_ATTEMPTS;
223 begin_ejtag_dma_write:
227 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
228 mips_ejtag_drscan_32(ejtag_info, &v);
232 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
233 mips_ejtag_drscan_32(ejtag_info, &v);
235 /* Initiate DMA Write & set DSTRT */
236 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
237 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
238 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
240 /* Wait for DSTRT to Clear */
241 ejtag_dma_dstrt_poll(ejtag_info);
243 /* Clear DMA & Check DERR */
244 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
245 ejtag_ctrl = ejtag_info->ejtag_ctrl;
246 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
247 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
249 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
250 goto begin_ejtag_dma_write;
252 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
253 return ERROR_JTAG_DEVICE_ERROR;
259 static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
263 int retries = RETRY_ATTEMPTS;
265 /* Handle the bigendian/littleendian */
269 begin_ejtag_dma_write_h:
273 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
274 mips_ejtag_drscan_32(ejtag_info, &v);
278 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
279 mips_ejtag_drscan_32(ejtag_info, &v);
281 /* Initiate DMA Write & set DSTRT */
282 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
283 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
284 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
286 /* Wait for DSTRT to Clear */
287 ejtag_dma_dstrt_poll(ejtag_info);
289 /* Clear DMA & Check DERR */
290 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
291 ejtag_ctrl = ejtag_info->ejtag_ctrl;
292 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
293 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
295 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
296 goto begin_ejtag_dma_write_h;
298 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
299 return ERROR_JTAG_DEVICE_ERROR;
305 static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
309 int retries = RETRY_ATTEMPTS;
311 /* Handle the bigendian/littleendian */
316 begin_ejtag_dma_write_b:
320 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
321 mips_ejtag_drscan_32(ejtag_info, &v);
325 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
326 mips_ejtag_drscan_32(ejtag_info, &v);
328 /* Initiate DMA Write & set DSTRT */
329 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
330 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
331 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
333 /* Wait for DSTRT to Clear */
334 ejtag_dma_dstrt_poll(ejtag_info);
336 /* Clear DMA & Check DERR */
337 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
338 ejtag_ctrl = ejtag_info->ejtag_ctrl;
339 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
340 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
342 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
343 goto begin_ejtag_dma_write_b;
345 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
346 return ERROR_JTAG_DEVICE_ERROR;
352 int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
356 return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf);
358 return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf);
360 return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf);
366 static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
371 for (i = 0; i < count; i++) {
372 retval = ejtag_dma_read(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
373 if (retval != ERROR_OK)
380 static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
385 for (i = 0; i < count; i++) {
386 retval = ejtag_dma_read_h(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
387 if (retval != ERROR_OK)
394 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
399 for (i = 0; i < count; i++) {
400 retval = ejtag_dma_read_b(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
401 if (retval != ERROR_OK)
408 int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
412 return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf);
414 return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf);
416 return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf);
422 static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint32_t *buf)
427 for (i = 0; i < count; i++) {
428 retval = ejtag_dma_write(ejtag_info, addr + i * sizeof(*buf), buf[i]);
429 if (retval != ERROR_OK)
436 static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint16_t *buf)
441 for (i = 0; i < count; i++) {
442 retval = ejtag_dma_write_h(ejtag_info, addr + i * sizeof(*buf), buf[i]);
443 if (retval != ERROR_OK)
450 static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint8_t *buf)
455 for (i = 0; i < count; i++) {
456 retval = ejtag_dma_write_b(ejtag_info, addr + i * sizeof(*buf), buf[i]);
457 if (retval != ERROR_OK)