1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
29 #include "mips32_dmaacc.h"
33 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
34 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
35 * (and any others that support EJTAG DMA transfers).
36 * Note: This only supports memory read/write. Since the BCM5352 doesn't
37 * appear to support PRACC accesses, all debug functions except halt
38 * do not work. Still, this does allow erasing/writing flash as well as
39 * displaying/modifying memory and memory mapped registers.
42 static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
46 int retries = RETRY_ATTEMPTS;
52 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
53 mips_ejtag_drscan_32(ejtag_info, &v);
55 /* Initiate DMA Read & set DSTRT */
56 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
57 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
58 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
60 /* Wait for DSTRT to Clear */
62 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
63 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
64 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
67 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
68 mips_ejtag_drscan_32(ejtag_info, data);
70 /* Clear DMA & Check DERR */
71 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
72 ejtag_ctrl = ejtag_info->ejtag_ctrl;
73 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
74 if (ejtag_ctrl & EJTAG_CTRL_DERR)
77 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
78 goto begin_ejtag_dma_read;
81 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
82 return ERROR_JTAG_DEVICE_ERROR;
88 static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
92 int retries = RETRY_ATTEMPTS;
94 begin_ejtag_dma_read_h:
98 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
99 mips_ejtag_drscan_32(ejtag_info, &v);
101 /* Initiate DMA Read & set DSTRT */
102 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
103 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
104 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
106 /* Wait for DSTRT to Clear */
108 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
109 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
110 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
113 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
114 mips_ejtag_drscan_32(ejtag_info, &v);
116 /* Clear DMA & Check DERR */
117 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
118 ejtag_ctrl = ejtag_info->ejtag_ctrl;
119 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
120 if (ejtag_ctrl & EJTAG_CTRL_DERR)
123 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
124 goto begin_ejtag_dma_read_h;
127 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
128 return ERROR_JTAG_DEVICE_ERROR;
131 /* Handle the bigendian/littleendian */
133 *data = (v >> 16) & 0xffff;
135 *data = (v & 0x0000ffff);
140 static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
144 int retries = RETRY_ATTEMPTS;
146 begin_ejtag_dma_read_b:
150 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
151 mips_ejtag_drscan_32(ejtag_info, &v);
153 /* Initiate DMA Read & set DSTRT */
154 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
155 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
156 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
158 /* Wait for DSTRT to Clear */
160 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
161 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
162 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
165 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
166 mips_ejtag_drscan_32(ejtag_info, &v);
168 /* Clear DMA & Check DERR */
169 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
170 ejtag_ctrl = ejtag_info->ejtag_ctrl;
171 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
172 if (ejtag_ctrl & EJTAG_CTRL_DERR)
175 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
176 goto begin_ejtag_dma_read_b;
179 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
180 return ERROR_JTAG_DEVICE_ERROR;
183 /* Handle the bigendian/littleendian */
184 switch (addr & 0x3) {
189 *data = (v >> 8) & 0xff;
192 *data = (v >> 16) & 0xff;
195 *data = (v >> 24) & 0xff;
202 static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
206 int retries = RETRY_ATTEMPTS;
208 begin_ejtag_dma_write:
212 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
213 mips_ejtag_drscan_32(ejtag_info, &v);
217 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
218 mips_ejtag_drscan_32(ejtag_info, &v);
220 /* Initiate DMA Write & set DSTRT */
221 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
222 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
223 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
225 /* Wait for DSTRT to Clear */
227 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
228 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
229 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
231 /* Clear DMA & Check DERR */
232 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
233 ejtag_ctrl = ejtag_info->ejtag_ctrl;
234 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
235 if (ejtag_ctrl & EJTAG_CTRL_DERR)
238 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
239 goto begin_ejtag_dma_write;
242 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
243 return ERROR_JTAG_DEVICE_ERROR;
249 static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
253 int retries = RETRY_ATTEMPTS;
255 /* Handle the bigendian/littleendian */
259 begin_ejtag_dma_write_h:
263 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
264 mips_ejtag_drscan_32(ejtag_info, &v);
268 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
269 mips_ejtag_drscan_32(ejtag_info, &v);
271 /* Initiate DMA Write & set DSTRT */
272 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
273 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
274 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
276 /* Wait for DSTRT to Clear */
278 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
279 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
280 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
282 /* Clear DMA & Check DERR */
283 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
284 ejtag_ctrl = ejtag_info->ejtag_ctrl;
285 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
286 if (ejtag_ctrl & EJTAG_CTRL_DERR)
289 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
290 goto begin_ejtag_dma_write_h;
293 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
294 return ERROR_JTAG_DEVICE_ERROR;
300 static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
304 int retries = RETRY_ATTEMPTS;
306 /* Handle the bigendian/littleendian */
311 begin_ejtag_dma_write_b:
315 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
316 mips_ejtag_drscan_32(ejtag_info, &v);
320 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
321 mips_ejtag_drscan_32(ejtag_info, &v);
323 /* Initiate DMA Write & set DSTRT */
324 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
325 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
326 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
328 /* Wait for DSTRT to Clear */
330 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
331 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
332 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
334 /* Clear DMA & Check DERR */
335 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
336 ejtag_ctrl = ejtag_info->ejtag_ctrl;
337 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
338 if (ejtag_ctrl & EJTAG_CTRL_DERR)
341 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
342 goto begin_ejtag_dma_write_b;
345 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
346 return ERROR_JTAG_DEVICE_ERROR;
352 int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
357 return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
359 return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
361 return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
367 int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
372 for (i=0; i<count; i++) {
373 if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
380 int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
385 for (i=0; i<count; i++) {
386 if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
393 int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
398 for (i=0; i<count; i++) {
399 if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
406 int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
411 return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
413 return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
415 return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
421 int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
426 for (i=0; i<count; i++) {
427 if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
434 int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
439 for (i=0; i<count; i++) {
440 if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
447 int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
452 for (i=0; i<count; i++) {
453 if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)