1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
29 #include "target_type.h"
34 /* forward declarations */
35 int mips_m4k_poll(target_t *target);
36 int mips_m4k_halt(struct target_s *target);
37 int mips_m4k_soft_reset_halt(struct target_s *target);
38 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
39 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
40 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
41 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
42 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
43 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
44 int mips_m4k_quit(void);
45 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
47 int mips_m4k_examine(struct target_s *target);
48 int mips_m4k_assert_reset(target_t *target);
49 int mips_m4k_deassert_reset(target_t *target);
50 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
52 target_type_t mips_m4k_target =
56 .poll = mips_m4k_poll,
57 .arch_state = mips32_arch_state,
59 .target_request_data = NULL,
61 .halt = mips_m4k_halt,
62 .resume = mips_m4k_resume,
63 .step = mips_m4k_step,
65 .assert_reset = mips_m4k_assert_reset,
66 .deassert_reset = mips_m4k_deassert_reset,
67 .soft_reset_halt = mips_m4k_soft_reset_halt,
69 .get_gdb_reg_list = mips32_get_gdb_reg_list,
71 .read_memory = mips_m4k_read_memory,
72 .write_memory = mips_m4k_write_memory,
73 .bulk_write_memory = mips_m4k_bulk_write_memory,
74 .checksum_memory = mips_m4k_checksum_memory,
75 .blank_check_memory = NULL,
77 .run_algorithm = mips32_run_algorithm,
79 .add_breakpoint = mips_m4k_add_breakpoint,
80 .remove_breakpoint = mips_m4k_remove_breakpoint,
81 .add_watchpoint = mips_m4k_add_watchpoint,
82 .remove_watchpoint = mips_m4k_remove_watchpoint,
84 .register_commands = mips_m4k_register_commands,
85 .target_create = mips_m4k_target_create,
86 .init_target = mips_m4k_init_target,
87 .examine = mips_m4k_examine,
91 int mips_m4k_examine_debug_reason(target_t *target)
96 if ((target->debug_reason != DBG_REASON_DBGRQ)
97 && (target->debug_reason != DBG_REASON_SINGLESTEP))
99 /* get info about inst breakpoint support */
100 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
102 if (break_status & 0x1f)
104 /* we have halted on a breakpoint */
105 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
107 target->debug_reason = DBG_REASON_BREAKPOINT;
110 /* get info about data breakpoint support */
111 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
113 if (break_status & 0x1f)
115 /* we have halted on a breakpoint */
116 if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
118 target->debug_reason = DBG_REASON_WATCHPOINT;
125 int mips_m4k_debug_entry(target_t *target)
127 mips32_common_t *mips32 = target->arch_info;
128 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
131 /* read debug register */
132 mips_ejtag_read_debug(ejtag_info, &debug_reg);
134 /* make sure break uit configured */
135 mips32_configure_break_unit(target);
137 /* attempt to find halt reason */
138 mips_m4k_examine_debug_reason(target);
140 /* clear single step if active */
141 if (debug_reg & EJTAG_DEBUG_DSS)
143 /* stopped due to single step - clear step bit */
144 mips_ejtag_config_step(ejtag_info, 0);
147 mips32_save_context(target);
149 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
150 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
151 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
156 int mips_m4k_poll(target_t *target)
159 mips32_common_t *mips32 = target->arch_info;
160 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
161 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
163 /* read ejtag control reg */
164 jtag_add_end_state(TAP_IDLE);
165 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
166 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
168 /* clear this bit before handling polling
169 * as after reset registers will read zero */
170 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
172 /* we have detected a reset, clear flag
173 * otherwise ejtag will not work */
174 jtag_add_end_state(TAP_IDLE);
175 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
177 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
178 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
179 LOG_DEBUG("Reset Detected");
182 /* check for processor halted */
183 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
185 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
187 jtag_add_end_state(TAP_IDLE);
188 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
190 target->state = TARGET_HALTED;
192 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
195 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
197 else if (target->state == TARGET_DEBUG_RUNNING)
199 target->state = TARGET_HALTED;
201 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
204 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
209 target->state = TARGET_RUNNING;
212 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
217 int mips_m4k_halt(struct target_s *target)
219 mips32_common_t *mips32 = target->arch_info;
220 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
222 LOG_DEBUG("target->state: %s",
223 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
225 if (target->state == TARGET_HALTED)
227 LOG_DEBUG("target was already halted");
231 if (target->state == TARGET_UNKNOWN)
233 LOG_WARNING("target was in unknown state when halt was requested");
236 if (target->state == TARGET_RESET)
238 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
240 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
241 return ERROR_TARGET_FAILURE;
245 /* we came here in a reset_halt or reset_init sequence
246 * debug entry was already prepared in mips32_prepare_reset_halt()
248 target->debug_reason = DBG_REASON_DBGRQ;
254 /* break processor */
255 mips_ejtag_enter_debug(ejtag_info);
257 target->debug_reason = DBG_REASON_DBGRQ;
262 int mips_m4k_assert_reset(target_t *target)
264 mips32_common_t *mips32 = target->arch_info;
265 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
267 LOG_DEBUG("target->state: %s",
268 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
270 if (!(jtag_reset_config & RESET_HAS_SRST))
272 LOG_ERROR("Can't assert SRST");
276 if (target->reset_halt)
278 /* use hardware to catch reset */
279 jtag_add_end_state(TAP_IDLE);
280 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
284 jtag_add_end_state(TAP_IDLE);
285 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
288 if (strcmp(target->variant, "ejtag_srst") == 0)
290 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
291 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
292 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
293 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
297 /* here we should issue a srst only, but we may have to assert trst as well */
298 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
300 jtag_add_reset(1, 1);
304 jtag_add_reset(0, 1);
308 target->state = TARGET_RESET;
309 jtag_add_sleep(50000);
311 mips32_invalidate_core_regs(target);
313 if (target->reset_halt)
316 if ((retval = target_halt(target))!=ERROR_OK)
323 int mips_m4k_deassert_reset(target_t *target)
325 LOG_DEBUG("target->state: %s",
326 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
328 /* deassert reset lines */
329 jtag_add_reset(0, 0);
334 int mips_m4k_soft_reset_halt(struct target_s *target)
340 int mips_m4k_single_step_core(target_t *target)
342 mips32_common_t *mips32 = target->arch_info;
343 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
345 /* configure single step mode */
346 mips_ejtag_config_step(ejtag_info, 1);
348 /* disable interrupts while stepping */
349 mips32_enable_interrupts(target, 0);
351 /* exit debug mode */
352 mips_ejtag_exit_debug(ejtag_info);
354 mips_m4k_debug_entry(target);
359 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
361 mips32_common_t *mips32 = target->arch_info;
362 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
363 breakpoint_t *breakpoint = NULL;
366 if (target->state != TARGET_HALTED)
368 LOG_WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED;
372 if (!debug_execution)
374 target_free_all_working_areas(target);
375 mips_m4k_enable_breakpoints(target);
376 mips_m4k_enable_watchpoints(target);
379 /* current = 1: continue on current pc, otherwise continue at <address> */
382 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
383 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
384 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
387 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
389 mips32_restore_context(target);
391 /* the front-end may request us not to handle breakpoints */
392 if (handle_breakpoints)
394 /* Single step past breakpoint at current address */
395 if ((breakpoint = breakpoint_find(target, resume_pc)))
397 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
398 mips_m4k_unset_breakpoint(target, breakpoint);
399 mips_m4k_single_step_core(target);
400 mips_m4k_set_breakpoint(target, breakpoint);
404 /* enable interrupts if we are running */
405 mips32_enable_interrupts(target, !debug_execution);
407 /* exit debug mode */
408 mips_ejtag_exit_debug(ejtag_info);
409 target->debug_reason = DBG_REASON_NOTHALTED;
411 /* registers are now invalid */
412 mips32_invalidate_core_regs(target);
414 if (!debug_execution)
416 target->state = TARGET_RUNNING;
417 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
418 LOG_DEBUG("target resumed at 0x%x", resume_pc);
422 target->state = TARGET_DEBUG_RUNNING;
423 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
424 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
430 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
432 /* get pointers to arch-specific information */
433 mips32_common_t *mips32 = target->arch_info;
434 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
435 breakpoint_t *breakpoint = NULL;
437 if (target->state != TARGET_HALTED)
439 LOG_WARNING("target not halted");
440 return ERROR_TARGET_NOT_HALTED;
443 /* current = 1: continue on current pc, otherwise continue at <address> */
445 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
447 /* the front-end may request us not to handle breakpoints */
448 if (handle_breakpoints)
449 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
450 mips_m4k_unset_breakpoint(target, breakpoint);
452 /* restore context */
453 mips32_restore_context(target);
455 /* configure single step mode */
456 mips_ejtag_config_step(ejtag_info, 1);
458 target->debug_reason = DBG_REASON_SINGLESTEP;
460 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
462 /* disable interrupts while stepping */
463 mips32_enable_interrupts(target, 0);
465 /* exit debug mode */
466 mips_ejtag_exit_debug(ejtag_info);
468 /* registers are now invalid */
469 mips32_invalidate_core_regs(target);
472 mips_m4k_set_breakpoint(target, breakpoint);
474 LOG_DEBUG("target stepped ");
476 mips_m4k_debug_entry(target);
477 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
482 void mips_m4k_enable_breakpoints(struct target_s *target)
484 breakpoint_t *breakpoint = target->breakpoints;
486 /* set any pending breakpoints */
489 if (breakpoint->set == 0)
490 mips_m4k_set_breakpoint(target, breakpoint);
491 breakpoint = breakpoint->next;
495 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
497 mips32_common_t *mips32 = target->arch_info;
498 mips32_comparator_t * comparator_list = mips32->inst_break_list;
503 LOG_WARNING("breakpoint already set");
507 if (breakpoint->type == BKPT_HARD)
511 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
513 if (bp_num >= mips32->num_inst_bpoints)
515 LOG_DEBUG("ERROR Can not find free FP Comparator");
516 LOG_WARNING("ERROR Can not find free FP Comparator");
519 breakpoint->set = bp_num + 1;
520 comparator_list[bp_num].used = 1;
521 comparator_list[bp_num].bp_value = breakpoint->address;
522 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
523 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
524 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
525 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
527 else if (breakpoint->type == BKPT_SOFT)
529 if (breakpoint->length == 4)
531 u32 verify = 0xffffffff;
533 if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
537 if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
542 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
546 if (verify != MIPS32_SDBBP)
548 LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
556 if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
560 if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
565 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
569 if (verify != MIPS16_SDBBP)
571 LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
576 breakpoint->set = 20; /* Any nice value but 0 */
582 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
584 /* get pointers to arch-specific information */
585 mips32_common_t *mips32 = target->arch_info;
586 mips32_comparator_t * comparator_list = mips32->inst_break_list;
589 if (!breakpoint->set)
591 LOG_WARNING("breakpoint not set");
595 if (breakpoint->type == BKPT_HARD)
597 int bp_num = breakpoint->set - 1;
598 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
600 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
603 comparator_list[bp_num].used = 0;
604 comparator_list[bp_num].bp_value = 0;
605 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
609 /* restore original instruction (kept in target endianness) */
610 if (breakpoint->length == 4)
614 /* check that user program has not modified breakpoint instruction */
615 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
619 if (current_instr == MIPS32_SDBBP)
621 if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
631 /* check that user program has not modified breakpoint instruction */
632 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
637 if (current_instr == MIPS16_SDBBP)
639 if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
651 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
653 mips32_common_t *mips32 = target->arch_info;
655 if (breakpoint->type == BKPT_HARD)
657 if (mips32->num_inst_bpoints_avail < 1)
659 LOG_INFO("no hardware breakpoint available");
660 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
663 mips32->num_inst_bpoints_avail--;
666 mips_m4k_set_breakpoint(target, breakpoint);
671 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
673 /* get pointers to arch-specific information */
674 mips32_common_t *mips32 = target->arch_info;
676 if (target->state != TARGET_HALTED)
678 LOG_WARNING("target not halted");
679 return ERROR_TARGET_NOT_HALTED;
684 mips_m4k_unset_breakpoint(target, breakpoint);
687 if (breakpoint->type == BKPT_HARD)
688 mips32->num_inst_bpoints_avail++;
693 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
699 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
705 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
711 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
717 void mips_m4k_enable_watchpoints(struct target_s *target)
719 watchpoint_t *watchpoint = target->watchpoints;
721 /* set any pending watchpoints */
724 if (watchpoint->set == 0)
725 mips_m4k_set_watchpoint(target, watchpoint);
726 watchpoint = watchpoint->next;
730 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
732 mips32_common_t *mips32 = target->arch_info;
733 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
735 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
737 if (target->state != TARGET_HALTED)
739 LOG_WARNING("target not halted");
740 return ERROR_TARGET_NOT_HALTED;
743 /* sanitize arguments */
744 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
745 return ERROR_INVALID_ARGUMENTS;
747 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
748 return ERROR_TARGET_UNALIGNED_ACCESS;
755 /* if noDMA off, use DMAACC mode for memory read */
756 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
757 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
759 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
761 LOG_ERROR("BUG: we shouldn't get here");
769 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
771 mips32_common_t *mips32 = target->arch_info;
772 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
774 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
776 if (target->state != TARGET_HALTED)
778 LOG_WARNING("target not halted");
779 return ERROR_TARGET_NOT_HALTED;
782 /* sanitize arguments */
783 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
784 return ERROR_INVALID_ARGUMENTS;
786 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
787 return ERROR_TARGET_UNALIGNED_ACCESS;
794 /* if noDMA off, use DMAACC mode for memory write */
795 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
796 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
798 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
801 LOG_ERROR("BUG: we shouldn't get here");
809 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
813 retval = mips32_register_commands(cmd_ctx);
817 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
819 mips32_build_reg_cache(target);
824 int mips_m4k_quit(void)
829 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
831 mips32_common_t *mips32 = &mips_m4k->mips32_common;
833 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
835 /* initialize mips4k specific info */
836 mips32_init_arch_info(target, mips32, tap);
837 mips32->arch_info = mips_m4k;
842 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
844 mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
846 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
851 int mips_m4k_examine(struct target_s *target)
854 mips32_common_t *mips32 = target->arch_info;
855 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
858 if (!target_was_examined(target))
860 mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
861 ejtag_info->idcode = idcode;
863 if (((idcode >> 1) & 0x7FF) == 0x29)
865 /* we are using a pic32mx so select ejtag port
866 * as it is not selected by default */
867 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
868 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
872 /* init rest of ejtag interface */
873 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
876 if ((retval = mips32_examine(target)) != ERROR_OK)
882 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
884 return mips_m4k_write_memory(target, address, 4, count, buffer);
887 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
889 return ERROR_FAIL; /* use bulk read method */