1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
37 /* forward declarations */
38 int mips_m4k_poll(target_t *target);
39 int mips_m4k_halt(struct target_s *target);
40 int mips_m4k_soft_reset_halt(struct target_s *target);
41 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
42 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
43 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
44 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
45 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
46 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
47 int mips_m4k_quit(void);
48 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
50 int mips_m4k_examine(struct target_s *target);
51 int mips_m4k_assert_reset(target_t *target);
52 int mips_m4k_deassert_reset(target_t *target);
54 target_type_t mips_m4k_target =
58 .poll = mips_m4k_poll,
59 .arch_state = mips32_arch_state,
61 .target_request_data = NULL,
63 .halt = mips_m4k_halt,
64 .resume = mips_m4k_resume,
65 .step = mips_m4k_step,
67 .assert_reset = mips_m4k_assert_reset,
68 .deassert_reset = mips_m4k_deassert_reset,
69 .soft_reset_halt = mips_m4k_soft_reset_halt,
71 .get_gdb_reg_list = mips32_get_gdb_reg_list,
73 .read_memory = mips_m4k_read_memory,
74 .write_memory = mips_m4k_write_memory,
75 .bulk_write_memory = mips_m4k_bulk_write_memory,
76 .checksum_memory = NULL,
77 .blank_check_memory = NULL,
79 .run_algorithm = mips32_run_algorithm,
81 .add_breakpoint = mips_m4k_add_breakpoint,
82 .remove_breakpoint = mips_m4k_remove_breakpoint,
83 .add_watchpoint = mips_m4k_add_watchpoint,
84 .remove_watchpoint = mips_m4k_remove_watchpoint,
86 .register_commands = mips_m4k_register_commands,
87 .target_create = mips_m4k_target_create,
88 .init_target = mips_m4k_init_target,
89 .examine = mips_m4k_examine,
93 int mips_m4k_examine_debug_reason(target_t *target)
98 if ((target->debug_reason != DBG_REASON_DBGRQ)
99 && (target->debug_reason != DBG_REASON_SINGLESTEP))
101 /* get info about inst breakpoint support */
102 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
104 if (break_status & 0x1f)
106 /* we have halted on a breakpoint */
107 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
109 target->debug_reason = DBG_REASON_BREAKPOINT;
112 /* get info about data breakpoint support */
113 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
115 if (break_status & 0x1f)
117 /* we have halted on a breakpoint */
118 if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
120 target->debug_reason = DBG_REASON_WATCHPOINT;
127 int mips_m4k_debug_entry(target_t *target)
129 mips32_common_t *mips32 = target->arch_info;
130 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
133 /* read debug register */
134 mips_ejtag_read_debug(ejtag_info, &debug_reg);
136 /* make sure break uit configured */
137 mips32_configure_break_unit(target);
139 /* attempt to find halt reason */
140 mips_m4k_examine_debug_reason(target);
142 /* clear single step if active */
143 if (debug_reg & EJTAG_DEBUG_DSS)
145 /* stopped due to single step - clear step bit */
146 mips_ejtag_config_step(ejtag_info, 0);
149 mips32_save_context(target);
151 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
152 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
153 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
158 int mips_m4k_poll(target_t *target)
161 mips32_common_t *mips32 = target->arch_info;
162 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
163 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
165 /* read ejtag control reg */
166 jtag_add_end_state(TAP_RTI);
167 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
168 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
170 /* clear this bit before handling polling
171 * as after reset registers will read zero */
172 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
174 /* we have detected a reset, clear flag
175 * otherwise ejtag will not work */
176 jtag_add_end_state(TAP_RTI);
177 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
179 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
180 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
181 LOG_DEBUG("Reset Detected");
184 /* check for processor halted */
185 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
187 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
189 jtag_add_end_state(TAP_RTI);
190 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
192 target->state = TARGET_HALTED;
194 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
197 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
199 else if (target->state == TARGET_DEBUG_RUNNING)
201 target->state = TARGET_HALTED;
203 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
206 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
211 target->state = TARGET_RUNNING;
214 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
219 int mips_m4k_halt(struct target_s *target)
221 mips32_common_t *mips32 = target->arch_info;
222 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
224 LOG_DEBUG("target->state: %s",
225 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
227 if (target->state == TARGET_HALTED)
229 LOG_DEBUG("target was already halted");
233 if (target->state == TARGET_UNKNOWN)
235 LOG_WARNING("target was in unknown state when halt was requested");
238 if (target->state == TARGET_RESET)
240 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
242 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
243 return ERROR_TARGET_FAILURE;
247 /* we came here in a reset_halt or reset_init sequence
248 * debug entry was already prepared in mips32_prepare_reset_halt()
250 target->debug_reason = DBG_REASON_DBGRQ;
256 /* break processor */
257 mips_ejtag_enter_debug(ejtag_info);
259 target->debug_reason = DBG_REASON_DBGRQ;
264 int mips_m4k_assert_reset(target_t *target)
266 mips32_common_t *mips32 = target->arch_info;
267 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
268 mips_m4k_common_t *mips_m4k = mips32->arch_info;
270 LOG_DEBUG("target->state: %s",
271 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
273 if (!(jtag_reset_config & RESET_HAS_SRST))
275 LOG_ERROR("Can't assert SRST");
279 if (target->reset_halt)
281 /* use hardware to catch reset */
282 jtag_add_end_state(TAP_RTI);
283 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
287 jtag_add_end_state(TAP_RTI);
288 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
291 if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
293 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
294 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
295 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
296 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
300 /* here we should issue a srst only, but we may have to assert trst as well */
301 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
303 jtag_add_reset(1, 1);
307 jtag_add_reset(0, 1);
311 target->state = TARGET_RESET;
312 jtag_add_sleep(50000);
314 mips32_invalidate_core_regs(target);
316 if (target->reset_halt)
319 if ((retval = target_halt(target))!=ERROR_OK)
326 int mips_m4k_deassert_reset(target_t *target)
328 LOG_DEBUG("target->state: %s",
329 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
331 /* deassert reset lines */
332 jtag_add_reset(0, 0);
337 int mips_m4k_soft_reset_halt(struct target_s *target)
343 int mips_m4k_single_step_core(target_t *target)
345 mips32_common_t *mips32 = target->arch_info;
346 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
348 /* configure single step mode */
349 mips_ejtag_config_step(ejtag_info, 1);
351 /* exit debug mode */
352 mips_ejtag_exit_debug(ejtag_info, 1);
354 mips_m4k_debug_entry(target);
359 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
361 mips32_common_t *mips32 = target->arch_info;
362 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
363 breakpoint_t *breakpoint = NULL;
366 if (target->state != TARGET_HALTED)
368 LOG_WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED;
372 if (!debug_execution)
374 target_free_all_working_areas(target);
375 mips_m4k_enable_breakpoints(target);
376 mips_m4k_enable_watchpoints(target);
379 /* current = 1: continue on current pc, otherwise continue at <address> */
382 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
383 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
384 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
387 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
389 mips32_restore_context(target);
391 /* the front-end may request us not to handle breakpoints */
392 if (handle_breakpoints)
394 /* Single step past breakpoint at current address */
395 if ((breakpoint = breakpoint_find(target, resume_pc)))
397 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
398 mips_m4k_unset_breakpoint(target, breakpoint);
399 mips_m4k_single_step_core(target);
400 mips_m4k_set_breakpoint(target, breakpoint);
404 /* exit debug mode - enable interrupts if required */
405 mips_ejtag_exit_debug(ejtag_info, !debug_execution);
406 target->debug_reason = DBG_REASON_NOTHALTED;
408 /* registers are now invalid */
409 mips32_invalidate_core_regs(target);
411 if (!debug_execution)
413 target->state = TARGET_RUNNING;
414 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
415 LOG_DEBUG("target resumed at 0x%x", resume_pc);
419 target->state = TARGET_DEBUG_RUNNING;
420 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
421 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
427 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
429 /* get pointers to arch-specific information */
430 mips32_common_t *mips32 = target->arch_info;
431 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
432 breakpoint_t *breakpoint = NULL;
434 if (target->state != TARGET_HALTED)
436 LOG_WARNING("target not halted");
437 return ERROR_TARGET_NOT_HALTED;
440 /* current = 1: continue on current pc, otherwise continue at <address> */
442 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
444 /* the front-end may request us not to handle breakpoints */
445 if (handle_breakpoints)
446 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
447 mips_m4k_unset_breakpoint(target, breakpoint);
449 /* restore context */
450 mips32_restore_context(target);
452 /* configure single step mode */
453 mips_ejtag_config_step(ejtag_info, 1);
455 target->debug_reason = DBG_REASON_SINGLESTEP;
457 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
459 /* exit debug mode */
460 mips_ejtag_exit_debug(ejtag_info, 1);
462 /* registers are now invalid */
463 mips32_invalidate_core_regs(target);
466 mips_m4k_set_breakpoint(target, breakpoint);
468 LOG_DEBUG("target stepped ");
470 mips_m4k_debug_entry(target);
471 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
476 void mips_m4k_enable_breakpoints(struct target_s *target)
478 breakpoint_t *breakpoint = target->breakpoints;
480 /* set any pending breakpoints */
483 if (breakpoint->set == 0)
484 mips_m4k_set_breakpoint(target, breakpoint);
485 breakpoint = breakpoint->next;
489 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
491 mips32_common_t *mips32 = target->arch_info;
492 mips32_comparator_t * comparator_list = mips32->inst_break_list;
496 LOG_WARNING("breakpoint already set");
500 if (breakpoint->type == BKPT_HARD)
504 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
506 if (bp_num >= mips32->num_inst_bpoints)
508 LOG_DEBUG("ERROR Can not find free FP Comparator");
509 LOG_WARNING("ERROR Can not find free FP Comparator");
512 breakpoint->set = bp_num + 1;
513 comparator_list[bp_num].used = 1;
514 comparator_list[bp_num].bp_value = breakpoint->address;
515 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
516 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
517 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
518 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
520 else if (breakpoint->type == BKPT_SOFT)
528 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
530 /* get pointers to arch-specific information */
531 mips32_common_t *mips32 = target->arch_info;
532 mips32_comparator_t * comparator_list = mips32->inst_break_list;
534 if (!breakpoint->set)
536 LOG_WARNING("breakpoint not set");
540 if (breakpoint->type == BKPT_HARD)
542 int bp_num = breakpoint->set - 1;
543 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
545 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
548 comparator_list[bp_num].used = 0;
549 comparator_list[bp_num].bp_value = 0;
550 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
561 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
563 mips32_common_t *mips32 = target->arch_info;
565 if (mips32->num_inst_bpoints_avail < 1)
567 LOG_INFO("no hardware breakpoint available");
568 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
571 /* default to hardware for now */
572 breakpoint->type = BKPT_HARD;
574 mips32->num_inst_bpoints_avail--;
575 mips_m4k_set_breakpoint(target, breakpoint);
580 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
582 /* get pointers to arch-specific information */
583 mips32_common_t *mips32 = target->arch_info;
585 if (target->state != TARGET_HALTED)
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED;
593 mips_m4k_unset_breakpoint(target, breakpoint);
596 if (breakpoint->type == BKPT_HARD)
597 mips32->num_inst_bpoints_avail++;
602 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
608 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
614 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
620 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
626 void mips_m4k_enable_watchpoints(struct target_s *target)
628 watchpoint_t *watchpoint = target->watchpoints;
630 /* set any pending watchpoints */
633 if (watchpoint->set == 0)
634 mips_m4k_set_watchpoint(target, watchpoint);
635 watchpoint = watchpoint->next;
639 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
641 mips32_common_t *mips32 = target->arch_info;
642 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
644 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
646 if (target->state != TARGET_HALTED)
648 LOG_WARNING("target not halted");
649 return ERROR_TARGET_NOT_HALTED;
652 /* sanitize arguments */
653 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
654 return ERROR_INVALID_ARGUMENTS;
656 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
657 return ERROR_TARGET_UNALIGNED_ACCESS;
664 /* if noDMA off, use DMAACC mode for memory read */
665 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
666 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
668 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
670 LOG_ERROR("BUG: we shouldn't get here");
678 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
680 mips32_common_t *mips32 = target->arch_info;
681 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
683 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
685 if (target->state != TARGET_HALTED)
687 LOG_WARNING("target not halted");
688 return ERROR_TARGET_NOT_HALTED;
691 /* sanitize arguments */
692 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
693 return ERROR_INVALID_ARGUMENTS;
695 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
696 return ERROR_TARGET_UNALIGNED_ACCESS;
703 /* if noDMA off, use DMAACC mode for memory write */
704 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
705 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
707 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
710 LOG_ERROR("BUG: we shouldn't get here");
718 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
722 retval = mips32_register_commands(cmd_ctx);
726 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
728 mips32_build_reg_cache(target);
733 int mips_m4k_quit(void)
738 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
740 mips32_common_t *mips32 = &mips_m4k->mips32_common;
744 mips_m4k->variant = strdup(variant);
748 mips_m4k->variant = strdup("");
751 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
753 /* initialize mips4k specific info */
754 mips32_init_arch_info(target, mips32, tap, variant);
755 mips32->arch_info = mips_m4k;
760 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
762 mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
764 mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
769 int mips_m4k_examine(struct target_s *target)
772 mips32_common_t *mips32 = target->arch_info;
773 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
776 if (!target->type->examined)
778 mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
780 if (((idcode >> 1) & 0x7FF) == 0x29)
782 /* we are using a pic32mx so select ejtag port
783 * as it is not selected by default */
784 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
785 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
789 /* init rest of ejtag interface */
790 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
793 if ((retval = mips32_examine(target)) != ERROR_OK)
799 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
801 return mips_m4k_write_memory(target, address, 4, count, buffer);