1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/time_support.h>
26 #include <helper/binarybuffer.h>
27 #include "breakpoints.h"
28 #include "nds32_insn.h"
29 #include "nds32_reg.h"
30 #include "nds32_edm.h"
31 #include "nds32_cmd.h"
33 #include "nds32_aice.h"
34 #include "target_type.h"
36 static int nds32_v2_register_mapping(struct nds32 *nds32, int reg_no)
38 uint32_t max_level = nds32->max_interrupt_level;
39 uint32_t cur_level = nds32->current_interrupt_level;
41 if ((1 <= cur_level) && (cur_level < max_level)) {
43 LOG_DEBUG("Map PSW to IPSW");
45 } else if (PC == reg_no) {
46 LOG_DEBUG("Map PC to IPC");
49 } else if ((2 <= cur_level) && (cur_level < max_level)) {
51 LOG_DEBUG("Mapping P0 to P_P0");
53 } else if (R27 == reg_no) {
54 LOG_DEBUG("Mapping P1 to P_P1");
56 } else if (IR1 == reg_no) {
57 LOG_DEBUG("Mapping IPSW to P_IPSW");
59 } else if (IR4 == reg_no) {
60 LOG_DEBUG("Mapping EVA to P_EVA");
62 } else if (IR6 == reg_no) {
63 LOG_DEBUG("Mapping ITYPE to P_ITYPE");
65 } else if (IR9 == reg_no) {
66 LOG_DEBUG("Mapping IPC to P_IPC");
69 } else if (cur_level == max_level) {
71 LOG_DEBUG("Mapping PC to O_IPC");
79 static int nds32_v2_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
82 struct aice_port_s *aice = target_to_aice(nds32->target);
84 aice_read_register(aice, IR6, &val_itype);
86 *reason = val_itype & 0x0F;
91 static int nds32_v2_activate_hardware_breakpoint(struct target *target)
93 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
94 struct aice_port_s *aice = target_to_aice(target);
95 struct breakpoint *bp;
96 int32_t hbr_index = 0;
98 for (bp = target->breakpoints; bp; bp = bp->next) {
99 if (bp->type == BKPT_SOFT) {
100 /* already set at nds32_v2_add_breakpoint() */
102 } else if (bp->type == BKPT_HARD) {
104 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
106 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
108 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
110 if (nds32_v2->nds32.memory.address_translation)
111 /* enable breakpoint (virtual address) */
112 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
114 /* enable breakpoint (physical address) */
115 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
117 LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
129 static int nds32_v2_deactivate_hardware_breakpoint(struct target *target)
131 struct aice_port_s *aice = target_to_aice(target);
132 struct breakpoint *bp;
133 int32_t hbr_index = 0;
135 for (bp = target->breakpoints; bp; bp = bp->next) {
136 if (bp->type == BKPT_SOFT)
138 else if (bp->type == BKPT_HARD)
139 /* disable breakpoint */
140 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
144 LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
153 static int nds32_v2_activate_hardware_watchpoint(struct target *target)
155 struct aice_port_s *aice = target_to_aice(target);
156 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
157 struct watchpoint *wp;
158 int32_t wp_num = nds32_v2->next_hbr_index;
159 uint32_t wp_config = 0;
161 for (wp = target->watchpoints; wp; wp = wp->next) {
164 wp->mask = wp->length - 1;
165 if ((wp->address % wp->length) != 0)
166 wp->mask = (wp->mask << 1) + 1;
168 if (wp->rw == WPT_READ)
170 else if (wp->rw == WPT_WRITE)
172 else if (wp->rw == WPT_ACCESS)
175 /* set/unset physical address bit of BPCn according to PSW.DT */
176 if (nds32_v2->nds32.memory.address_translation == false)
180 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
181 wp->address - (wp->address % wp->length));
183 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
184 /* enable watchpoint */
185 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
187 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
189 LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32, wp_num,
190 wp->address, wp->mask);
197 static int nds32_v2_deactivate_hardware_watchpoint(struct target *target)
199 struct aice_port_s *aice = target_to_aice(target);
200 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
201 int32_t wp_num = nds32_v2->next_hbr_index;
202 struct watchpoint *wp;
204 for (wp = target->watchpoints; wp; wp = wp->next) {
206 /* disable watchpoint */
207 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
209 LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
210 wp_num, wp->address, wp->mask);
216 static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
218 struct nds32 *nds32 = &(nds32_v2->nds32);
219 struct aice_port_s *aice = target_to_aice(nds32->target);
223 uint32_t modified_psw;
225 /* Save interrupt level */
226 aice_read_register(aice, IR0, &val_ir0); /* get $IR0 directly */
229 nds32_v2->backup_ir0 = val_ir0;
231 nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
233 if (nds32_reach_max_interrupt_level(nds32)) {
234 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
235 nds32->current_interrupt_level);
237 /* decrease interrupt level */
238 modified_psw = val_ir0 - 0x2;
240 /* disable GIE, IT, DT, HSS */
241 modified_psw &= (~0x8C1);
243 aice_write_register(aice, IR0, modified_psw);
248 /* There is a case that single step also trigger another interrupt,
249 then HSS bit in psw(ir0) will push to ipsw(ir1).
250 Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2
251 Therefore, HSS bit in p_ipsw(ir2) also need clear.
253 Only update $ir2 as current interrupt level is 2, because $ir2 will be random
254 value if the target never reaches interrupt level 2. */
255 if ((nds32->max_interrupt_level == 3) && (nds32->current_interrupt_level == 2)) {
256 aice_read_register(aice, IR2, &val_ir2); /* get $IR2 directly */
257 val_ir2 &= ~(0x01 << 11);
258 aice_write_register(aice, IR2, val_ir2);
261 /* get origianl DT bit and set to current state let debugger has same memory view
262 PSW.IT MUST be turned off. Otherwise, DIM could not operate normally. */
263 aice_read_register(aice, IR1, &val_ir1);
264 modified_psw = val_ir0 | (val_ir1 & 0x80);
265 aice_write_register(aice, IR0, modified_psw);
270 static int nds32_v2_restore_interrupt_stack(struct nds32_v2_common *nds32_v2)
272 struct nds32 *nds32 = &(nds32_v2->nds32);
273 struct aice_port_s *aice = target_to_aice(nds32->target);
275 /* restore origin $IR0 */
276 aice_write_register(aice, IR0, nds32_v2->backup_ir0);
282 * Save processor state. This is called after a HALT instruction
283 * succeeds, and on other occasions the processor enters debug mode
284 * (breakpoint, watchpoint, etc).
286 static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
288 LOG_DEBUG("nds32_v2_debug_entry");
290 if (nds32->virtual_hosting)
291 LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
292 "under V1/V2 architecture. -->");
294 enum target_state backup_state = nds32->target->state;
295 nds32->target->state = TARGET_HALTED;
297 if (nds32->init_arch_info_after_halted == false) {
298 /* init architecture info according to config registers */
299 CHECK_RETVAL(nds32_config(nds32));
301 nds32->init_arch_info_after_halted = true;
304 /* REVISIT entire cache should already be invalid !!! */
305 register_cache_invalidate(nds32->core_cache);
307 /* deactivate all hardware breakpoints */
308 CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
310 if (enable_watchpoint)
311 CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
313 if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
314 nds32->target->state = backup_state;
316 /* re-activate all hardware breakpoints & watchpoints */
317 CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
319 if (enable_watchpoint) {
320 /* activate all watchpoints */
321 CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
327 /* check interrupt level before .full_context(), because
328 * get_mapped_reg() in nds32_full_context() needs current_interrupt_level
330 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
331 nds32_v2_check_interrupt_stack(nds32_v2);
333 /* Save registers. */
334 nds32_full_context(nds32);
339 /* target request support */
340 static int nds32_v2_target_request_data(struct target *target,
341 uint32_t size, uint8_t *buffer)
343 /* AndesCore could use DTR register to communicate with OpenOCD
345 * Target data will be put in buffer
346 * The format of DTR is as follow
347 * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
348 * target_req_cmd has three possible values:
349 * TARGET_REQ_TRACEMSG
350 * TARGET_REQ_DEBUGMSG
351 * TARGET_REQ_DEBUGCHAR
352 * if size == 0, target will call target_asciimsg(),
353 * else call target_hexmsg()
355 LOG_WARNING("Not implemented: %s", __func__);
361 * Restore processor state.
363 static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
365 LOG_DEBUG("nds32_v2_leave_debug_state");
367 struct target *target = nds32->target;
369 /* activate all hardware breakpoints */
370 CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
372 if (enable_watchpoint) {
373 /* activate all watchpoints */
374 CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
377 /* restore interrupt stack */
378 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
379 nds32_v2_restore_interrupt_stack(nds32_v2);
381 /* restore PSW, PC, and R0 ... after flushing any modified
384 CHECK_RETVAL(nds32_restore_context(target));
386 register_cache_invalidate(nds32->core_cache);
391 static int nds32_v2_soft_reset_halt(struct target *target)
394 struct nds32 *nds32 = target_to_nds32(target);
395 struct aice_port_s *aice = target_to_aice(target);
397 aice_assert_srst(aice, AICE_SRST);
399 /* halt core and set pc to 0x0 */
400 int retval = target_halt(target);
401 if (retval != ERROR_OK)
404 /* start fetching from IVB */
406 nds32_get_mapped_reg(nds32, IR3, &value_ir3);
407 nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
412 static int nds32_v2_deassert_reset(struct target *target)
416 CHECK_RETVAL(nds32_poll(target));
418 if (target->state != TARGET_HALTED) {
420 LOG_WARNING("%s: ran after reset and before halt ...",
421 target_name(target));
422 retval = target_halt(target);
423 if (retval != ERROR_OK)
430 static int nds32_v2_checksum_memory(struct target *target,
431 uint32_t address, uint32_t count, uint32_t *checksum)
433 LOG_WARNING("Not implemented: %s", __func__);
438 static int nds32_v2_add_breakpoint(struct target *target,
439 struct breakpoint *breakpoint)
441 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
442 struct nds32 *nds32 = &(nds32_v2->nds32);
445 if (breakpoint->type == BKPT_HARD) {
446 /* check hardware resource */
447 if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
448 LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
449 "breakpoints/watchpoints! The limit of "
450 "combined hardware breakpoints/watchpoints "
451 "is %d. -->", nds32_v2->n_hbr);
452 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
455 /* update next place to put hardware breakpoint */
456 nds32_v2->next_hbr_index++;
458 /* hardware breakpoint insertion occurs before 'continue' actually */
460 } else if (breakpoint->type == BKPT_SOFT) {
461 result = nds32_add_software_breakpoint(target, breakpoint);
462 if (ERROR_OK != result) {
463 /* auto convert to hardware breakpoint if failed */
464 if (nds32->auto_convert_hw_bp) {
465 /* convert to hardware breakpoint */
466 breakpoint->type = BKPT_HARD;
468 return nds32_v2_add_breakpoint(target, breakpoint);
473 } else /* unrecognized breakpoint type */
479 static int nds32_v2_remove_breakpoint(struct target *target,
480 struct breakpoint *breakpoint)
482 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
484 if (breakpoint->type == BKPT_HARD) {
485 if (nds32_v2->next_hbr_index <= 0)
488 /* update next place to put hardware breakpoint */
489 nds32_v2->next_hbr_index--;
491 /* hardware breakpoint removal occurs after 'halted' actually */
493 } else if (breakpoint->type == BKPT_SOFT) {
494 return nds32_remove_software_breakpoint(target, breakpoint);
495 } else /* unrecognized breakpoint type */
501 static int nds32_v2_add_watchpoint(struct target *target,
502 struct watchpoint *watchpoint)
504 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
506 /* check hardware resource */
507 if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
508 LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
509 "breakpoints/watchpoints! The limit of "
510 "combined hardware breakpoints/watchpoints is %d. -->", nds32_v2->n_hbr);
511 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
514 /* update next place to put hardware watchpoint */
515 nds32_v2->next_hbr_index++;
520 static int nds32_v2_remove_watchpoint(struct target *target,
521 struct watchpoint *watchpoint)
523 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
525 if (nds32_v2->next_hbr_index <= 0)
528 /* update next place to put hardware breakpoint */
529 nds32_v2->next_hbr_index--;
534 static int nds32_v2_get_exception_address(struct nds32 *nds32,
535 uint32_t *address, uint32_t reason)
537 struct aice_port_s *aice = target_to_aice(nds32->target);
539 aice_read_register(aice, IR4, address); /* read $EVA directly */
541 /* TODO: hit multiple watchpoints */
547 * find out which watchpoint hits
548 * get exception address and compare the address to watchpoints
550 static int nds32_v2_hit_watchpoint(struct target *target,
551 struct watchpoint **hit_watchpoint)
553 uint32_t exception_address;
554 struct watchpoint *wp;
555 static struct watchpoint scan_all_watchpoint;
556 struct nds32 *nds32 = target_to_nds32(target);
558 scan_all_watchpoint.address = 0;
559 scan_all_watchpoint.rw = WPT_WRITE;
560 scan_all_watchpoint.next = 0;
561 scan_all_watchpoint.unique_id = 0x5CA8;
563 exception_address = nds32->watched_address;
565 if (exception_address == 0) {
566 /* send watch:0 to tell GDB to do software scan for hitting multiple watchpoints */
567 *hit_watchpoint = &scan_all_watchpoint;
571 for (wp = target->watchpoints; wp; wp = wp->next) {
572 if (((exception_address ^ wp->address) & (~wp->mask)) == 0) {
573 /* TODO: dispel false match */
574 *hit_watchpoint = wp;
582 static int nds32_v2_run_algorithm(struct target *target,
584 struct mem_param *mem_params,
586 struct reg_param *reg_params,
587 uint32_t entry_point,
592 LOG_WARNING("Not implemented: %s", __func__);
597 static int nds32_v2_target_create(struct target *target, Jim_Interp *interp)
599 struct nds32_v2_common *nds32_v2;
601 nds32_v2 = calloc(1, sizeof(*nds32_v2));
605 nds32_v2->nds32.register_map = nds32_v2_register_mapping;
606 nds32_v2->nds32.get_debug_reason = nds32_v2_get_debug_reason;
607 nds32_v2->nds32.enter_debug_state = nds32_v2_debug_entry;
608 nds32_v2->nds32.leave_debug_state = nds32_v2_leave_debug_state;
609 nds32_v2->nds32.get_watched_address = nds32_v2_get_exception_address;
611 nds32_init_arch_info(target, &(nds32_v2->nds32));
616 static int nds32_v2_init_target(struct command_context *cmd_ctx,
617 struct target *target)
619 /* Initialize anything we can set up without talking to the target */
621 struct nds32 *nds32 = target_to_nds32(target);
628 /* talk to the target and set things up */
629 static int nds32_v2_examine(struct target *target)
631 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
632 struct nds32 *nds32 = &(nds32_v2->nds32);
633 struct aice_port_s *aice = target_to_aice(target);
635 if (!target_was_examined(target)) {
636 CHECK_RETVAL(nds32_edm_config(nds32));
638 if (nds32->reset_halt_as_examine)
639 CHECK_RETVAL(nds32_reset_halt(nds32));
643 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
645 /* get the number of hardware breakpoints */
646 nds32_v2->n_hbr = (edm_cfg & 0x7) + 1;
648 nds32_v2->next_hbr_index = 0;
650 LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
653 nds32->target->state = TARGET_RUNNING;
654 nds32->target->debug_reason = DBG_REASON_NOTHALTED;
656 target_set_examined(target);
661 static int nds32_v2_translate_address(struct target *target, uint32_t *address)
663 struct nds32 *nds32 = target_to_nds32(target);
664 struct nds32_memory *memory = &(nds32->memory);
665 uint32_t physical_address;
667 /* Following conditions need to do address translation
669 * 2. CPU mode under maximum interrupt level */
670 if ((NDS_MEMORY_ACC_BUS == memory->access_channel) ||
671 ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
672 nds32_reach_max_interrupt_level(nds32))) {
673 if (ERROR_OK == target->type->virt2phys(target, *address, &physical_address))
674 *address = physical_address;
682 static int nds32_v2_read_buffer(struct target *target, uint32_t address,
683 uint32_t size, uint8_t *buffer)
685 struct nds32 *nds32 = target_to_nds32(target);
686 struct nds32_memory *memory = &(nds32->memory);
688 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
689 (target->state != TARGET_HALTED)) {
690 LOG_WARNING("target was not halted");
691 return ERROR_TARGET_NOT_HALTED;
694 /* BUG: If access range crosses multiple pages, the translation will not correct
695 * for second page or so. */
697 nds32_v2_translate_address(target, &address);
699 return nds32_read_buffer(target, address, size, buffer);
702 static int nds32_v2_write_buffer(struct target *target, uint32_t address,
703 uint32_t size, const uint8_t *buffer)
705 struct nds32 *nds32 = target_to_nds32(target);
706 struct nds32_memory *memory = &(nds32->memory);
708 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
709 (target->state != TARGET_HALTED)) {
710 LOG_WARNING("target was not halted");
711 return ERROR_TARGET_NOT_HALTED;
714 /* BUG: If access range crosses multiple pages, the translation will not correct
715 * for second page or so. */
717 nds32_v2_translate_address(target, &address);
719 return nds32_write_buffer(target, address, size, buffer);
722 static int nds32_v2_read_memory(struct target *target, uint32_t address,
723 uint32_t size, uint32_t count, uint8_t *buffer)
725 struct nds32 *nds32 = target_to_nds32(target);
726 struct nds32_memory *memory = &(nds32->memory);
728 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
729 (target->state != TARGET_HALTED)) {
730 LOG_WARNING("target was not halted");
731 return ERROR_TARGET_NOT_HALTED;
734 /* BUG: If access range crosses multiple pages, the translation will not correct
735 * for second page or so. */
737 nds32_v2_translate_address(target, &address);
739 return nds32_read_memory(target, address, size, count, buffer);
742 static int nds32_v2_write_memory(struct target *target, uint32_t address,
743 uint32_t size, uint32_t count, const uint8_t *buffer)
745 struct nds32 *nds32 = target_to_nds32(target);
746 struct nds32_memory *memory = &(nds32->memory);
748 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
749 (target->state != TARGET_HALTED)) {
750 LOG_WARNING("target was not halted");
751 return ERROR_TARGET_NOT_HALTED;
754 /* BUG: If access range crosses multiple pages, the translation will not correct
755 * for second page or so. */
757 nds32_v2_translate_address(target, &address);
759 return nds32_write_memory(target, address, size, count, buffer);
762 /** Holds methods for V2 targets. */
763 struct target_type nds32_v2_target = {
767 .arch_state = nds32_arch_state,
769 .target_request_data = nds32_v2_target_request_data,
772 .resume = nds32_resume,
775 .assert_reset = nds32_assert_reset,
776 .deassert_reset = nds32_v2_deassert_reset,
777 .soft_reset_halt = nds32_v2_soft_reset_halt,
779 /* register access */
780 .get_gdb_reg_list = nds32_get_gdb_reg_list,
783 .read_buffer = nds32_v2_read_buffer,
784 .write_buffer = nds32_v2_write_buffer,
785 .read_memory = nds32_v2_read_memory,
786 .write_memory = nds32_v2_write_memory,
788 .checksum_memory = nds32_v2_checksum_memory,
790 /* breakpoint/watchpoint */
791 .add_breakpoint = nds32_v2_add_breakpoint,
792 .remove_breakpoint = nds32_v2_remove_breakpoint,
793 .add_watchpoint = nds32_v2_add_watchpoint,
794 .remove_watchpoint = nds32_v2_remove_watchpoint,
795 .hit_watchpoint = nds32_v2_hit_watchpoint,
799 .virt2phys = nds32_virtual_to_physical,
800 .read_phys_memory = nds32_read_phys_memory,
801 .write_phys_memory = nds32_write_phys_memory,
803 .run_algorithm = nds32_v2_run_algorithm,
805 .commands = nds32_command_handlers,
806 .target_create = nds32_v2_target_create,
807 .init_target = nds32_v2_init_target,
808 .examine = nds32_v2_examine,