git.sur5r.net Git - openocd/blob - src/target/nds32_v3_common.c

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Andes Technology                                   *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "breakpoints.h"
  26 #include "nds32_reg.h"
  27 #include "nds32_disassembler.h"
  28 #include "nds32.h"
  29 #include "nds32_aice.h"
  30 #include "nds32_v3_common.h"
  31
  32 static struct nds32_v3_common_callback *v3_common_callback;
  33
  34 static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no)
  35 {
  36         if (reg_no == PC)
  37                 return IR11;
  38
  39         return reg_no;
  40 }
  41
  42 static int nds32_v3_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
  43 {
  44         uint32_t edmsw;
  45         struct aice_port_s *aice = target_to_aice(nds32->target);
  46         aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
  47
  48         *reason = (edmsw >> 12) & 0x0F;
  49
  50         return ERROR_OK;
  51 }
  52
  53 /**
  54  * Save processor state.  This is called after a HALT instruction
  55  * succeeds, and on other occasions the processor enters debug mode
  56  * (breakpoint, watchpoint, etc).
  57  */
  58 static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
  59 {
  60         LOG_DEBUG("nds32_v3_debug_entry");
  61
  62         jtag_poll_set_enabled(false);
  63
  64         enum target_state backup_state = nds32->target->state;
  65         nds32->target->state = TARGET_HALTED;
  66
  67         if (nds32->init_arch_info_after_halted == false) {
  68                 /* init architecture info according to config registers */
  69                 CHECK_RETVAL(nds32_config(nds32));
  70
  71                 nds32->init_arch_info_after_halted = true;
  72         }
  73
  74         /* REVISIT entire cache should already be invalid !!! */
  75         register_cache_invalidate(nds32->core_cache);
  76
  77         /* deactivate all hardware breakpoints */
  78         CHECK_RETVAL(v3_common_callback->deactivate_hardware_breakpoint(nds32->target));
  79
  80         if (enable_watchpoint)
  81                 CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target));
  82
  83         if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
  84                 nds32->target->state = backup_state;
  85
  86                 /* re-activate all hardware breakpoints & watchpoints */
  87                 CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(nds32->target));
  88
  89                 if (enable_watchpoint)
  90                         CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(nds32->target));
  91
  92                 jtag_poll_set_enabled(true);
  93
  94                 return ERROR_FAIL;
  95         }
  96
  97         /* Save registers. */
  98         nds32_full_context(nds32);
  99
 100         /* check interrupt level */
 101         v3_common_callback->check_interrupt_stack(nds32);
 102
 103         return ERROR_OK;
 104 }
 105
 106 /**
 107  * Restore processor state.
 108  */
 109 static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
 110 {
 111         LOG_DEBUG("nds32_v3_leave_debug_state");
 112
 113         struct target *target = nds32->target;
 114
 115         /* activate all hardware breakpoints */
 116         CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(target));
 117
 118         if (enable_watchpoint) {
 119                 /* activate all watchpoints */
 120                 CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(target));
 121         }
 122
 123         /* restore interrupt stack */
 124         v3_common_callback->restore_interrupt_stack(nds32);
 125
 126         /* REVISIT once we start caring about MMU and cache state,
 127          * address it here ...
 128          */
 129
 130         /* restore PSW, PC, and R0 ... after flushing any modified
 131          * registers.
 132          */
 133         CHECK_RETVAL(nds32_restore_context(target));
 134
 135         /* enable polling */
 136         jtag_poll_set_enabled(true);
 137
 138         return ERROR_OK;
 139 }
 140
 141 static int nds32_v3_get_exception_address(struct nds32 *nds32,
 142                 uint32_t *address, uint32_t reason)
 143 {
 144         LOG_DEBUG("nds32_v3_get_exception_address");
 145
 146         struct aice_port_s *aice = target_to_aice(nds32->target);
 147         struct target *target = nds32->target;
 148         uint32_t edmsw;
 149         uint32_t edm_cfg;
 150         uint32_t match_bits;
 151         uint32_t match_count;
 152         int32_t i;
 153         static int32_t number_of_hard_break;
 154
 155         if (number_of_hard_break == 0) {
 156                 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
 157                 number_of_hard_break = (edm_cfg & 0x7) + 1;
 158         }
 159
 160         aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
 161         /* clear matching bits (write-one-clear) */
 162         aice_write_debug_reg(aice, NDS_EDM_SR_EDMSW, edmsw);
 163         match_bits = (edmsw >> 4) & 0xFF;
 164         match_count = 0;
 165         for (i = 0 ; i < number_of_hard_break ; i++) {
 166                 if (match_bits & (1 << i)) {
 167                         aice_read_debug_reg(aice, NDS_EDM_SR_BPA0 + i, address);
 168                         match_count++;
 169                 }
 170         }
 171
 172         if (match_count > 1) { /* multiple hits */
 173                 *address = 0;
 174                 return ERROR_OK;
 175         } else if (match_count == 1) {
 176                 uint32_t val_pc;
 177                 uint32_t opcode;
 178                 struct nds32_instruction instruction;
 179                 struct watchpoint *wp;
 180                 bool hit;
 181
 182                 nds32_get_mapped_reg(nds32, PC, &val_pc);
 183
 184                 if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) ||
 185                                 (NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) {
 186                         if (edmsw & 0x4) /* check EDMSW.IS_16BIT */
 187                                 val_pc -= 2;
 188                         else
 189                                 val_pc -= 4;
 190                 }
 191
 192                 nds32_read_opcode(nds32, val_pc, &opcode);
 193                 nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
 194
 195                 LOG_DEBUG("PC: 0x%08x, access start: 0x%08x, end: 0x%08x", val_pc,
 196                                 instruction.access_start, instruction.access_end);
 197
 198                 /* check if multiple hits in the access range */
 199                 uint32_t in_range_watch_count = 0;
 200                 for (wp = target->watchpoints; wp; wp = wp->next) {
 201                         if ((instruction.access_start <= wp->address) &&
 202                                         (wp->address < instruction.access_end))
 203                                 in_range_watch_count++;
 204                 }
 205                 if (in_range_watch_count > 1) {
 206                         /* Hit LSMW instruction. */
 207                         *address = 0;
 208                         return ERROR_OK;
 209                 }
 210
 211                 /* dispel false match */
 212                 hit = false;
 213                 for (wp = target->watchpoints; wp; wp = wp->next) {
 214                         if (((*address ^ wp->address) & (~wp->mask)) == 0) {
 215                                 uint32_t watch_start;
 216                                 uint32_t watch_end;
 217
 218                                 watch_start = wp->address;
 219                                 watch_end = wp->address + wp->length;
 220
 221                                 if ((watch_end <= instruction.access_start) ||
 222                                                 (instruction.access_end <= watch_start))
 223                                         continue;
 224
 225                                 hit = true;
 226                                 break;
 227                         }
 228                 }
 229
 230                 if (hit)
 231                         return ERROR_OK;
 232                 else
 233                         return ERROR_FAIL;
 234         } else if (match_count == 0) {
 235                 /* global stop is precise exception */
 236                 if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) {
 237                         /* parse instruction to get correct access address */
 238                         uint32_t val_pc;
 239                         uint32_t opcode;
 240                         struct nds32_instruction instruction;
 241
 242                         nds32_get_mapped_reg(nds32, PC, &val_pc);
 243                         nds32_read_opcode(nds32, val_pc, &opcode);
 244                         nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
 245
 246                         *address = instruction.access_start;
 247
 248                         return ERROR_OK;
 249                 }
 250         }
 251
 252         *address = 0xFFFFFFFF;
 253         return ERROR_FAIL;
 254 }
 255
 256 void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback)
 257 {
 258         v3_common_callback = callback;
 259 }
 260
 261 /** target_type functions: */
 262 /* target request support */
 263 int nds32_v3_target_request_data(struct target *target,
 264                 uint32_t size, uint8_t *buffer)
 265 {
 266         /* AndesCore could use DTR register to communicate with OpenOCD
 267          * to output messages
 268          * Target data will be put in buffer
 269          * The format of DTR is as follow
 270          * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
 271          * target_req_cmd has three possible values:
 272          *   TARGET_REQ_TRACEMSG
 273          *   TARGET_REQ_DEBUGMSG
 274          *   TARGET_REQ_DEBUGCHAR
 275          * if size == 0, target will call target_asciimsg(),
 276          * else call target_hexmsg()
 277          */
 278         LOG_WARNING("Not implemented: %s", __func__);
 279
 280         return ERROR_OK;
 281 }
 282
 283 int nds32_v3_soft_reset_halt(struct target *target)
 284 {
 285         struct aice_port_s *aice = target_to_aice(target);
 286         return aice_assert_srst(aice, AICE_RESET_HOLD);
 287 }
 288
 289 int nds32_v3_checksum_memory(struct target *target,
 290                 uint32_t address, uint32_t count, uint32_t *checksum)
 291 {
 292         LOG_WARNING("Not implemented: %s", __func__);
 293
 294         return ERROR_FAIL;
 295 }
 296
 297 /**
 298  * find out which watchpoint hits
 299  * get exception address and compare the address to watchpoints
 300  */
 301 int nds32_v3_hit_watchpoint(struct target *target,
 302                 struct watchpoint **hit_watchpoint)
 303 {
 304         static struct watchpoint scan_all_watchpoint;
 305
 306         uint32_t exception_address;
 307         struct watchpoint *wp;
 308         struct nds32 *nds32 = target_to_nds32(target);
 309
 310         exception_address = nds32->watched_address;
 311
 312         if (exception_address == 0xFFFFFFFF)
 313                 return ERROR_FAIL;
 314
 315         if (exception_address == 0) {
 316                 scan_all_watchpoint.address = 0;
 317                 scan_all_watchpoint.rw = WPT_WRITE;
 318                 scan_all_watchpoint.next = 0;
 319                 scan_all_watchpoint.unique_id = 0x5CA8;
 320
 321                 *hit_watchpoint = &scan_all_watchpoint;
 322                 return ERROR_OK;
 323         }
 324
 325         for (wp = target->watchpoints; wp; wp = wp->next) {
 326                 if (((exception_address ^ wp->address) & (~wp->mask)) == 0) {
 327                         *hit_watchpoint = wp;
 328
 329                         return ERROR_OK;
 330                 }
 331         }
 332
 333         return ERROR_FAIL;
 334 }
 335
 336 int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32)
 337 {
 338         nds32->register_map = nds32_v3_register_mapping;
 339         nds32->get_debug_reason = nds32_v3_get_debug_reason;
 340         nds32->enter_debug_state = nds32_v3_debug_entry;
 341         nds32->leave_debug_state = nds32_v3_leave_debug_state;
 342         nds32->get_watched_address = nds32_v3_get_exception_address;
 343
 344         /* Init target->arch_info in nds32_init_arch_info().
 345          * After this, user could use target_to_nds32() to get nds32 object */
 346         nds32_init_arch_info(target, nds32);
 347
 348         return ERROR_OK;
 349 }
 350
 351 int nds32_v3_run_algorithm(struct target *target,
 352                 int num_mem_params,
 353                 struct mem_param *mem_params,
 354                 int num_reg_params,
 355                 struct reg_param *reg_params,
 356                 uint32_t entry_point,
 357                 uint32_t exit_point,
 358                 int timeout_ms,
 359                 void *arch_info)
 360 {
 361         LOG_WARNING("Not implemented: %s", __func__);
 362
 363         return ERROR_FAIL;
 364 }
 365
 366 int nds32_v3_read_buffer(struct target *target, uint32_t address,
 367                 uint32_t size, uint8_t *buffer)
 368 {
 369         struct nds32 *nds32 = target_to_nds32(target);
 370         struct nds32_memory *memory = &(nds32->memory);
 371
 372         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 373                         (target->state != TARGET_HALTED)) {
 374                 LOG_WARNING("target was not halted");
 375                 return ERROR_TARGET_NOT_HALTED;
 376         }
 377
 378         uint32_t physical_address;
 379         /* BUG: If access range crosses multiple pages, the translation will not correct
 380          * for second page or so. */
 381
 382         /* When DEX is set to one, hardware will enforce the following behavior without
 383          * modifying the corresponding control bits in PSW.
 384          *
 385          * Disable all interrupts
 386          * Become superuser mode
 387          * Turn off IT/DT
 388          * Use MMU_CFG.DE as the data access endian
 389          * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
 390          * Disable audio special features
 391          * Disable inline function call
 392          *
 393          * Because hardware will turn off IT/DT by default, it MUST translate virtual address
 394          * to physical address.
 395          */
 396         if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
 397                 address = physical_address;
 398         else
 399                 return ERROR_FAIL;
 400
 401         return nds32_read_buffer(target, address, size, buffer);
 402 }
 403
 404 int nds32_v3_write_buffer(struct target *target, uint32_t address,
 405                 uint32_t size, const uint8_t *buffer)
 406 {
 407         struct nds32 *nds32 = target_to_nds32(target);
 408         struct nds32_memory *memory = &(nds32->memory);
 409
 410         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 411                         (target->state != TARGET_HALTED)) {
 412                 LOG_WARNING("target was not halted");
 413                 return ERROR_TARGET_NOT_HALTED;
 414         }
 415
 416         uint32_t physical_address;
 417         /* BUG: If access range crosses multiple pages, the translation will not correct
 418          * for second page or so. */
 419
 420         /* When DEX is set to one, hardware will enforce the following behavior without
 421          * modifying the corresponding control bits in PSW.
 422          *
 423          * Disable all interrupts
 424          * Become superuser mode
 425          * Turn off IT/DT
 426          * Use MMU_CFG.DE as the data access endian
 427          * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
 428          * Disable audio special features
 429          * Disable inline function call
 430          *
 431          * Because hardware will turn off IT/DT by default, it MUST translate virtual address
 432          * to physical address.
 433          */
 434         if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
 435                 address = physical_address;
 436         else
 437                 return ERROR_FAIL;
 438
 439         return nds32_write_buffer(target, address, size, buffer);
 440 }
 441
 442 int nds32_v3_read_memory(struct target *target, uint32_t address,
 443                 uint32_t size, uint32_t count, uint8_t *buffer)
 444 {
 445         struct nds32 *nds32 = target_to_nds32(target);
 446         struct nds32_memory *memory = &(nds32->memory);
 447
 448         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 449                         (target->state != TARGET_HALTED)) {
 450                 LOG_WARNING("target was not halted");
 451                 return ERROR_TARGET_NOT_HALTED;
 452         }
 453
 454         uint32_t physical_address;
 455         /* BUG: If access range crosses multiple pages, the translation will not correct
 456          * for second page or so. */
 457
 458         /* When DEX is set to one, hardware will enforce the following behavior without
 459          * modifying the corresponding control bits in PSW.
 460          *
 461          * Disable all interrupts
 462          * Become superuser mode
 463          * Turn off IT/DT
 464          * Use MMU_CFG.DE as the data access endian
 465          * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
 466          * Disable audio special features
 467          * Disable inline function call
 468          *
 469          * Because hardware will turn off IT/DT by default, it MUST translate virtual address
 470          * to physical address.
 471          */
 472         if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
 473                 address = physical_address;
 474         else
 475                 return ERROR_FAIL;
 476
 477         int result;
 478
 479         result = nds32_read_memory(target, address, size, count, buffer);
 480
 481         return result;
 482 }
 483
 484 int nds32_v3_write_memory(struct target *target, uint32_t address,
 485                 uint32_t size, uint32_t count, const uint8_t *buffer)
 486 {
 487         struct nds32 *nds32 = target_to_nds32(target);
 488         struct nds32_memory *memory = &(nds32->memory);
 489
 490         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 491                         (target->state != TARGET_HALTED)) {
 492                 LOG_WARNING("target was not halted");
 493                 return ERROR_TARGET_NOT_HALTED;
 494         }
 495
 496         uint32_t physical_address;
 497         /* BUG: If access range crosses multiple pages, the translation will not correct
 498          * for second page or so. */
 499
 500         /* When DEX is set to one, hardware will enforce the following behavior without
 501          * modifying the corresponding control bits in PSW.
 502          *
 503          * Disable all interrupts
 504          * Become superuser mode
 505          * Turn off IT/DT
 506          * Use MMU_CFG.DE as the data access endian
 507          * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
 508          * Disable audio special features
 509          * Disable inline function call
 510          *
 511          * Because hardware will turn off IT/DT by default, it MUST translate virtual address
 512          * to physical address.
 513          */
 514         if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
 515                 address = physical_address;
 516         else
 517                 return ERROR_FAIL;
 518
 519         return nds32_write_memory(target, address, size, count, buffer);
 520 }
 521
 522 int nds32_v3_init_target(struct command_context *cmd_ctx,
 523                 struct target *target)
 524 {
 525         /* Initialize anything we can set up without talking to the target */
 526         struct nds32 *nds32 = target_to_nds32(target);
 527
 528         nds32_init(nds32);
 529
 530         return ERROR_OK;
 531 }