1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm_simulator.h"
32 #include "arm_disassembler.h"
35 #include "binarybuffer.h"
36 #include "time_support.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
49 int xscale_register_commands(struct command_context_s *cmd_ctx);
51 /* forward declarations */
52 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
53 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
56 int xscale_arch_state(struct target_s *target);
57 int xscale_poll(target_t *target);
58 int xscale_halt(target_t *target);
59 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
60 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
61 int xscale_debug_entry(target_t *target);
62 int xscale_restore_context(target_t *target);
64 int xscale_assert_reset(target_t *target);
65 int xscale_deassert_reset(target_t *target);
66 int xscale_soft_reset_halt(struct target_s *target);
68 int xscale_set_reg_u32(reg_t *reg, u32 value);
70 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
71 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
73 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
74 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
75 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
76 int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
78 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
79 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
80 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
81 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
82 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
83 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
84 void xscale_enable_watchpoints(struct target_s *target);
85 void xscale_enable_breakpoints(struct target_s *target);
86 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
87 static int xscale_mmu(struct target_s *target, int *enabled);
89 int xscale_read_trace(target_t *target);
91 target_type_t xscale_target =
96 .arch_state = xscale_arch_state,
98 .target_request_data = NULL,
101 .resume = xscale_resume,
104 .assert_reset = xscale_assert_reset,
105 .deassert_reset = xscale_deassert_reset,
106 .soft_reset_halt = xscale_soft_reset_halt,
108 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
110 .read_memory = xscale_read_memory,
111 .write_memory = xscale_write_memory,
112 .bulk_write_memory = xscale_bulk_write_memory,
113 .checksum_memory = xscale_checksum_memory,
115 .run_algorithm = armv4_5_run_algorithm,
117 .add_breakpoint = xscale_add_breakpoint,
118 .remove_breakpoint = xscale_remove_breakpoint,
119 .add_watchpoint = xscale_add_watchpoint,
120 .remove_watchpoint = xscale_remove_watchpoint,
122 .register_commands = xscale_register_commands,
123 .target_command = xscale_target_command,
124 .init_target = xscale_init_target,
127 .virt2phys = xscale_virt2phys,
131 char* xscale_reg_list[] =
133 "XSCALE_MAINID", /* 0 */
143 "XSCALE_IBCR0", /* 10 */
153 "XSCALE_RX", /* 20 */
157 xscale_reg_t xscale_reg_arch_info[] =
159 {XSCALE_MAINID, NULL},
160 {XSCALE_CACHETYPE, NULL},
162 {XSCALE_AUXCTRL, NULL},
168 {XSCALE_CPACCESS, NULL},
169 {XSCALE_IBCR0, NULL},
170 {XSCALE_IBCR1, NULL},
173 {XSCALE_DBCON, NULL},
174 {XSCALE_TBREG, NULL},
175 {XSCALE_CHKPT0, NULL},
176 {XSCALE_CHKPT1, NULL},
177 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
178 {-1, NULL}, /* TX accessed via JTAG */
179 {-1, NULL}, /* RX accessed via JTAG */
180 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
183 int xscale_reg_arch_type = -1;
185 int xscale_get_reg(reg_t *reg);
186 int xscale_set_reg(reg_t *reg, u8 *buf);
188 int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
190 armv4_5_common_t *armv4_5 = target->arch_info;
191 xscale_common_t *xscale = armv4_5->arch_info;
193 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
195 LOG_ERROR("target isn't an XScale target");
199 if (xscale->common_magic != XSCALE_COMMON_MAGIC)
201 LOG_ERROR("target isn't an XScale target");
205 *armv4_5_p = armv4_5;
211 int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
213 jtag_device_t *device = jtag_get_device(chain_pos);
215 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
219 field.device = chain_pos;
220 field.num_bits = device->ir_length;
221 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
222 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
223 field.out_mask = NULL;
224 field.in_value = NULL;
225 jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
227 jtag_add_ir_scan(1, &field, -1);
229 free(field.out_value);
235 int xscale_read_dcsr(target_t *target)
237 armv4_5_common_t *armv4_5 = target->arch_info;
238 xscale_common_t *xscale = armv4_5->arch_info;
242 scan_field_t fields[3];
244 u8 field0_check_value = 0x2;
245 u8 field0_check_mask = 0x7;
247 u8 field2_check_value = 0x0;
248 u8 field2_check_mask = 0x1;
250 jtag_add_end_state(TAP_PD);
251 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
253 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
254 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
256 fields[0].device = xscale->jtag_info.chain_pos;
257 fields[0].num_bits = 3;
258 fields[0].out_value = &field0;
259 fields[0].out_mask = NULL;
260 fields[0].in_value = NULL;
261 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
263 fields[1].device = xscale->jtag_info.chain_pos;
264 fields[1].num_bits = 32;
265 fields[1].out_value = NULL;
266 fields[1].out_mask = NULL;
267 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
268 fields[1].in_handler = NULL;
269 fields[1].in_handler_priv = NULL;
270 fields[1].in_check_value = NULL;
271 fields[1].in_check_mask = NULL;
273 fields[2].device = xscale->jtag_info.chain_pos;
274 fields[2].num_bits = 1;
275 fields[2].out_value = &field2;
276 fields[2].out_mask = NULL;
277 fields[2].in_value = NULL;
278 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
280 jtag_add_dr_scan(3, fields, -1);
282 if ((retval = jtag_execute_queue()) != ERROR_OK)
284 LOG_ERROR("JTAG error while reading DCSR");
288 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
289 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
291 /* write the register with the value we just read
292 * on this second pass, only the first bit of field0 is guaranteed to be 0)
294 field0_check_mask = 0x1;
295 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
296 fields[1].in_value = NULL;
298 jtag_add_end_state(TAP_RTI);
300 jtag_add_dr_scan(3, fields, -1);
302 /* DANGER!!! this must be here. It will make sure that the arguments
303 * to jtag_set_check_value() does not go out of scope! */
304 return jtag_execute_queue();
307 int xscale_receive(target_t *target, u32 *buffer, int num_words)
310 return ERROR_INVALID_ARGUMENTS;
313 armv4_5_common_t *armv4_5 = target->arch_info;
314 xscale_common_t *xscale = armv4_5->arch_info;
316 enum tap_state path[3];
317 scan_field_t fields[3];
319 u8 *field0 = malloc(num_words * 1);
320 u8 field0_check_value = 0x2;
321 u8 field0_check_mask = 0x6;
322 u32 *field1 = malloc(num_words * 4);
323 u8 field2_check_value = 0x0;
324 u8 field2_check_mask = 0x1;
326 int words_scheduled = 0;
334 fields[0].device = xscale->jtag_info.chain_pos;
335 fields[0].num_bits = 3;
336 fields[0].out_value = NULL;
337 fields[0].out_mask = NULL;
338 fields[0].in_value = NULL;
339 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
341 fields[1].device = xscale->jtag_info.chain_pos;
342 fields[1].num_bits = 32;
343 fields[1].out_value = NULL;
344 fields[1].out_mask = NULL;
345 fields[1].in_value = NULL;
346 fields[1].in_handler = NULL;
347 fields[1].in_handler_priv = NULL;
348 fields[1].in_check_value = NULL;
349 fields[1].in_check_mask = NULL;
353 fields[2].device = xscale->jtag_info.chain_pos;
354 fields[2].num_bits = 1;
355 fields[2].out_value = NULL;
356 fields[2].out_mask = NULL;
357 fields[2].in_value = NULL;
358 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
360 jtag_add_end_state(TAP_RTI);
361 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
362 jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
364 /* repeat until all words have been collected */
366 while (words_done < num_words)
370 for (i = words_done; i < num_words; i++)
372 fields[0].in_value = &field0[i];
373 fields[1].in_handler = buf_to_u32_handler;
374 fields[1].in_handler_priv = (u8*)&field1[i];
376 jtag_add_pathmove(3, path);
377 jtag_add_dr_scan(3, fields, TAP_RTI);
381 if ((retval = jtag_execute_queue()) != ERROR_OK)
383 LOG_ERROR("JTAG error while receiving data from debug handler");
387 /* examine results */
388 for (i = words_done; i < num_words; i++)
390 if (!(field0[0] & 1))
392 /* move backwards if necessary */
394 for (j = i; j < num_words - 1; j++)
396 field0[j] = field0[j+1];
397 field1[j] = field1[j+1];
402 if (words_scheduled==0)
404 if (attempts++==1000)
406 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
407 retval=ERROR_TARGET_TIMEOUT;
412 words_done += words_scheduled;
415 for (i = 0; i < num_words; i++)
416 *(buffer++) = buf_get_u32((u8*)&field1[i], 0, 32);
423 int xscale_read_tx(target_t *target, int consume)
425 armv4_5_common_t *armv4_5 = target->arch_info;
426 xscale_common_t *xscale = armv4_5->arch_info;
427 enum tap_state path[3];
428 enum tap_state noconsume_path[6];
431 struct timeval timeout, now;
433 scan_field_t fields[3];
435 u8 field0_check_value = 0x2;
436 u8 field0_check_mask = 0x6;
437 u8 field2_check_value = 0x0;
438 u8 field2_check_mask = 0x1;
440 jtag_add_end_state(TAP_RTI);
442 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
448 noconsume_path[0] = TAP_SDS;
449 noconsume_path[1] = TAP_CD;
450 noconsume_path[2] = TAP_E1D;
451 noconsume_path[3] = TAP_PD;
452 noconsume_path[4] = TAP_E2D;
453 noconsume_path[5] = TAP_SD;
455 fields[0].device = xscale->jtag_info.chain_pos;
456 fields[0].num_bits = 3;
457 fields[0].out_value = NULL;
458 fields[0].out_mask = NULL;
459 fields[0].in_value = &field0_in;
460 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
462 fields[1].device = xscale->jtag_info.chain_pos;
463 fields[1].num_bits = 32;
464 fields[1].out_value = NULL;
465 fields[1].out_mask = NULL;
466 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
467 fields[1].in_handler = NULL;
468 fields[1].in_handler_priv = NULL;
469 fields[1].in_check_value = NULL;
470 fields[1].in_check_mask = NULL;
474 fields[2].device = xscale->jtag_info.chain_pos;
475 fields[2].num_bits = 1;
476 fields[2].out_value = NULL;
477 fields[2].out_mask = NULL;
478 fields[2].in_value = NULL;
479 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
481 gettimeofday(&timeout, NULL);
482 timeval_add_time(&timeout, 1, 0);
487 for (i=0; i<100; i++)
489 /* if we want to consume the register content (i.e. clear TX_READY),
490 * we have to go straight from Capture-DR to Shift-DR
491 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
494 jtag_add_pathmove(3, path);
497 jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
500 jtag_add_dr_scan(3, fields, TAP_RTI);
502 if ((retval = jtag_execute_queue()) != ERROR_OK)
504 LOG_ERROR("JTAG error while reading TX");
505 return ERROR_TARGET_TIMEOUT;
508 gettimeofday(&now, NULL);
509 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
511 LOG_ERROR("time out reading TX register");
512 return ERROR_TARGET_TIMEOUT;
514 if (!((!(field0_in & 1)) && consume))
519 LOG_DEBUG("waiting 10ms");
520 usleep(10*1000); /* avoid flooding the logs */
524 if (!(field0_in & 1))
525 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
530 int xscale_write_rx(target_t *target)
532 armv4_5_common_t *armv4_5 = target->arch_info;
533 xscale_common_t *xscale = armv4_5->arch_info;
536 struct timeval timeout, now;
538 scan_field_t fields[3];
541 u8 field0_check_value = 0x2;
542 u8 field0_check_mask = 0x6;
544 u8 field2_check_value = 0x0;
545 u8 field2_check_mask = 0x1;
547 jtag_add_end_state(TAP_RTI);
549 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
551 fields[0].device = xscale->jtag_info.chain_pos;
552 fields[0].num_bits = 3;
553 fields[0].out_value = &field0_out;
554 fields[0].out_mask = NULL;
555 fields[0].in_value = &field0_in;
556 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
558 fields[1].device = xscale->jtag_info.chain_pos;
559 fields[1].num_bits = 32;
560 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
561 fields[1].out_mask = NULL;
562 fields[1].in_value = NULL;
563 fields[1].in_handler = NULL;
564 fields[1].in_handler_priv = NULL;
565 fields[1].in_check_value = NULL;
566 fields[1].in_check_mask = NULL;
570 fields[2].device = xscale->jtag_info.chain_pos;
571 fields[2].num_bits = 1;
572 fields[2].out_value = &field2;
573 fields[2].out_mask = NULL;
574 fields[2].in_value = NULL;
575 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
577 gettimeofday(&timeout, NULL);
578 timeval_add_time(&timeout, 1, 0);
580 /* poll until rx_read is low */
581 LOG_DEBUG("polling RX");
587 jtag_add_dr_scan(3, fields, TAP_RTI);
589 if ((retval = jtag_execute_queue()) != ERROR_OK)
591 LOG_ERROR("JTAG error while writing RX");
595 gettimeofday(&now, NULL);
596 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
598 LOG_ERROR("time out writing RX register");
599 return ERROR_TARGET_TIMEOUT;
601 if (!(field0_in & 1))
604 LOG_DEBUG("waiting 10ms");
605 usleep(10*1000); /* wait 10ms to avoid flooding the logs */
611 jtag_add_dr_scan(3, fields, TAP_RTI);
613 if ((retval = jtag_execute_queue()) != ERROR_OK)
615 LOG_ERROR("JTAG error while writing RX");
622 /* send count elements of size byte to the debug handler */
623 int xscale_send(target_t *target, u8 *buffer, int count, int size)
625 armv4_5_common_t *armv4_5 = target->arch_info;
626 xscale_common_t *xscale = armv4_5->arch_info;
634 jtag_add_end_state(TAP_RTI);
636 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
643 int endianness = target->endianness;
644 while (done_count++ < count)
649 if (endianness == TARGET_LITTLE_ENDIAN)
651 t[1]=le_to_h_u32(buffer);
654 t[1]=be_to_h_u32(buffer);
658 if (endianness == TARGET_LITTLE_ENDIAN)
660 t[1]=le_to_h_u16(buffer);
663 t[1]=be_to_h_u16(buffer);
670 LOG_ERROR("BUG: size neither 4, 2 nor 1");
673 jtag_add_dr_out(xscale->jtag_info.chain_pos,
681 if ((retval = jtag_execute_queue()) != ERROR_OK)
683 LOG_ERROR("JTAG error while sending data to debug handler");
690 int xscale_send_u32(target_t *target, u32 value)
692 armv4_5_common_t *armv4_5 = target->arch_info;
693 xscale_common_t *xscale = armv4_5->arch_info;
695 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
696 return xscale_write_rx(target);
699 int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
701 armv4_5_common_t *armv4_5 = target->arch_info;
702 xscale_common_t *xscale = armv4_5->arch_info;
706 scan_field_t fields[3];
708 u8 field0_check_value = 0x2;
709 u8 field0_check_mask = 0x7;
711 u8 field2_check_value = 0x0;
712 u8 field2_check_mask = 0x1;
715 xscale->hold_rst = hold_rst;
717 if (ext_dbg_brk != -1)
718 xscale->external_debug_break = ext_dbg_brk;
720 jtag_add_end_state(TAP_RTI);
721 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
723 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
724 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
726 fields[0].device = xscale->jtag_info.chain_pos;
727 fields[0].num_bits = 3;
728 fields[0].out_value = &field0;
729 fields[0].out_mask = NULL;
730 fields[0].in_value = NULL;
731 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
733 fields[1].device = xscale->jtag_info.chain_pos;
734 fields[1].num_bits = 32;
735 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
736 fields[1].out_mask = NULL;
737 fields[1].in_value = NULL;
738 fields[1].in_handler = NULL;
739 fields[1].in_handler_priv = NULL;
740 fields[1].in_check_value = NULL;
741 fields[1].in_check_mask = NULL;
745 fields[2].device = xscale->jtag_info.chain_pos;
746 fields[2].num_bits = 1;
747 fields[2].out_value = &field2;
748 fields[2].out_mask = NULL;
749 fields[2].in_value = NULL;
750 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
752 jtag_add_dr_scan(3, fields, -1);
754 if ((retval = jtag_execute_queue()) != ERROR_OK)
756 LOG_ERROR("JTAG error while writing DCSR");
760 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
761 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
766 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
767 unsigned int parity (unsigned int v)
774 LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
775 return (0x6996 >> v) & 1;
778 int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
780 armv4_5_common_t *armv4_5 = target->arch_info;
781 xscale_common_t *xscale = armv4_5->arch_info;
786 scan_field_t fields[2];
788 LOG_DEBUG("loading miniIC at 0x%8.8x", va);
790 jtag_add_end_state(TAP_RTI);
791 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
793 /* CMD is b010 for Main IC and b011 for Mini IC */
795 buf_set_u32(&cmd, 0, 3, 0x3);
797 buf_set_u32(&cmd, 0, 3, 0x2);
799 buf_set_u32(&cmd, 3, 3, 0x0);
801 /* virtual address of desired cache line */
802 buf_set_u32(packet, 0, 27, va >> 5);
804 fields[0].device = xscale->jtag_info.chain_pos;
805 fields[0].num_bits = 6;
806 fields[0].out_value = &cmd;
807 fields[0].out_mask = NULL;
808 fields[0].in_value = NULL;
809 fields[0].in_check_value = NULL;
810 fields[0].in_check_mask = NULL;
811 fields[0].in_handler = NULL;
812 fields[0].in_handler_priv = NULL;
814 fields[1].device = xscale->jtag_info.chain_pos;
815 fields[1].num_bits = 27;
816 fields[1].out_value = packet;
817 fields[1].out_mask = NULL;
818 fields[1].in_value = NULL;
819 fields[1].in_check_value = NULL;
820 fields[1].in_check_mask = NULL;
821 fields[1].in_handler = NULL;
822 fields[1].in_handler_priv = NULL;
824 jtag_add_dr_scan(2, fields, -1);
826 fields[0].num_bits = 32;
827 fields[0].out_value = packet;
829 fields[1].num_bits = 1;
830 fields[1].out_value = &cmd;
832 for (word = 0; word < 8; word++)
834 buf_set_u32(packet, 0, 32, buffer[word]);
835 cmd = parity(*((u32*)packet));
836 jtag_add_dr_scan(2, fields, -1);
839 jtag_execute_queue();
844 int xscale_invalidate_ic_line(target_t *target, u32 va)
846 armv4_5_common_t *armv4_5 = target->arch_info;
847 xscale_common_t *xscale = armv4_5->arch_info;
851 scan_field_t fields[2];
853 jtag_add_end_state(TAP_RTI);
854 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
856 /* CMD for invalidate IC line b000, bits [6:4] b000 */
857 buf_set_u32(&cmd, 0, 6, 0x0);
859 /* virtual address of desired cache line */
860 buf_set_u32(packet, 0, 27, va >> 5);
862 fields[0].device = xscale->jtag_info.chain_pos;
863 fields[0].num_bits = 6;
864 fields[0].out_value = &cmd;
865 fields[0].out_mask = NULL;
866 fields[0].in_value = NULL;
867 fields[0].in_check_value = NULL;
868 fields[0].in_check_mask = NULL;
869 fields[0].in_handler = NULL;
870 fields[0].in_handler_priv = NULL;
872 fields[1].device = xscale->jtag_info.chain_pos;
873 fields[1].num_bits = 27;
874 fields[1].out_value = packet;
875 fields[1].out_mask = NULL;
876 fields[1].in_value = NULL;
877 fields[1].in_check_value = NULL;
878 fields[1].in_check_mask = NULL;
879 fields[1].in_handler = NULL;
880 fields[1].in_handler_priv = NULL;
882 jtag_add_dr_scan(2, fields, -1);
887 int xscale_update_vectors(target_t *target)
889 armv4_5_common_t *armv4_5 = target->arch_info;
890 xscale_common_t *xscale = armv4_5->arch_info;
894 u32 low_reset_branch, high_reset_branch;
896 for (i = 1; i < 8; i++)
898 /* if there's a static vector specified for this exception, override */
899 if (xscale->static_high_vectors_set & (1 << i))
901 xscale->high_vectors[i] = xscale->static_high_vectors[i];
905 retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
906 if (retval == ERROR_TARGET_TIMEOUT)
908 if (retval!=ERROR_OK)
910 /* Some of these reads will fail as part of normal execution */
911 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
916 for (i = 1; i < 8; i++)
918 if (xscale->static_low_vectors_set & (1 << i))
920 xscale->low_vectors[i] = xscale->static_low_vectors[i];
924 retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
925 if (retval == ERROR_TARGET_TIMEOUT)
927 if (retval!=ERROR_OK)
929 /* Some of these reads will fail as part of normal execution */
930 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
935 /* calculate branches to debug handler */
936 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
937 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
939 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
940 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
942 /* invalidate and load exception vectors in mini i-cache */
943 xscale_invalidate_ic_line(target, 0x0);
944 xscale_invalidate_ic_line(target, 0xffff0000);
946 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
947 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
952 int xscale_arch_state(struct target_s *target)
954 armv4_5_common_t *armv4_5 = target->arch_info;
955 xscale_common_t *xscale = armv4_5->arch_info;
959 "disabled", "enabled"
962 char *arch_dbg_reason[] =
964 "", "\n(processor reset)", "\n(trace buffer full)"
967 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
969 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
973 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
974 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
975 "MMU: %s, D-Cache: %s, I-Cache: %s"
977 armv4_5_state_strings[armv4_5->core_state],
978 target_debug_reason_strings[target->debug_reason],
979 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
980 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
981 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
982 state[xscale->armv4_5_mmu.mmu_enabled],
983 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
984 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
985 arch_dbg_reason[xscale->arch_debug_reason]);
990 int xscale_poll(target_t *target)
993 armv4_5_common_t *armv4_5 = target->arch_info;
994 xscale_common_t *xscale = armv4_5->arch_info;
996 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
998 enum target_state previous_state = target->state;
999 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
1002 /* there's data to read from the tx register, we entered debug state */
1003 xscale->handler_running = 1;
1005 target->state = TARGET_HALTED;
1007 /* process debug entry, fetching current mode regs */
1008 retval = xscale_debug_entry(target);
1010 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1012 LOG_USER("error while polling TX register, reset CPU");
1013 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1014 target->state = TARGET_HALTED;
1017 /* debug_entry could have overwritten target state (i.e. immediate resume)
1018 * don't signal event handlers in that case
1020 if (target->state != TARGET_HALTED)
1023 /* if target was running, signal that we halted
1024 * otherwise we reentered from debug execution */
1025 if (previous_state == TARGET_RUNNING)
1026 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1028 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1034 int xscale_debug_entry(target_t *target)
1036 armv4_5_common_t *armv4_5 = target->arch_info;
1037 xscale_common_t *xscale = armv4_5->arch_info;
1045 /* clear external dbg break (will be written on next DCSR read) */
1046 xscale->external_debug_break = 0;
1047 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1050 /* get r0, pc, r1 to r7 and cpsr */
1051 if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
1054 /* move r0 from buffer to register cache */
1055 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
1056 armv4_5->core_cache->reg_list[15].dirty = 1;
1057 armv4_5->core_cache->reg_list[15].valid = 1;
1058 LOG_DEBUG("r0: 0x%8.8x", buffer[0]);
1060 /* move pc from buffer to register cache */
1061 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
1062 armv4_5->core_cache->reg_list[15].dirty = 1;
1063 armv4_5->core_cache->reg_list[15].valid = 1;
1064 LOG_DEBUG("pc: 0x%8.8x", buffer[1]);
1066 /* move data from buffer to register cache */
1067 for (i = 1; i <= 7; i++)
1069 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
1070 armv4_5->core_cache->reg_list[i].dirty = 1;
1071 armv4_5->core_cache->reg_list[i].valid = 1;
1072 LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
1075 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
1076 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1077 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1078 LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]);
1080 armv4_5->core_mode = buffer[9] & 0x1f;
1081 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1083 target->state = TARGET_UNKNOWN;
1084 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1085 return ERROR_TARGET_FAILURE;
1087 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1089 if (buffer[9] & 0x20)
1090 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1092 armv4_5->core_state = ARMV4_5_STATE_ARM;
1094 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1095 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1097 xscale_receive(target, buffer, 8);
1098 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1099 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1100 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1104 /* r8 to r14, but no spsr */
1105 xscale_receive(target, buffer, 7);
1108 /* move data from buffer to register cache */
1109 for (i = 8; i <= 14; i++)
1111 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
1112 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1113 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1116 /* examine debug reason */
1117 xscale_read_dcsr(target);
1118 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
1120 /* stored PC (for calculating fixup) */
1121 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1125 case 0x0: /* Processor reset */
1126 target->debug_reason = DBG_REASON_DBGRQ;
1127 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
1130 case 0x1: /* Instruction breakpoint hit */
1131 target->debug_reason = DBG_REASON_BREAKPOINT;
1132 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1135 case 0x2: /* Data breakpoint hit */
1136 target->debug_reason = DBG_REASON_WATCHPOINT;
1137 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1140 case 0x3: /* BKPT instruction executed */
1141 target->debug_reason = DBG_REASON_BREAKPOINT;
1142 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1145 case 0x4: /* Ext. debug event */
1146 target->debug_reason = DBG_REASON_DBGRQ;
1147 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1150 case 0x5: /* Vector trap occured */
1151 target->debug_reason = DBG_REASON_BREAKPOINT;
1152 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1155 case 0x6: /* Trace buffer full break */
1156 target->debug_reason = DBG_REASON_DBGRQ;
1157 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1160 case 0x7: /* Reserved */
1162 LOG_ERROR("Method of Entry is 'Reserved'");
1167 /* apply PC fixup */
1168 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1170 /* on the first debug entry, identify cache type */
1171 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1175 /* read cp15 cache type register */
1176 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1177 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1179 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1182 /* examine MMU and Cache settings */
1183 /* read cp15 control register */
1184 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1185 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1186 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1187 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1188 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1190 /* tracing enabled, read collected trace data */
1191 if (xscale->trace.buffer_enabled)
1193 xscale_read_trace(target);
1194 xscale->trace.buffer_fill--;
1196 /* resume if we're still collecting trace data */
1197 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1198 && (xscale->trace.buffer_fill > 0))
1200 xscale_resume(target, 1, 0x0, 1, 0);
1204 xscale->trace.buffer_enabled = 0;
1211 int xscale_halt(target_t *target)
1213 armv4_5_common_t *armv4_5 = target->arch_info;
1214 xscale_common_t *xscale = armv4_5->arch_info;
1216 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1218 if (target->state == TARGET_HALTED)
1220 LOG_DEBUG("target was already halted");
1223 else if (target->state == TARGET_UNKNOWN)
1225 /* this must not happen for a xscale target */
1226 LOG_ERROR("target was in unknown state when halt was requested");
1227 return ERROR_TARGET_INVALID;
1229 else if (target->state == TARGET_RESET)
1231 LOG_DEBUG("target->state == TARGET_RESET");
1235 /* assert external dbg break */
1236 xscale->external_debug_break = 1;
1237 xscale_read_dcsr(target);
1239 target->debug_reason = DBG_REASON_DBGRQ;
1245 int xscale_enable_single_step(struct target_s *target, u32 next_pc)
1247 armv4_5_common_t *armv4_5 = target->arch_info;
1248 xscale_common_t *xscale= armv4_5->arch_info;
1249 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1251 if (xscale->ibcr0_used)
1253 breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1257 xscale_unset_breakpoint(target, ibcr0_bp);
1261 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1266 xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1271 int xscale_disable_single_step(struct target_s *target)
1273 armv4_5_common_t *armv4_5 = target->arch_info;
1274 xscale_common_t *xscale= armv4_5->arch_info;
1275 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1277 xscale_set_reg_u32(ibcr0, 0x0);
1282 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1284 armv4_5_common_t *armv4_5 = target->arch_info;
1285 xscale_common_t *xscale= armv4_5->arch_info;
1286 breakpoint_t *breakpoint = target->breakpoints;
1295 if (target->state != TARGET_HALTED)
1297 LOG_WARNING("target not halted");
1298 return ERROR_TARGET_NOT_HALTED;
1301 if (!debug_execution)
1303 target_free_all_working_areas(target);
1306 /* update vector tables */
1307 if ((retval=xscale_update_vectors(target))!=ERROR_OK)
1310 /* current = 1: continue on current pc, otherwise continue at <address> */
1312 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1314 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1316 /* if we're at the reset vector, we have to simulate the branch */
1317 if (current_pc == 0x0)
1319 arm_simulate_step(target, NULL);
1320 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1323 /* the front-end may request us not to handle breakpoints */
1324 if (handle_breakpoints)
1326 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1330 /* there's a breakpoint at the current PC, we have to step over it */
1331 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1332 xscale_unset_breakpoint(target, breakpoint);
1334 /* calculate PC of next instruction */
1335 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1338 target_read_u32(target, current_pc, ¤t_opcode);
1339 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1342 LOG_DEBUG("enable single-step");
1343 xscale_enable_single_step(target, next_pc);
1345 /* restore banked registers */
1346 xscale_restore_context(target);
1348 /* send resume request (command 0x30 or 0x31)
1349 * clean the trace buffer if it is to be enabled (0x62) */
1350 if (xscale->trace.buffer_enabled)
1352 xscale_send_u32(target, 0x62);
1353 xscale_send_u32(target, 0x31);
1356 xscale_send_u32(target, 0x30);
1359 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1360 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1362 for (i = 7; i >= 0; i--)
1365 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1366 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1370 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1371 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1373 /* wait for and process debug entry */
1374 xscale_debug_entry(target);
1376 LOG_DEBUG("disable single-step");
1377 xscale_disable_single_step(target);
1379 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1380 xscale_set_breakpoint(target, breakpoint);
1384 /* enable any pending breakpoints and watchpoints */
1385 xscale_enable_breakpoints(target);
1386 xscale_enable_watchpoints(target);
1388 /* restore banked registers */
1389 xscale_restore_context(target);
1391 /* send resume request (command 0x30 or 0x31)
1392 * clean the trace buffer if it is to be enabled (0x62) */
1393 if (xscale->trace.buffer_enabled)
1395 xscale_send_u32(target, 0x62);
1396 xscale_send_u32(target, 0x31);
1399 xscale_send_u32(target, 0x30);
1402 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1403 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1405 for (i = 7; i >= 0; i--)
1408 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1409 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1413 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1414 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1416 target->debug_reason = DBG_REASON_NOTHALTED;
1418 if (!debug_execution)
1420 /* registers are now invalid */
1421 armv4_5_invalidate_core_regs(target);
1422 target->state = TARGET_RUNNING;
1423 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1427 target->state = TARGET_DEBUG_RUNNING;
1428 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1431 LOG_DEBUG("target resumed");
1433 xscale->handler_running = 1;
1438 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1440 armv4_5_common_t *armv4_5 = target->arch_info;
1441 xscale_common_t *xscale = armv4_5->arch_info;
1442 breakpoint_t *breakpoint = target->breakpoints;
1444 u32 current_pc, next_pc;
1448 if (target->state != TARGET_HALTED)
1450 LOG_WARNING("target not halted");
1451 return ERROR_TARGET_NOT_HALTED;
1454 /* current = 1: continue on current pc, otherwise continue at <address> */
1456 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1458 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1460 /* if we're at the reset vector, we have to simulate the step */
1461 if (current_pc == 0x0)
1463 arm_simulate_step(target, NULL);
1464 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1466 target->debug_reason = DBG_REASON_SINGLESTEP;
1467 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1472 /* the front-end may request us not to handle breakpoints */
1473 if (handle_breakpoints)
1474 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1476 xscale_unset_breakpoint(target, breakpoint);
1479 target->debug_reason = DBG_REASON_SINGLESTEP;
1481 /* calculate PC of next instruction */
1482 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1485 target_read_u32(target, current_pc, ¤t_opcode);
1486 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1489 LOG_DEBUG("enable single-step");
1490 xscale_enable_single_step(target, next_pc);
1492 /* restore banked registers */
1493 xscale_restore_context(target);
1495 /* send resume request (command 0x30 or 0x31)
1496 * clean the trace buffer if it is to be enabled (0x62) */
1497 if (xscale->trace.buffer_enabled)
1499 xscale_send_u32(target, 0x62);
1500 xscale_send_u32(target, 0x31);
1503 xscale_send_u32(target, 0x30);
1506 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1507 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1509 for (i = 7; i >= 0; i--)
1512 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1513 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1517 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1518 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1520 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1522 /* registers are now invalid */
1523 armv4_5_invalidate_core_regs(target);
1525 /* wait for and process debug entry */
1526 xscale_debug_entry(target);
1528 LOG_DEBUG("disable single-step");
1529 xscale_disable_single_step(target);
1531 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1535 xscale_set_breakpoint(target, breakpoint);
1538 LOG_DEBUG("target stepped");
1544 int xscale_assert_reset(target_t *target)
1546 armv4_5_common_t *armv4_5 = target->arch_info;
1547 xscale_common_t *xscale = armv4_5->arch_info;
1549 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1551 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1552 * end up in T-L-R, which would reset JTAG
1554 jtag_add_end_state(TAP_RTI);
1555 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
1557 /* set Hold reset, Halt mode and Trap Reset */
1558 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1559 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1560 xscale_write_dcsr(target, 1, 0);
1562 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1563 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
1564 jtag_execute_queue();
1567 jtag_add_reset(0, 1);
1569 /* sleep 1ms, to be sure we fulfill any requirements */
1570 jtag_add_sleep(1000);
1571 jtag_execute_queue();
1573 target->state = TARGET_RESET;
1578 int xscale_deassert_reset(target_t *target)
1580 armv4_5_common_t *armv4_5 = target->arch_info;
1581 xscale_common_t *xscale = armv4_5->arch_info;
1583 fileio_t debug_handler;
1591 breakpoint_t *breakpoint = target->breakpoints;
1595 xscale->ibcr_available = 2;
1596 xscale->ibcr0_used = 0;
1597 xscale->ibcr1_used = 0;
1599 xscale->dbr_available = 2;
1600 xscale->dbr0_used = 0;
1601 xscale->dbr1_used = 0;
1603 /* mark all hardware breakpoints as unset */
1606 if (breakpoint->type == BKPT_HARD)
1608 breakpoint->set = 0;
1610 breakpoint = breakpoint->next;
1613 if (!xscale->handler_installed)
1616 jtag_add_reset(0, 0);
1618 /* wait 300ms; 150 and 100ms were not enough */
1619 jtag_add_sleep(300*1000);
1621 jtag_add_runtest(2030, TAP_RTI);
1622 jtag_execute_queue();
1624 /* set Hold reset, Halt mode and Trap Reset */
1625 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1626 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1627 xscale_write_dcsr(target, 1, 0);
1629 /* Load debug handler */
1630 if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1635 if ((binary_size = debug_handler.size) % 4)
1637 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1641 if (binary_size > 0x800)
1643 LOG_ERROR("debug_handler.bin: larger than 2kb");
1647 binary_size = CEIL(binary_size, 32) * 32;
1649 address = xscale->handler_address;
1650 while (binary_size > 0)
1655 if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
1660 for (i = 0; i < buf_cnt; i += 4)
1662 /* convert LE buffer to host-endian u32 */
1663 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1666 for (; buf_cnt < 32; buf_cnt += 4)
1668 cache_line[buf_cnt / 4] = 0xe1a08008;
1671 /* only load addresses other than the reset vectors */
1672 if ((address % 0x400) != 0x0)
1674 xscale_load_ic(target, 1, address, cache_line);
1678 binary_size -= buf_cnt;
1681 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
1682 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
1684 jtag_add_runtest(30, TAP_RTI);
1686 jtag_add_sleep(100000);
1688 /* set Hold reset, Halt mode and Trap Reset */
1689 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1690 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1691 xscale_write_dcsr(target, 1, 0);
1693 /* clear Hold reset to let the target run (should enter debug handler) */
1694 xscale_write_dcsr(target, 0, 1);
1695 target->state = TARGET_RUNNING;
1697 if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT))
1699 jtag_add_sleep(10000);
1701 /* we should have entered debug now */
1702 xscale_debug_entry(target);
1703 target->state = TARGET_HALTED;
1705 /* resume the target */
1706 xscale_resume(target, 1, 0x0, 1, 0);
1709 fileio_close(&debug_handler);
1713 jtag_add_reset(0, 0);
1720 int xscale_soft_reset_halt(struct target_s *target)
1726 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1732 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1738 int xscale_full_context(target_t *target)
1740 armv4_5_common_t *armv4_5 = target->arch_info;
1748 if (target->state != TARGET_HALTED)
1750 LOG_WARNING("target not halted");
1751 return ERROR_TARGET_NOT_HALTED;
1754 buffer = malloc(4 * 8);
1756 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1757 * we can't enter User mode on an XScale (unpredictable),
1758 * but User shares registers with SYS
1760 for(i = 1; i < 7; i++)
1764 /* check if there are invalid registers in the current mode
1766 for (j = 0; j <= 16; j++)
1768 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1776 /* request banked registers */
1777 xscale_send_u32(target, 0x0);
1780 tmp_cpsr |= armv4_5_number_to_mode(i);
1781 tmp_cpsr |= 0xc0; /* I/F bits */
1783 /* send CPSR for desired mode */
1784 xscale_send_u32(target, tmp_cpsr);
1786 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1787 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1789 xscale_receive(target, buffer, 8);
1790 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1791 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1792 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1796 xscale_receive(target, buffer, 7);
1799 /* move data from buffer to register cache */
1800 for (j = 8; j <= 14; j++)
1802 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
1803 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1804 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1814 int xscale_restore_context(target_t *target)
1816 armv4_5_common_t *armv4_5 = target->arch_info;
1822 if (target->state != TARGET_HALTED)
1824 LOG_WARNING("target not halted");
1825 return ERROR_TARGET_NOT_HALTED;
1828 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1829 * we can't enter User mode on an XScale (unpredictable),
1830 * but User shares registers with SYS
1832 for(i = 1; i < 7; i++)
1836 /* check if there are invalid registers in the current mode
1838 for (j = 8; j <= 14; j++)
1840 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
1844 /* if not USR/SYS, check if the SPSR needs to be written */
1845 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1847 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
1855 /* send banked registers */
1856 xscale_send_u32(target, 0x1);
1859 tmp_cpsr |= armv4_5_number_to_mode(i);
1860 tmp_cpsr |= 0xc0; /* I/F bits */
1862 /* send CPSR for desired mode */
1863 xscale_send_u32(target, tmp_cpsr);
1865 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1866 for (j = 8; j <= 14; j++)
1868 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
1869 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1872 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1874 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
1875 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1883 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1885 armv4_5_common_t *armv4_5 = target->arch_info;
1886 xscale_common_t *xscale = armv4_5->arch_info;
1891 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1893 if (target->state != TARGET_HALTED)
1895 LOG_WARNING("target not halted");
1896 return ERROR_TARGET_NOT_HALTED;
1899 /* sanitize arguments */
1900 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1901 return ERROR_INVALID_ARGUMENTS;
1903 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1904 return ERROR_TARGET_UNALIGNED_ACCESS;
1906 /* send memory read request (command 0x1n, n: access size) */
1907 if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
1910 /* send base address for read request */
1911 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
1914 /* send number of requested data words */
1915 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
1918 /* receive data from target (count times 32-bit words in host endianness) */
1919 buf32 = malloc(4 * count);
1920 if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
1923 /* extract data from host-endian buffer into byte stream */
1924 for (i = 0; i < count; i++)
1929 target_buffer_set_u32(target, buffer, buf32[i]);
1933 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1937 *buffer++ = buf32[i] & 0xff;
1940 LOG_ERROR("should never get here");
1947 /* examine DCSR, to see if Sticky Abort (SA) got set */
1948 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1950 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1953 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
1956 return ERROR_TARGET_DATA_ABORT;
1962 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1964 armv4_5_common_t *armv4_5 = target->arch_info;
1965 xscale_common_t *xscale = armv4_5->arch_info;
1968 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1970 if (target->state != TARGET_HALTED)
1972 LOG_WARNING("target not halted");
1973 return ERROR_TARGET_NOT_HALTED;
1976 /* sanitize arguments */
1977 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1978 return ERROR_INVALID_ARGUMENTS;
1980 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1981 return ERROR_TARGET_UNALIGNED_ACCESS;
1983 /* send memory write request (command 0x2n, n: access size) */
1984 if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
1987 /* send base address for read request */
1988 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
1991 /* send number of requested data words to be written*/
1992 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
1995 /* extract data from host-endian buffer into byte stream */
1997 for (i = 0; i < count; i++)
2002 value = target_buffer_get_u32(target, buffer);
2003 xscale_send_u32(target, value);
2007 value = target_buffer_get_u16(target, buffer);
2008 xscale_send_u32(target, value);
2013 xscale_send_u32(target, value);
2017 LOG_ERROR("should never get here");
2022 if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
2025 /* examine DCSR, to see if Sticky Abort (SA) got set */
2026 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
2028 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
2031 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
2034 return ERROR_TARGET_DATA_ABORT;
2040 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2042 return xscale_write_memory(target, address, 4, count, buffer);
2045 int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2047 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2050 u32 xscale_get_ttb(target_t *target)
2052 armv4_5_common_t *armv4_5 = target->arch_info;
2053 xscale_common_t *xscale = armv4_5->arch_info;
2056 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2057 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2062 void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2064 armv4_5_common_t *armv4_5 = target->arch_info;
2065 xscale_common_t *xscale = armv4_5->arch_info;
2068 /* read cp15 control register */
2069 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2070 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2073 cp15_control &= ~0x1U;
2078 xscale_send_u32(target, 0x50);
2079 xscale_send_u32(target, xscale->cache_clean_address);
2081 /* invalidate DCache */
2082 xscale_send_u32(target, 0x51);
2084 cp15_control &= ~0x4U;
2089 /* invalidate ICache */
2090 xscale_send_u32(target, 0x52);
2091 cp15_control &= ~0x1000U;
2094 /* write new cp15 control register */
2095 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2097 /* execute cpwait to ensure outstanding operations complete */
2098 xscale_send_u32(target, 0x53);
2101 void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2103 armv4_5_common_t *armv4_5 = target->arch_info;
2104 xscale_common_t *xscale = armv4_5->arch_info;
2107 /* read cp15 control register */
2108 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2109 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2112 cp15_control |= 0x1U;
2115 cp15_control |= 0x4U;
2118 cp15_control |= 0x1000U;
2120 /* write new cp15 control register */
2121 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2123 /* execute cpwait to ensure outstanding operations complete */
2124 xscale_send_u32(target, 0x53);
2127 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2129 armv4_5_common_t *armv4_5 = target->arch_info;
2130 xscale_common_t *xscale = armv4_5->arch_info;
2132 if (target->state != TARGET_HALTED)
2134 LOG_WARNING("target not halted");
2135 return ERROR_TARGET_NOT_HALTED;
2138 if (xscale->force_hw_bkpts)
2139 breakpoint->type = BKPT_HARD;
2141 if (breakpoint->set)
2143 LOG_WARNING("breakpoint already set");
2147 if (breakpoint->type == BKPT_HARD)
2149 u32 value = breakpoint->address | 1;
2150 if (!xscale->ibcr0_used)
2152 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2153 xscale->ibcr0_used = 1;
2154 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2156 else if (!xscale->ibcr1_used)
2158 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2159 xscale->ibcr1_used = 1;
2160 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2164 LOG_ERROR("BUG: no hardware comparator available");
2168 else if (breakpoint->type == BKPT_SOFT)
2170 if (breakpoint->length == 4)
2172 /* keep the original instruction in target endianness */
2173 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2174 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2175 target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
2179 /* keep the original instruction in target endianness */
2180 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2181 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2182 target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
2184 breakpoint->set = 1;
2191 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2193 armv4_5_common_t *armv4_5 = target->arch_info;
2194 xscale_common_t *xscale = armv4_5->arch_info;
2196 if (target->state != TARGET_HALTED)
2198 LOG_WARNING("target not halted");
2199 return ERROR_TARGET_NOT_HALTED;
2202 if (xscale->force_hw_bkpts)
2204 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
2205 breakpoint->type = BKPT_HARD;
2208 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2210 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2211 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2215 xscale->ibcr_available--;
2218 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2220 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2221 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2227 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2229 armv4_5_common_t *armv4_5 = target->arch_info;
2230 xscale_common_t *xscale = armv4_5->arch_info;
2232 if (target->state != TARGET_HALTED)
2234 LOG_WARNING("target not halted");
2235 return ERROR_TARGET_NOT_HALTED;
2238 if (!breakpoint->set)
2240 LOG_WARNING("breakpoint not set");
2244 if (breakpoint->type == BKPT_HARD)
2246 if (breakpoint->set == 1)
2248 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2249 xscale->ibcr0_used = 0;
2251 else if (breakpoint->set == 2)
2253 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2254 xscale->ibcr1_used = 0;
2256 breakpoint->set = 0;
2260 /* restore original instruction (kept in target endianness) */
2261 if (breakpoint->length == 4)
2263 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2267 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2269 breakpoint->set = 0;
2275 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2277 armv4_5_common_t *armv4_5 = target->arch_info;
2278 xscale_common_t *xscale = armv4_5->arch_info;
2280 if (target->state != TARGET_HALTED)
2282 LOG_WARNING("target not halted");
2283 return ERROR_TARGET_NOT_HALTED;
2286 if (breakpoint->set)
2288 xscale_unset_breakpoint(target, breakpoint);
2291 if (breakpoint->type == BKPT_HARD)
2292 xscale->ibcr_available++;
2297 int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2299 armv4_5_common_t *armv4_5 = target->arch_info;
2300 xscale_common_t *xscale = armv4_5->arch_info;
2302 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2303 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2305 if (target->state != TARGET_HALTED)
2307 LOG_WARNING("target not halted");
2308 return ERROR_TARGET_NOT_HALTED;
2311 xscale_get_reg(dbcon);
2313 switch (watchpoint->rw)
2325 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2328 if (!xscale->dbr0_used)
2330 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2331 dbcon_value |= enable;
2332 xscale_set_reg_u32(dbcon, dbcon_value);
2333 watchpoint->set = 1;
2334 xscale->dbr0_used = 1;
2336 else if (!xscale->dbr1_used)
2338 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2339 dbcon_value |= enable << 2;
2340 xscale_set_reg_u32(dbcon, dbcon_value);
2341 watchpoint->set = 2;
2342 xscale->dbr1_used = 1;
2346 LOG_ERROR("BUG: no hardware comparator available");
2353 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2355 armv4_5_common_t *armv4_5 = target->arch_info;
2356 xscale_common_t *xscale = armv4_5->arch_info;
2358 if (target->state != TARGET_HALTED)
2360 LOG_WARNING("target not halted");
2361 return ERROR_TARGET_NOT_HALTED;
2364 if (xscale->dbr_available < 1)
2366 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2369 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
2371 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2374 xscale->dbr_available--;
2379 int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2381 armv4_5_common_t *armv4_5 = target->arch_info;
2382 xscale_common_t *xscale = armv4_5->arch_info;
2383 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2384 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2386 if (target->state != TARGET_HALTED)
2388 LOG_WARNING("target not halted");
2389 return ERROR_TARGET_NOT_HALTED;
2392 if (!watchpoint->set)
2394 LOG_WARNING("breakpoint not set");
2398 if (watchpoint->set == 1)
2400 dbcon_value &= ~0x3;
2401 xscale_set_reg_u32(dbcon, dbcon_value);
2402 xscale->dbr0_used = 0;
2404 else if (watchpoint->set == 2)
2406 dbcon_value &= ~0xc;
2407 xscale_set_reg_u32(dbcon, dbcon_value);
2408 xscale->dbr1_used = 0;
2410 watchpoint->set = 0;
2415 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2417 armv4_5_common_t *armv4_5 = target->arch_info;
2418 xscale_common_t *xscale = armv4_5->arch_info;
2420 if (target->state != TARGET_HALTED)
2422 LOG_WARNING("target not halted");
2423 return ERROR_TARGET_NOT_HALTED;
2426 if (watchpoint->set)
2428 xscale_unset_watchpoint(target, watchpoint);
2431 xscale->dbr_available++;
2436 void xscale_enable_watchpoints(struct target_s *target)
2438 watchpoint_t *watchpoint = target->watchpoints;
2442 if (watchpoint->set == 0)
2443 xscale_set_watchpoint(target, watchpoint);
2444 watchpoint = watchpoint->next;
2448 void xscale_enable_breakpoints(struct target_s *target)
2450 breakpoint_t *breakpoint = target->breakpoints;
2452 /* set any pending breakpoints */
2455 if (breakpoint->set == 0)
2456 xscale_set_breakpoint(target, breakpoint);
2457 breakpoint = breakpoint->next;
2461 int xscale_get_reg(reg_t *reg)
2463 xscale_reg_t *arch_info = reg->arch_info;
2464 target_t *target = arch_info->target;
2465 armv4_5_common_t *armv4_5 = target->arch_info;
2466 xscale_common_t *xscale = armv4_5->arch_info;
2468 /* DCSR, TX and RX are accessible via JTAG */
2469 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2471 return xscale_read_dcsr(arch_info->target);
2473 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2475 /* 1 = consume register content */
2476 return xscale_read_tx(arch_info->target, 1);
2478 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2480 /* can't read from RX register (host -> debug handler) */
2483 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2485 /* can't (explicitly) read from TXRXCTRL register */
2488 else /* Other DBG registers have to be transfered by the debug handler */
2490 /* send CP read request (command 0x40) */
2491 xscale_send_u32(target, 0x40);
2493 /* send CP register number */
2494 xscale_send_u32(target, arch_info->dbg_handler_number);
2496 /* read register value */
2497 xscale_read_tx(target, 1);
2498 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2507 int xscale_set_reg(reg_t *reg, u8* buf)
2509 xscale_reg_t *arch_info = reg->arch_info;
2510 target_t *target = arch_info->target;
2511 armv4_5_common_t *armv4_5 = target->arch_info;
2512 xscale_common_t *xscale = armv4_5->arch_info;
2513 u32 value = buf_get_u32(buf, 0, 32);
2515 /* DCSR, TX and RX are accessible via JTAG */
2516 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2518 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2519 return xscale_write_dcsr(arch_info->target, -1, -1);
2521 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2523 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2524 return xscale_write_rx(arch_info->target);
2526 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2528 /* can't write to TX register (debug-handler -> host) */
2531 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2533 /* can't (explicitly) write to TXRXCTRL register */
2536 else /* Other DBG registers have to be transfered by the debug handler */
2538 /* send CP write request (command 0x41) */
2539 xscale_send_u32(target, 0x41);
2541 /* send CP register number */
2542 xscale_send_u32(target, arch_info->dbg_handler_number);
2544 /* send CP register value */
2545 xscale_send_u32(target, value);
2546 buf_set_u32(reg->value, 0, 32, value);
2552 /* convenience wrapper to access XScale specific registers */
2553 int xscale_set_reg_u32(reg_t *reg, u32 value)
2557 buf_set_u32(buf, 0, 32, value);
2559 return xscale_set_reg(reg, buf);
2562 int xscale_write_dcsr_sw(target_t *target, u32 value)
2564 /* get pointers to arch-specific information */
2565 armv4_5_common_t *armv4_5 = target->arch_info;
2566 xscale_common_t *xscale = armv4_5->arch_info;
2567 reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2568 xscale_reg_t *dcsr_arch_info = dcsr->arch_info;
2570 /* send CP write request (command 0x41) */
2571 xscale_send_u32(target, 0x41);
2573 /* send CP register number */
2574 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2576 /* send CP register value */
2577 xscale_send_u32(target, value);
2578 buf_set_u32(dcsr->value, 0, 32, value);
2583 int xscale_read_trace(target_t *target)
2585 /* get pointers to arch-specific information */
2586 armv4_5_common_t *armv4_5 = target->arch_info;
2587 xscale_common_t *xscale = armv4_5->arch_info;
2588 xscale_trace_data_t **trace_data_p;
2590 /* 258 words from debug handler
2591 * 256 trace buffer entries
2592 * 2 checkpoint addresses
2594 u32 trace_buffer[258];
2595 int is_address[256];
2598 if (target->state != TARGET_HALTED)
2600 LOG_WARNING("target must be stopped to read trace data");
2601 return ERROR_TARGET_NOT_HALTED;
2604 /* send read trace buffer command (command 0x61) */
2605 xscale_send_u32(target, 0x61);
2607 /* receive trace buffer content */
2608 xscale_receive(target, trace_buffer, 258);
2610 /* parse buffer backwards to identify address entries */
2611 for (i = 255; i >= 0; i--)
2614 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2615 ((trace_buffer[i] & 0xf0) == 0xd0))
2618 is_address[--i] = 1;
2620 is_address[--i] = 1;
2622 is_address[--i] = 1;
2624 is_address[--i] = 1;
2629 /* search first non-zero entry */
2630 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2635 LOG_DEBUG("no trace data collected");
2636 return ERROR_XSCALE_NO_TRACE_DATA;
2639 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2642 *trace_data_p = malloc(sizeof(xscale_trace_data_t));
2643 (*trace_data_p)->next = NULL;
2644 (*trace_data_p)->chkpt0 = trace_buffer[256];
2645 (*trace_data_p)->chkpt1 = trace_buffer[257];
2646 (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2647 (*trace_data_p)->entries = malloc(sizeof(xscale_trace_entry_t) * (256 - j));
2648 (*trace_data_p)->depth = 256 - j;
2650 for (i = j; i < 256; i++)
2652 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2654 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2656 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2662 int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
2664 /* get pointers to arch-specific information */
2665 armv4_5_common_t *armv4_5 = target->arch_info;
2666 xscale_common_t *xscale = armv4_5->arch_info;
2673 if (!xscale->trace.image)
2674 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2676 /* search for the section the current instruction belongs to */
2677 for (i = 0; i < xscale->trace.image->num_sections; i++)
2679 if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) &&
2680 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc))
2689 /* current instruction couldn't be found in the image */
2690 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2693 if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
2696 if ((retval = image_read_section(xscale->trace.image, section,
2697 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2698 4, buf, &size_read)) != ERROR_OK)
2700 LOG_ERROR("error while reading instruction: %i", retval);
2701 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2703 opcode = target_buffer_get_u32(target, buf);
2704 arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2706 else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
2709 if ((retval = image_read_section(xscale->trace.image, section,
2710 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2711 2, buf, &size_read)) != ERROR_OK)
2713 LOG_ERROR("error while reading instruction: %i", retval);
2714 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2716 opcode = target_buffer_get_u16(target, buf);
2717 thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2721 LOG_ERROR("BUG: unknown core state encountered");
2728 int xscale_branch_address(xscale_trace_data_t *trace_data, int i, u32 *target)
2730 /* if there are less than four entries prior to the indirect branch message
2731 * we can't extract the address */
2737 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2738 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2743 int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
2745 /* get pointers to arch-specific information */
2746 armv4_5_common_t *armv4_5 = target->arch_info;
2747 xscale_common_t *xscale = armv4_5->arch_info;
2750 xscale_trace_data_t *trace_data = xscale->trace.data;
2759 xscale->trace.core_state = ARMV4_5_STATE_ARM;
2764 for (i = 0; i < trace_data->depth; i++)
2770 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2773 switch ((trace_data->entries[i].data & 0xf0) >> 4)
2775 case 0: /* Exceptions */
2783 exception = (trace_data->entries[i].data & 0x70) >> 4;
2785 next_pc = (trace_data->entries[i].data & 0xf0) >> 2;
2786 command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4);
2788 case 8: /* Direct Branch */
2791 case 9: /* Indirect Branch */
2793 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2798 case 13: /* Checkpointed Indirect Branch */
2799 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2802 if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
2803 || ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
2804 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2806 /* explicit fall-through */
2807 case 12: /* Checkpointed Direct Branch */
2812 next_pc = trace_data->chkpt0;
2815 else if (chkpt == 1)
2818 next_pc = trace_data->chkpt0;
2823 LOG_WARNING("more than two checkpointed branches encountered");
2826 case 15: /* Roll-over */
2829 default: /* Reserved */
2830 command_print(cmd_ctx, "--- reserved trace message ---");
2831 LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
2835 if (xscale->trace.pc_ok)
2837 int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
2838 arm_instruction_t instruction;
2840 if ((exception == 6) || (exception == 7))
2842 /* IRQ or FIQ exception, no instruction executed */
2846 while (executed-- >= 0)
2848 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2850 /* can't continue tracing with no image available */
2851 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2855 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2857 /* TODO: handle incomplete images */
2861 /* a precise abort on a load to the PC is included in the incremental
2862 * word count, other instructions causing data aborts are not included
2864 if ((executed == 0) && (exception == 4)
2865 && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM)))
2867 if ((instruction.type == ARM_LDM)
2868 && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0))
2872 else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
2873 && (instruction.info.load_store.Rd != 15))
2879 /* only the last instruction executed
2880 * (the one that caused the control flow change)
2881 * could be a taken branch
2883 if (((executed == -1) && (branch == 1)) &&
2884 (((instruction.type == ARM_B) ||
2885 (instruction.type == ARM_BL) ||
2886 (instruction.type == ARM_BLX)) &&
2887 (instruction.info.b_bl_bx_blx.target_address != -1)))
2889 xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
2893 xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
2895 command_print(cmd_ctx, "%s", instruction.text);
2903 xscale->trace.current_pc = next_pc;
2904 xscale->trace.pc_ok = 1;
2908 for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
2910 arm_instruction_t instruction;
2911 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2913 /* can't continue tracing with no image available */
2914 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2918 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2920 /* TODO: handle incomplete images */
2923 command_print(cmd_ctx, "%s", instruction.text);
2926 trace_data = trace_data->next;
2932 void xscale_build_reg_cache(target_t *target)
2934 /* get pointers to arch-specific information */
2935 armv4_5_common_t *armv4_5 = target->arch_info;
2936 xscale_common_t *xscale = armv4_5->arch_info;
2938 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
2939 xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
2941 int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
2943 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
2944 armv4_5->core_cache = (*cache_p);
2946 /* register a register arch-type for XScale dbg registers only once */
2947 if (xscale_reg_arch_type == -1)
2948 xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
2950 (*cache_p)->next = malloc(sizeof(reg_cache_t));
2951 cache_p = &(*cache_p)->next;
2953 /* fill in values for the xscale reg cache */
2954 (*cache_p)->name = "XScale registers";
2955 (*cache_p)->next = NULL;
2956 (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
2957 (*cache_p)->num_regs = num_regs;
2959 for (i = 0; i < num_regs; i++)
2961 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2962 (*cache_p)->reg_list[i].value = calloc(4, 1);
2963 (*cache_p)->reg_list[i].dirty = 0;
2964 (*cache_p)->reg_list[i].valid = 0;
2965 (*cache_p)->reg_list[i].size = 32;
2966 (*cache_p)->reg_list[i].bitfield_desc = NULL;
2967 (*cache_p)->reg_list[i].num_bitfields = 0;
2968 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2969 (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
2970 arch_info[i] = xscale_reg_arch_info[i];
2971 arch_info[i].target = target;
2974 xscale->reg_cache = (*cache_p);
2977 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
2988 int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, char *variant)
2990 armv4_5_common_t *armv4_5;
2991 u32 high_reset_branch, low_reset_branch;
2994 armv4_5 = &xscale->armv4_5_common;
2996 /* store architecture specfic data (none so far) */
2997 xscale->arch_info = NULL;
2998 xscale->common_magic = XSCALE_COMMON_MAGIC;
3000 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3001 xscale->variant = strdup(variant);
3003 /* prepare JTAG information for the new target */
3004 xscale->jtag_info.chain_pos = chain_pos;
3006 xscale->jtag_info.dbgrx = 0x02;
3007 xscale->jtag_info.dbgtx = 0x10;
3008 xscale->jtag_info.dcsr = 0x09;
3009 xscale->jtag_info.ldic = 0x07;
3011 if ((strcmp(xscale->variant, "pxa250") == 0) ||
3012 (strcmp(xscale->variant, "pxa255") == 0) ||
3013 (strcmp(xscale->variant, "pxa26x") == 0))
3015 xscale->jtag_info.ir_length = 5;
3017 else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
3018 (strcmp(xscale->variant, "ixp42x") == 0) ||
3019 (strcmp(xscale->variant, "ixp45x") == 0) ||
3020 (strcmp(xscale->variant, "ixp46x") == 0))
3022 xscale->jtag_info.ir_length = 7;
3025 /* the debug handler isn't installed (and thus not running) at this time */
3026 xscale->handler_installed = 0;
3027 xscale->handler_running = 0;
3028 xscale->handler_address = 0xfe000800;
3030 /* clear the vectors we keep locally for reference */
3031 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3032 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3034 /* no user-specified vectors have been configured yet */
3035 xscale->static_low_vectors_set = 0x0;
3036 xscale->static_high_vectors_set = 0x0;
3038 /* calculate branches to debug handler */
3039 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3040 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3042 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3043 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3045 for (i = 1; i <= 7; i++)
3047 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3048 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3051 /* 64kB aligned region used for DCache cleaning */
3052 xscale->cache_clean_address = 0xfffe0000;
3054 xscale->hold_rst = 0;
3055 xscale->external_debug_break = 0;
3057 xscale->force_hw_bkpts = 1;
3059 xscale->ibcr_available = 2;
3060 xscale->ibcr0_used = 0;
3061 xscale->ibcr1_used = 0;
3063 xscale->dbr_available = 2;
3064 xscale->dbr0_used = 0;
3065 xscale->dbr1_used = 0;
3067 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3068 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3070 xscale->vector_catch = 0x1;
3072 xscale->trace.capture_status = TRACE_IDLE;
3073 xscale->trace.data = NULL;
3074 xscale->trace.image = NULL;
3075 xscale->trace.buffer_enabled = 0;
3076 xscale->trace.buffer_fill = 0;
3078 /* prepare ARMv4/5 specific information */
3079 armv4_5->arch_info = xscale;
3080 armv4_5->read_core_reg = xscale_read_core_reg;
3081 armv4_5->write_core_reg = xscale_write_core_reg;
3082 armv4_5->full_context = xscale_full_context;
3084 armv4_5_init_arch_info(target, armv4_5);
3086 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3087 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3088 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3089 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3090 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3091 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3092 xscale->armv4_5_mmu.has_tiny_pages = 1;
3093 xscale->armv4_5_mmu.mmu_enabled = 0;
3098 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3099 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
3102 char *variant = NULL;
3103 xscale_common_t *xscale = malloc(sizeof(xscale_common_t));
3104 memset(xscale, 0, sizeof(*xscale));
3108 LOG_ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3112 chain_pos = strtoul(args[3], NULL, 0);
3116 xscale_init_arch_info(target, xscale, chain_pos, variant);
3117 xscale_build_reg_cache(target);
3122 int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3124 target_t *target = NULL;
3125 armv4_5_common_t *armv4_5;
3126 xscale_common_t *xscale;
3128 u32 handler_address;
3132 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3136 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3138 LOG_ERROR("no target '%s' configured", args[0]);
3142 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3147 handler_address = strtoul(args[1], NULL, 0);
3149 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3150 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3152 xscale->handler_address = handler_address;
3156 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3162 int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3164 target_t *target = NULL;
3165 armv4_5_common_t *armv4_5;
3166 xscale_common_t *xscale;
3168 u32 cache_clean_address;
3172 LOG_ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3176 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3178 LOG_ERROR("no target '%s' configured", args[0]);
3182 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3187 cache_clean_address = strtoul(args[1], NULL, 0);
3189 if (cache_clean_address & 0xffff)
3191 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3195 xscale->cache_clean_address = cache_clean_address;
3201 int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3203 target_t *target = get_current_target(cmd_ctx);
3204 armv4_5_common_t *armv4_5;
3205 xscale_common_t *xscale;
3207 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3212 return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
3215 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
3217 armv4_5_common_t *armv4_5;
3218 xscale_common_t *xscale;
3226 if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
3230 u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
3239 static int xscale_mmu(struct target_s *target, int *enabled)
3241 armv4_5_common_t *armv4_5 = target->arch_info;
3242 xscale_common_t *xscale = armv4_5->arch_info;
3244 if (target->state != TARGET_HALTED)
3246 LOG_ERROR("Target not halted");
3247 return ERROR_TARGET_INVALID;
3249 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3254 int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3256 target_t *target = get_current_target(cmd_ctx);
3257 armv4_5_common_t *armv4_5;
3258 xscale_common_t *xscale;
3260 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3265 if (target->state != TARGET_HALTED)
3267 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3273 if (strcmp("enable", args[0]) == 0)
3275 xscale_enable_mmu_caches(target, 1, 0, 0);
3276 xscale->armv4_5_mmu.mmu_enabled = 1;
3278 else if (strcmp("disable", args[0]) == 0)
3280 xscale_disable_mmu_caches(target, 1, 0, 0);
3281 xscale->armv4_5_mmu.mmu_enabled = 0;
3285 command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3290 int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3292 target_t *target = get_current_target(cmd_ctx);
3293 armv4_5_common_t *armv4_5;
3294 xscale_common_t *xscale;
3295 int icache = 0, dcache = 0;
3297 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3302 if (target->state != TARGET_HALTED)
3304 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3308 if (strcmp(cmd, "icache") == 0)
3310 else if (strcmp(cmd, "dcache") == 0)
3315 if (strcmp("enable", args[0]) == 0)
3317 xscale_enable_mmu_caches(target, 0, dcache, icache);
3320 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
3322 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
3324 else if (strcmp("disable", args[0]) == 0)
3326 xscale_disable_mmu_caches(target, 0, dcache, icache);
3329 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
3331 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
3336 command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
3339 command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
3344 int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3346 target_t *target = get_current_target(cmd_ctx);
3347 armv4_5_common_t *armv4_5;
3348 xscale_common_t *xscale;
3350 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3357 command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
3361 xscale->vector_catch = strtoul(args[0], NULL, 0);
3362 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3363 xscale_write_dcsr(target, -1, -1);
3366 command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3371 int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3373 target_t *target = get_current_target(cmd_ctx);
3374 armv4_5_common_t *armv4_5;
3375 xscale_common_t *xscale;
3377 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3382 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3384 xscale->force_hw_bkpts = 1;
3386 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3388 xscale->force_hw_bkpts = 0;
3392 command_print(cmd_ctx, "usage: xscale force_hw_bkpts <enable|disable>");
3395 command_print(cmd_ctx, "force hardware breakpoints %s", (xscale->force_hw_bkpts) ? "enabled" : "disabled");
3400 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3402 target_t *target = get_current_target(cmd_ctx);
3403 armv4_5_common_t *armv4_5;
3404 xscale_common_t *xscale;
3407 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3412 if (target->state != TARGET_HALTED)
3414 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3418 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3420 xscale_trace_data_t *td, *next_td;
3421 xscale->trace.buffer_enabled = 1;
3423 /* free old trace data */
3424 td = xscale->trace.data;
3434 xscale->trace.data = NULL;
3436 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3438 xscale->trace.buffer_enabled = 0;
3441 if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
3444 xscale->trace.buffer_fill = strtoul(args[2], NULL, 0);
3446 xscale->trace.buffer_fill = 1;
3448 else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
3450 xscale->trace.buffer_fill = -1;
3453 if (xscale->trace.buffer_enabled)
3455 /* if we enable the trace buffer in fill-once
3456 * mode we know the address of the first instruction */
3457 xscale->trace.pc_ok = 1;
3458 xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
3462 /* otherwise the address is unknown, and we have no known good PC */
3463 xscale->trace.pc_ok = 0;
3466 command_print(cmd_ctx, "trace buffer %s (%s)",
3467 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3468 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3470 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3471 if (xscale->trace.buffer_fill >= 0)
3472 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3474 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3479 int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3482 armv4_5_common_t *armv4_5;
3483 xscale_common_t *xscale;
3487 command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
3491 target = get_current_target(cmd_ctx);
3493 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3498 if (xscale->trace.image)
3500 image_close(xscale->trace.image);
3501 free(xscale->trace.image);
3502 command_print(cmd_ctx, "previously loaded image found and closed");
3505 xscale->trace.image = malloc(sizeof(image_t));
3506 xscale->trace.image->base_address_set = 0;
3507 xscale->trace.image->start_address_set = 0;
3509 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3512 xscale->trace.image->base_address_set = 1;
3513 xscale->trace.image->base_address = strtoul(args[1], NULL, 0);
3517 xscale->trace.image->base_address_set = 0;
3520 if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
3522 free(xscale->trace.image);
3523 xscale->trace.image = NULL;
3530 int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3532 target_t *target = get_current_target(cmd_ctx);
3533 armv4_5_common_t *armv4_5;
3534 xscale_common_t *xscale;
3535 xscale_trace_data_t *trace_data;
3538 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3543 if (target->state != TARGET_HALTED)
3545 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3551 command_print(cmd_ctx, "usage: xscale dump_trace <file>");
3555 trace_data = xscale->trace.data;
3559 command_print(cmd_ctx, "no trace data collected");
3563 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3572 fileio_write_u32(&file, trace_data->chkpt0);
3573 fileio_write_u32(&file, trace_data->chkpt1);
3574 fileio_write_u32(&file, trace_data->last_instruction);
3575 fileio_write_u32(&file, trace_data->depth);
3577 for (i = 0; i < trace_data->depth; i++)
3578 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3580 trace_data = trace_data->next;
3583 fileio_close(&file);
3588 int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3590 target_t *target = get_current_target(cmd_ctx);
3591 armv4_5_common_t *armv4_5;
3592 xscale_common_t *xscale;
3594 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3599 xscale_analyze_trace(target, cmd_ctx);
3604 int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3606 target_t *target = get_current_target(cmd_ctx);
3607 armv4_5_common_t *armv4_5;
3608 xscale_common_t *xscale;
3610 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3615 if (target->state != TARGET_HALTED)
3617 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3624 reg_no = strtoul(args[0], NULL, 0);
3625 /*translate from xscale cp15 register no to openocd register*/
3629 reg_no = XSCALE_MAINID;
3632 reg_no = XSCALE_CTRL;
3635 reg_no = XSCALE_TTB;
3638 reg_no = XSCALE_DAC;
3641 reg_no = XSCALE_FSR;
3644 reg_no = XSCALE_FAR;
3647 reg_no = XSCALE_PID;
3650 reg_no = XSCALE_CPACCESS;
3653 command_print(cmd_ctx, "invalid register number");
3654 return ERROR_INVALID_ARGUMENTS;
3656 reg = &xscale->reg_cache->reg_list[reg_no];
3663 /* read cp15 control register */
3664 xscale_get_reg(reg);
3665 value = buf_get_u32(reg->value, 0, 32);
3666 command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value);
3671 u32 value = strtoul(args[1], NULL, 0);
3673 /* send CP write request (command 0x41) */
3674 xscale_send_u32(target, 0x41);
3676 /* send CP register number */
3677 xscale_send_u32(target, reg_no);
3679 /* send CP register value */
3680 xscale_send_u32(target, value);
3682 /* execute cpwait to ensure outstanding operations complete */
3683 xscale_send_u32(target, 0x53);
3687 command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
3693 int xscale_register_commands(struct command_context_s *cmd_ctx)
3695 command_t *xscale_cmd;
3697 xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
3699 register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
3700 register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
3702 register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
3703 register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
3704 register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
3705 register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
3707 register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
3709 register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
3711 register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
3712 register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
3713 register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
3714 COMMAND_EXEC, "load image from <file> [base address]");
3716 register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
3718 armv4_5_register_commands(cmd_ctx);