2 # script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
6 # samdXX devices only support SWD transports.
8 source [find target/swj-dp.tcl]
10 if { [info exists CHIPNAME] } {
11 set _CHIPNAME $CHIPNAME
13 set _CHIPNAME at91samd
16 if { [info exists ENDIAN] } {
22 # Work-area is a space in RAM used for flash programming
24 if { [info exists WORKAREASIZE] } {
25 set _WORKAREASIZE $WORKAREASIZE
27 set _WORKAREASIZE 0x800
30 if { [info exists CPUTAPID] } {
31 set _CPUTAPID $CPUTAPID
33 set _CPUTAPID 0x4ba00477
36 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
38 set _TARGETNAME $_CHIPNAME.cpu
39 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
43 # SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
44 # deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
46 # dsu_reset_deassert configures whether we want to run or halt out of reset,
47 # then instruct the DSU to let us out of reset.
48 $_TARGETNAME configure -event reset-deassert-post {
49 at91samd dsu_reset_deassert
52 # SRST (wired to RESET_N) resets debug circuitry
53 # srst_pulls_trst is not configured here to avoid an error raised in reset halt
54 reset_config srst_gates_jtag
56 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) cannot
57 # stop the MCU before it starts executing code if hardware RESETN
58 # line is configured by command "reset_config srst_only"
59 # Use "reset_config none" (default) before flash programming.
61 # Do not use a reset button with other SWD adapter than Atmel's EDBG.
62 # DSU usually locks MCU in reset state until you issue a reset command
65 # SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
66 # Other members of family usually use SYSCLK = 4 MHz after reset.
67 # Datasheet does not specify SYSCLK to SWD clock ratio.
68 # Usually used SYSCLK/6 is slow, testing shows that debugging can
69 # work @ SYSCLK/2 but your mileage may vary.
70 # This limit is most probably imposed by incorrectly handled SWD WAIT
71 # on some SWD adapters.
75 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
76 # without problem at maximal clock speed. Atmel recommends
77 # adapter speed less than 10 * CPU clock.
81 # if srst is not fitted use SYSRESETREQ to
82 # perform a soft reset
83 cortex_m reset_config sysresetreq
86 set _FLASHNAME $_CHIPNAME.flash
87 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME