1 # TI/Luminary Stellaris LM3S chip family
3 # Some devices have errata in returning their device class.
4 # DEVICECLASS is provided as a manual override
5 # Manual setting of a device class of 0xff is not allowed
9 if { [info exists DEVICECLASS ] } {
10 set _DEVICECLASS $DEVICECLASS
15 # Luminary chips support both JTAG and SWD transports.
16 # Adapt based on what transport is active.
17 source [find target/swj-dp.tcl]
19 # For now we ignore the SPI and UART options, which
20 # are usable only for ISP style initial flash programming.
22 if { [info exists CHIPNAME] } {
23 set _CHIPNAME $CHIPNAME
28 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
29 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
30 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
31 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
32 # ... we'll ignore the JTAG version field, rather than list every
33 # chip revision that turns up.
34 if { [info exists CPUTAPID ] } {
35 set _CPUTAPID $CPUTAPID
37 set _CPUTAPID 0x0ba00477
40 # SWD DAP, and JTAG TAP, take same params for now;
41 # ... even though SWD ignores all except TAPID, and
42 # JTAG shouldn't need anything more then irlen. (and TAPID).
43 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
44 -expected-id $_CPUTAPID -ignore-version
46 if { [info exists WORKAREASIZE ] } {
47 set _WORKAREASIZE $WORKAREASIZE
49 # default to 8K working area
50 set _WORKAREASIZE 0x2000
53 set _TARGETNAME $_CHIPNAME.cpu
54 target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
56 # 8K working area at base of ram, not backed up
58 # NOTE: you may need or want to reconfigure the work area;
59 # some parts have just 6K, and you may want to use other
60 # addresses (at end of mem not beginning) or back it up.
61 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
63 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
64 # LM3S parts don't support RTCK
66 # NOTE: this may be increased by a reset-init handler, after it
67 # configures and enables the PLL. Or you might need to decrease
68 # this, if you're using a slower clock.
71 source [find mem_helper.tcl]
73 $_TARGETNAME configure -event reset-start {
77 # When nRST is asserted on most Stellaris devices, it clears some of
78 # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
79 # and OpenOCD depends on those TRMs. So we won't use SRST on those
80 # chips. (Only power-on reset should affect debug state, beyond a
81 # few specified bits; not the chip's nRST input, wired to SRST.)
83 # REVISIT current errata specs don't seem to cover this issue.
84 # Do we have more details than this email?
85 # https://lists.berlios.de/pipermail
86 # /openocd-development/2008-August/003065.html
91 if {$_DEVICECLASS != 0xff} {
92 set device_class $_DEVICECLASS
94 set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
97 if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
98 # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
99 cortex_m3 reset_config sysresetreq
101 # Tempest and newer default to using NVIC VECTRESET
102 # this does mean a reset-init event handler is required to reset
104 cortex_m3 reset_config vectreset
108 # flash configuration ... autodetects sizes, autoprobed
109 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME