1 # script for stm32h7x family
4 # stm32h7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32h7x
17 # Work-area is a space in RAM used for flash programming
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x10000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 set _CPUTAPID 0x6ba00477
32 set _CPUTAPID 0x6ba02477
36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
40 swj_newdap $_CHIPNAME bs -irlen 5
43 set _TARGETNAME $_CHIPNAME.cpu
44 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
46 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
48 set _FLASHNAME $_CHIPNAME.flash
49 flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
51 # Clock after reset is HSI at 64 MHz, no need of PLL
54 adapter_nsrst_delay 100
59 # use hardware reset, connect under reset
60 reset_config srst_only srst_nogate
63 # if srst is not fitted use SYSRESETREQ to
64 # perform a soft reset
65 cortex_m reset_config sysresetreq
68 $_TARGETNAME configure -event examine-end {
69 # Enable D3 and D1 DBG clocks
70 # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
71 mmw 0x5C001004 0x00600000 0
73 # Enable debug during low power modes (uses more power)
74 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
75 mmw 0x5C001004 0x00000187 0
77 # Stop watchdog counters during halt
78 # DBGMCU_APB3FZ1 |= WWDG1
79 mmw 0x5C001034 0x00000040 0
80 # DBGMCU_APB4FZ1 |= WDGLSD1
81 mmw 0x5C001054 0x00040000 0
84 $_TARGETNAME configure -event trace-config {
85 # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
86 # change this value accordingly to configure trace pins
88 mmw 0x5C001004 0x00100000 0
91 $_TARGETNAME configure -event reset-init {
92 # Clock after reset is HSI at 64 MHz, no need of PLL
96 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
97 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
98 # makes the data access cacheable. This allows reading and writing data in the
99 # CPU cache from the debugger, which is far more useful than going straight to
100 # RAM when operating on typical variables, and is generally no worse when
101 # operating on special memory locations.
102 $_CHIPNAME.dap apcsw 0x08000000 0x08000000