git.sur5r.net Git - freertos/blob

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xreg_cortexa9.h
  36 *
  37 * This header file contains definitions for using inline assembler code. It is
  38 * written specifically for the GNU, ARMCC compiler.
  39 *
  40 * All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
  41 * with the positions of the bits within the registers.
  42 *
  43 * <pre>
  44 * MODIFICATION HISTORY:
  45 *
  46 * Ver   Who      Date     Changes
  47 * ----- -------- -------- -----------------------------------------------
  48 * 1.00a ecm/sdm  10/20/09 First release
  49 * </pre>
  50 *
  51 ******************************************************************************/
  52 #ifndef XREG_CORTEXA9_H
  53 #define XREG_CORTEXA9_H
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif /* __cplusplus */
  58
  59 /* GPRs */
  60 #define XREG_GPR0                               r0
  61 #define XREG_GPR1                               r1
  62 #define XREG_GPR2                               r2
  63 #define XREG_GPR3                               r3
  64 #define XREG_GPR4                               r4
  65 #define XREG_GPR5                               r5
  66 #define XREG_GPR6                               r6
  67 #define XREG_GPR7                               r7
  68 #define XREG_GPR8                               r8
  69 #define XREG_GPR9                               r9
  70 #define XREG_GPR10                              r10
  71 #define XREG_GPR11                              r11
  72 #define XREG_GPR12                              r12
  73 #define XREG_GPR13                              r13
  74 #define XREG_GPR14                              r14
  75 #define XREG_GPR15                              r15
  76 #define XREG_CPSR                               cpsr
  77
  78 /* Coprocessor number defines */
  79 #define XREG_CP0                                0
  80 #define XREG_CP1                                1
  81 #define XREG_CP2                                2
  82 #define XREG_CP3                                3
  83 #define XREG_CP4                                4
  84 #define XREG_CP5                                5
  85 #define XREG_CP6                                6
  86 #define XREG_CP7                                7
  87 #define XREG_CP8                                8
  88 #define XREG_CP9                                9
  89 #define XREG_CP10                               10
  90 #define XREG_CP11                               11
  91 #define XREG_CP12                               12
  92 #define XREG_CP13                               13
  93 #define XREG_CP14                               14
  94 #define XREG_CP15                               15
  95
  96 /* Coprocessor control register defines */
  97 #define XREG_CR0                                cr0
  98 #define XREG_CR1                                cr1
  99 #define XREG_CR2                                cr2
 100 #define XREG_CR3                                cr3
 101 #define XREG_CR4                                cr4
 102 #define XREG_CR5                                cr5
 103 #define XREG_CR6                                cr6
 104 #define XREG_CR7                                cr7
 105 #define XREG_CR8                                cr8
 106 #define XREG_CR9                                cr9
 107 #define XREG_CR10                               cr10
 108 #define XREG_CR11                               cr11
 109 #define XREG_CR12                               cr12
 110 #define XREG_CR13                               cr13
 111 #define XREG_CR14                               cr14
 112 #define XREG_CR15                               cr15
 113
 114 /* Current Processor Status Register (CPSR) Bits */
 115 #define XREG_CPSR_THUMB_MODE                    0x20
 116 #define XREG_CPSR_MODE_BITS                     0x1F
 117 #define XREG_CPSR_SYSTEM_MODE                   0x1F
 118 #define XREG_CPSR_UNDEFINED_MODE                0x1B
 119 #define XREG_CPSR_DATA_ABORT_MODE               0x17
 120 #define XREG_CPSR_SVC_MODE                      0x13
 121 #define XREG_CPSR_IRQ_MODE                      0x12
 122 #define XREG_CPSR_FIQ_MODE                      0x11
 123 #define XREG_CPSR_USER_MODE                     0x10
 124
 125 #define XREG_CPSR_IRQ_ENABLE                    0x80
 126 #define XREG_CPSR_FIQ_ENABLE                    0x40
 127
 128 #define XREG_CPSR_N_BIT                         0x80000000
 129 #define XREG_CPSR_Z_BIT                         0x40000000
 130 #define XREG_CPSR_C_BIT                         0x20000000
 131 #define XREG_CPSR_V_BIT                         0x10000000
 132
 133
 134 /* CP15 defines */
 135 #if defined (__GNUC__)
 136 /* C0 Register defines */
 137 #define XREG_CP15_MAIN_ID                       "p15, 0, %0,  c0,  c0, 0"
 138 #define XREG_CP15_CACHE_TYPE                    "p15, 0, %0,  c0,  c0, 1"
 139 #define XREG_CP15_TCM_TYPE                      "p15, 0, %0,  c0,  c0, 2"
 140 #define XREG_CP15_TLB_TYPE                      "p15, 0, %0,  c0,  c0, 3"
 141 #define XREG_CP15_MULTI_PROC_AFFINITY           "p15, 0, %0,  c0,  c0, 5"
 142
 143 #define XREG_CP15_PROC_FEATURE_0                "p15, 0, %0,  c0,  c1, 0"
 144 #define XREG_CP15_PROC_FEATURE_1                "p15, 0, %0,  c0,  c1, 1"
 145 #define XREG_CP15_DEBUG_FEATURE_0               "p15, 0, %0,  c0,  c1, 2"
 146 #define XREG_CP15_MEMORY_FEATURE_0              "p15, 0, %0,  c0,  c1, 4"
 147 #define XREG_CP15_MEMORY_FEATURE_1              "p15, 0, %0,  c0,  c1, 5"
 148 #define XREG_CP15_MEMORY_FEATURE_2              "p15, 0, %0,  c0,  c1, 6"
 149 #define XREG_CP15_MEMORY_FEATURE_3              "p15, 0, %0,  c0,  c1, 7"
 150
 151 #define XREG_CP15_INST_FEATURE_0                "p15, 0, %0,  c0,  c2, 0"
 152 #define XREG_CP15_INST_FEATURE_1                "p15, 0, %0,  c0,  c2, 1"
 153 #define XREG_CP15_INST_FEATURE_2                "p15, 0, %0,  c0,  c2, 2"
 154 #define XREG_CP15_INST_FEATURE_3                "p15, 0, %0,  c0,  c2, 3"
 155 #define XREG_CP15_INST_FEATURE_4                "p15, 0, %0,  c0,  c2, 4"
 156
 157 #define XREG_CP15_CACHE_SIZE_ID                 "p15, 1, %0,  c0,  c0, 0"
 158 #define XREG_CP15_CACHE_LEVEL_ID                "p15, 1, %0,  c0,  c0, 1"
 159 #define XREG_CP15_AUXILARY_ID                   "p15, 1, %0,  c0,  c0, 7"
 160
 161 #define XREG_CP15_CACHE_SIZE_SEL                "p15, 2, %0,  c0,  c0, 0"
 162
 163 /* C1 Register Defines */
 164 #define XREG_CP15_SYS_CONTROL                   "p15, 0, %0,  c1,  c0, 0"
 165 #define XREG_CP15_AUX_CONTROL                   "p15, 0, %0,  c1,  c0, 1"
 166 #define XREG_CP15_CP_ACCESS_CONTROL             "p15, 0, %0,  c1,  c0, 2"
 167
 168 #define XREG_CP15_SECURE_CONFIG                 "p15, 0, %0,  c1,  c1, 0"
 169 #define XREG_CP15_SECURE_DEBUG_ENABLE           "p15, 0, %0,  c1,  c1, 1"
 170 #define XREG_CP15_NS_ACCESS_CONTROL             "p15, 0, %0,  c1,  c1, 2"
 171 #define XREG_CP15_VIRTUAL_CONTROL               "p15, 0, %0,  c1,  c1, 3"
 172
 173 #else /* RVCT */
 174 /* C0 Register defines */
 175 #define XREG_CP15_MAIN_ID                       "cp15:0:c0:c0:0"
 176 #define XREG_CP15_CACHE_TYPE                    "cp15:0:c0:c0:1"
 177 #define XREG_CP15_TCM_TYPE                      "cp15:0:c0:c0:2"
 178 #define XREG_CP15_TLB_TYPE                      "cp15:0:c0:c0:3"
 179 #define XREG_CP15_MULTI_PROC_AFFINITY           "cp15:0:c0:c0:5"
 180
 181 #define XREG_CP15_PROC_FEATURE_0                "cp15:0:c0:c1:0"
 182 #define XREG_CP15_PROC_FEATURE_1                "cp15:0:c0:c1:1"
 183 #define XREG_CP15_DEBUG_FEATURE_0               "cp15:0:c0:c1:2"
 184 #define XREG_CP15_MEMORY_FEATURE_0              "cp15:0:c0:c1:4"
 185 #define XREG_CP15_MEMORY_FEATURE_1              "cp15:0:c0:c1:5"
 186 #define XREG_CP15_MEMORY_FEATURE_2              "cp15:0:c0:c1:6"
 187 #define XREG_CP15_MEMORY_FEATURE_3              "cp15:0:c0:c1:7"
 188
 189 #define XREG_CP15_INST_FEATURE_0                "cp15:0:c0:c2:0"
 190 #define XREG_CP15_INST_FEATURE_1                "cp15:0:c0:c2:1"
 191 #define XREG_CP15_INST_FEATURE_2                "cp15:0:c0:c2:2"
 192 #define XREG_CP15_INST_FEATURE_3                "cp15:0:c0:c2:3"
 193 #define XREG_CP15_INST_FEATURE_4                "cp15:0:c0:c2:4"
 194
 195 #define XREG_CP15_CACHE_SIZE_ID                 "cp15:1:c0:c0:0"
 196 #define XREG_CP15_CACHE_LEVEL_ID                "cp15:1:c0:c0:1"
 197 #define XREG_CP15_AUXILARY_ID                   "cp15:1:c0:c0:7"
 198
 199 #define XREG_CP15_CACHE_SIZE_SEL                "cp15:2:c0:c0:0"
 200
 201 /* C1 Register Defines */
 202 #define XREG_CP15_SYS_CONTROL                   "cp15:0:c1:c0:0"
 203 #define XREG_CP15_AUX_CONTROL                   "cp15:0:c1:c0:1"
 204 #define XREG_CP15_CP_ACCESS_CONTROL             "cp15:0:c1:c0:2"
 205
 206 #define XREG_CP15_SECURE_CONFIG                 "cp15:0:c1:c1:0"
 207 #define XREG_CP15_SECURE_DEBUG_ENABLE           "cp15:0:c1:c1:1"
 208 #define XREG_CP15_NS_ACCESS_CONTROL             "cp15:0:c1:c1:2"
 209 #define XREG_CP15_VIRTUAL_CONTROL               "cp15:0:c1:c1:3"
 210 #endif
 211
 212 /* XREG_CP15_CONTROL bit defines */
 213 #define XREG_CP15_CONTROL_TE_BIT                0x40000000
 214 #define XREG_CP15_CONTROL_AFE_BIT               0x20000000
 215 #define XREG_CP15_CONTROL_TRE_BIT               0x10000000
 216 #define XREG_CP15_CONTROL_NMFI_BIT              0x08000000
 217 #define XREG_CP15_CONTROL_EE_BIT                0x02000000
 218 #define XREG_CP15_CONTROL_HA_BIT                0x00020000
 219 #define XREG_CP15_CONTROL_RR_BIT                0x00004000
 220 #define XREG_CP15_CONTROL_V_BIT                 0x00002000
 221 #define XREG_CP15_CONTROL_I_BIT                 0x00001000
 222 #define XREG_CP15_CONTROL_Z_BIT                 0x00000800
 223 #define XREG_CP15_CONTROL_SW_BIT                0x00000400
 224 #define XREG_CP15_CONTROL_B_BIT                 0x00000080
 225 #define XREG_CP15_CONTROL_C_BIT                 0x00000004
 226 #define XREG_CP15_CONTROL_A_BIT                 0x00000002
 227 #define XREG_CP15_CONTROL_M_BIT                 0x00000001
 228
 229 #if defined (__GNUC__)
 230 /* C2 Register Defines */
 231 #define XREG_CP15_TTBR0                         "p15, 0, %0,  c2,  c0, 0"
 232 #define XREG_CP15_TTBR1                         "p15, 0, %0,  c2,  c0, 1"
 233 #define XREG_CP15_TTB_CONTROL                   "p15, 0, %0,  c2,  c0, 2"
 234
 235 /* C3 Register Defines */
 236 #define XREG_CP15_DOMAIN_ACCESS_CTRL            "p15, 0, %0,  c3,  c0, 0"
 237
 238 /* C4 Register Defines */
 239 /* Not Used */
 240
 241 /* C5 Register Defines */
 242 #define XREG_CP15_DATA_FAULT_STATUS             "p15, 0, %0,  c5,  c0, 0"
 243 #define XREG_CP15_INST_FAULT_STATUS             "p15, 0, %0,  c5,  c0, 1"
 244
 245 #define XREG_CP15_AUX_DATA_FAULT_STATUS         "p15, 0, %0,  c5,  c1, 0"
 246 #define XREG_CP15_AUX_INST_FAULT_STATUS         "p15, 0, %0,  c5,  c1, 1"
 247
 248 /* C6 Register Defines */
 249 #define XREG_CP15_DATA_FAULT_ADDRESS            "p15, 0, %0,  c6,  c0, 0"
 250 #define XREG_CP15_INST_FAULT_ADDRESS            "p15, 0, %0,  c6,  c0, 2"
 251
 252 /* C7 Register Defines */
 253 #define XREG_CP15_NOP                           "p15, 0, %0,  c7,  c0, 4"
 254
 255 #define XREG_CP15_INVAL_IC_POU_IS               "p15, 0, %0,  c7,  c1, 0"
 256 #define XREG_CP15_INVAL_BRANCH_ARRAY_IS         "p15, 0, %0,  c7,  c1, 6"
 257
 258 #define XREG_CP15_PHYS_ADDR                     "p15, 0, %0,  c7,  c4, 0"
 259
 260 #define XREG_CP15_INVAL_IC_POU                  "p15, 0, %0,  c7,  c5, 0"
 261 #define XREG_CP15_INVAL_IC_LINE_MVA_POU         "p15, 0, %0,  c7,  c5, 1"
 262
 263 /* The CP15 register access below has been deprecated in favor of the new
 264  * isb instruction in Cortex A9.
 265  */
 266 #define XREG_CP15_INST_SYNC_BARRIER             "p15, 0, %0,  c7,  c5, 4"
 267 #define XREG_CP15_INVAL_BRANCH_ARRAY            "p15, 0, %0,  c7,  c5, 6"
 268
 269 #define XREG_CP15_INVAL_DC_LINE_MVA_POC         "p15, 0, %0,  c7,  c6, 1"
 270 #define XREG_CP15_INVAL_DC_LINE_SW              "p15, 0, %0,  c7,  c6, 2"
 271
 272 #define XREG_CP15_VA_TO_PA_CURRENT_0            "p15, 0, %0,  c7,  c8, 0"
 273 #define XREG_CP15_VA_TO_PA_CURRENT_1            "p15, 0, %0,  c7,  c8, 1"
 274 #define XREG_CP15_VA_TO_PA_CURRENT_2            "p15, 0, %0,  c7,  c8, 2"
 275 #define XREG_CP15_VA_TO_PA_CURRENT_3            "p15, 0, %0,  c7,  c8, 3"
 276
 277 #define XREG_CP15_VA_TO_PA_OTHER_0              "p15, 0, %0,  c7,  c8, 4"
 278 #define XREG_CP15_VA_TO_PA_OTHER_1              "p15, 0, %0,  c7,  c8, 5"
 279 #define XREG_CP15_VA_TO_PA_OTHER_2              "p15, 0, %0,  c7,  c8, 6"
 280 #define XREG_CP15_VA_TO_PA_OTHER_3              "p15, 0, %0,  c7,  c8, 7"
 281
 282 #define XREG_CP15_CLEAN_DC_LINE_MVA_POC         "p15, 0, %0,  c7, c10, 1"
 283 #define XREG_CP15_CLEAN_DC_LINE_SW              "p15, 0, %0,  c7, c10, 2"
 284
 285 /* The next two CP15 register accesses below have been deprecated in favor
 286  * of the new dsb and dmb instructions in Cortex A9.
 287  */
 288 #define XREG_CP15_DATA_SYNC_BARRIER             "p15, 0, %0,  c7, c10, 4"
 289 #define XREG_CP15_DATA_MEMORY_BARRIER           "p15, 0, %0,  c7, c10, 5"
 290
 291 #define XREG_CP15_CLEAN_DC_LINE_MVA_POU         "p15, 0, %0,  c7, c11, 1"
 292
 293 #define XREG_CP15_NOP2                          "p15, 0, %0,  c7, c13, 1"
 294
 295 #define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC   "p15, 0, %0,  c7, c14, 1"
 296 #define XREG_CP15_CLEAN_INVAL_DC_LINE_SW        "p15, 0, %0,  c7, c14, 2"
 297
 298 /* C8 Register Defines */
 299 #define XREG_CP15_INVAL_TLB_IS                  "p15, 0, %0,  c8,  c3, 0"
 300 #define XREG_CP15_INVAL_TLB_MVA_IS              "p15, 0, %0,  c8,  c3, 1"
 301 #define XREG_CP15_INVAL_TLB_ASID_IS             "p15, 0, %0,  c8,  c3, 2"
 302 #define XREG_CP15_INVAL_TLB_MVA_ASID_IS         "p15, 0, %0,  c8,  c3, 3"
 303
 304 #define XREG_CP15_INVAL_ITLB_UNLOCKED           "p15, 0, %0,  c8,  c5, 0"
 305 #define XREG_CP15_INVAL_ITLB_MVA                "p15, 0, %0,  c8,  c5, 1"
 306 #define XREG_CP15_INVAL_ITLB_ASID               "p15, 0, %0,  c8,  c5, 2"
 307
 308 #define XREG_CP15_INVAL_DTLB_UNLOCKED           "p15, 0, %0,  c8,  c6, 0"
 309 #define XREG_CP15_INVAL_DTLB_MVA                "p15, 0, %0,  c8,  c6, 1"
 310 #define XREG_CP15_INVAL_DTLB_ASID               "p15, 0, %0,  c8,  c6, 2"
 311
 312 #define XREG_CP15_INVAL_UTLB_UNLOCKED           "p15, 0, %0,  c8,  c7, 0"
 313 #define XREG_CP15_INVAL_UTLB_MVA                "p15, 0, %0,  c8,  c7, 1"
 314 #define XREG_CP15_INVAL_UTLB_ASID               "p15, 0, %0,  c8,  c7, 2"
 315 #define XREG_CP15_INVAL_UTLB_MVA_ASID           "p15, 0, %0,  c8,  c7, 3"
 316
 317 /* C9 Register Defines */
 318 #define XREG_CP15_PERF_MONITOR_CTRL             "p15, 0, %0,  c9, c12, 0"
 319 #define XREG_CP15_COUNT_ENABLE_SET              "p15, 0, %0,  c9, c12, 1"
 320 #define XREG_CP15_COUNT_ENABLE_CLR              "p15, 0, %0,  c9, c12, 2"
 321 #define XREG_CP15_V_FLAG_STATUS                 "p15, 0, %0,  c9, c12, 3"
 322 #define XREG_CP15_SW_INC                        "p15, 0, %0,  c9, c12, 4"
 323 #define XREG_CP15_EVENT_CNTR_SEL                "p15, 0, %0,  c9, c12, 5"
 324
 325 #define XREG_CP15_PERF_CYCLE_COUNTER            "p15, 0, %0,  c9, c13, 0"
 326 #define XREG_CP15_EVENT_TYPE_SEL                "p15, 0, %0,  c9, c13, 1"
 327 #define XREG_CP15_PERF_MONITOR_COUNT            "p15, 0, %0,  c9, c13, 2"
 328
 329 #define XREG_CP15_USER_ENABLE                   "p15, 0, %0,  c9, c14, 0"
 330 #define XREG_CP15_INTR_ENABLE_SET               "p15, 0, %0,  c9, c14, 1"
 331 #define XREG_CP15_INTR_ENABLE_CLR               "p15, 0, %0,  c9, c14, 2"
 332
 333 /* C10 Register Defines */
 334 #define XREG_CP15_TLB_LOCKDWN                   "p15, 0, %0, c10,  c0, 0"
 335
 336 #define XREG_CP15_PRI_MEM_REMAP                 "p15, 0, %0, c10,  c2, 0"
 337 #define XREG_CP15_NORM_MEM_REMAP                "p15, 0, %0, c10,  c2, 1"
 338
 339 /* C11 Register Defines */
 340 /* Not used */
 341
 342 /* C12 Register Defines */
 343 #define XREG_CP15_VEC_BASE_ADDR                 "p15, 0, %0, c12,  c0, 0"
 344 #define XREG_CP15_MONITOR_VEC_BASE_ADDR         "p15, 0, %0, c12,  c0, 1"
 345
 346 #define XREG_CP15_INTERRUPT_STATUS              "p15, 0, %0, c12,  c1, 0"
 347 #define XREG_CP15_VIRTUALIZATION_INTR           "p15, 0, %0, c12,  c1, 1"
 348
 349 /* C13 Register Defines */
 350 #define XREG_CP15_CONTEXT_ID                    "p15, 0, %0, c13,  c0, 1"
 351 #define USER_RW_THREAD_PID                      "p15, 0, %0, c13,  c0, 2"
 352 #define USER_RO_THREAD_PID                      "p15, 0, %0, c13,  c0, 3"
 353 #define USER_PRIV_THREAD_PID                    "p15, 0, %0, c13,  c0, 4"
 354
 355 /* C14 Register Defines */
 356 /* not used */
 357
 358 /* C15 Register Defines */
 359 #define XREG_CP15_POWER_CTRL                    "p15, 0, %0, c15,  c0, 0"
 360 #define XREG_CP15_CONFIG_BASE_ADDR              "p15, 4, %0, c15,  c0, 0"
 361
 362 #define XREG_CP15_READ_TLB_ENTRY                "p15, 5, %0, c15,  c4, 2"
 363 #define XREG_CP15_WRITE_TLB_ENTRY               "p15, 5, %0, c15,  c4, 4"
 364
 365 #define XREG_CP15_MAIN_TLB_VA                   "p15, 5, %0, c15,  c5, 2"
 366
 367 #define XREG_CP15_MAIN_TLB_PA                   "p15, 5, %0, c15,  c6, 2"
 368
 369 #define XREG_CP15_MAIN_TLB_ATTR                 "p15, 5, %0, c15,  c7, 2"
 370
 371 #else
 372 /* C2 Register Defines */
 373 #define XREG_CP15_TTBR0                         "cp15:0:c2:c0:0"
 374 #define XREG_CP15_TTBR1                         "cp15:0:c2:c0:1"
 375 #define XREG_CP15_TTB_CONTROL                   "cp15:0:c2:c0:2"
 376
 377 /* C3 Register Defines */
 378 #define XREG_CP15_DOMAIN_ACCESS_CTRL            "cp15:0:c3:c0:0"
 379
 380 /* C4 Register Defines */
 381 /* Not Used */
 382
 383 /* C5 Register Defines */
 384 #define XREG_CP15_DATA_FAULT_STATUS             "cp15:0:c5:c0:0"
 385 #define XREG_CP15_INST_FAULT_STATUS             "cp15:0:c5:c0:1"
 386
 387 #define XREG_CP15_AUX_DATA_FAULT_STATUS         "cp15:0:c5:c1:0"
 388 #define XREG_CP15_AUX_INST_FAULT_STATUS         "cp15:0:c5:c1:1"
 389
 390 /* C6 Register Defines */
 391 #define XREG_CP15_DATA_FAULT_ADDRESS            "cp15:0:c6:c0:0"
 392 #define XREG_CP15_INST_FAULT_ADDRESS            "cp15:0:c6:c0:2"
 393
 394 /* C7 Register Defines */
 395 #define XREG_CP15_NOP                           "cp15:0:c7:c0:4"
 396
 397 #define XREG_CP15_INVAL_IC_POU_IS               "cp15:0:c7:c1:0"
 398 #define XREG_CP15_INVAL_BRANCH_ARRAY_IS         "cp15:0:c7:c1:6"
 399
 400 #define XREG_CP15_PHYS_ADDR                     "cp15:0:c7:c4:0"
 401
 402 #define XREG_CP15_INVAL_IC_POU                  "cp15:0:c7:c5:0"
 403 #define XREG_CP15_INVAL_IC_LINE_MVA_POU         "cp15:0:c7:c5:1"
 404
 405 /* The CP15 register access below has been deprecated in favor of the new
 406  * isb instruction in Cortex A9.
 407  */
 408 #define XREG_CP15_INST_SYNC_BARRIER             "cp15:0:c7:c5:4"
 409 #define XREG_CP15_INVAL_BRANCH_ARRAY            "cp15:0:c7:c5:6"
 410
 411 #define XREG_CP15_INVAL_DC_LINE_MVA_POC         "cp15:0:c7:c6:1"
 412 #define XREG_CP15_INVAL_DC_LINE_SW              "cp15:0:c7:c6:2"
 413
 414 #define XREG_CP15_VA_TO_PA_CURRENT_0            "cp15:0:c7:c8:0"
 415 #define XREG_CP15_VA_TO_PA_CURRENT_1            "cp15:0:c7:c8:1"
 416 #define XREG_CP15_VA_TO_PA_CURRENT_2            "cp15:0:c7:c8:2"
 417 #define XREG_CP15_VA_TO_PA_CURRENT_3            "cp15:0:c7:c8:3"
 418
 419 #define XREG_CP15_VA_TO_PA_OTHER_0              "cp15:0:c7:c8:4"
 420 #define XREG_CP15_VA_TO_PA_OTHER_1              "cp15:0:c7:c8:5"
 421 #define XREG_CP15_VA_TO_PA_OTHER_2              "cp15:0:c7:c8:6"
 422 #define XREG_CP15_VA_TO_PA_OTHER_3              "cp15:0:c7:c8:7"
 423
 424 #define XREG_CP15_CLEAN_DC_LINE_MVA_POC         "cp15:0:c7:c10:1"
 425 #define XREG_CP15_CLEAN_DC_LINE_SW              "cp15:0:c7:c10:2"
 426
 427 /* The next two CP15 register accesses below have been deprecated in favor
 428  * of the new dsb and dmb instructions in Cortex A9.
 429  */
 430 #define XREG_CP15_DATA_SYNC_BARRIER             "cp15:0:c7:c10:4"
 431 #define XREG_CP15_DATA_MEMORY_BARRIER           "cp15:0:c7:c10:5"
 432
 433 #define XREG_CP15_CLEAN_DC_LINE_MVA_POU         "cp15:0:c7:c11:1"
 434
 435 #define XREG_CP15_NOP2                          "cp15:0:c7:c13:1"
 436
 437 #define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC   "cp15:0:c7:c14:1"
 438 #define XREG_CP15_CLEAN_INVAL_DC_LINE_SW        "cp15:0:c7:c14:2"
 439
 440 /* C8 Register Defines */
 441 #define XREG_CP15_INVAL_TLB_IS                  "cp15:0:c8:c3:0"
 442 #define XREG_CP15_INVAL_TLB_MVA_IS              "cp15:0:c8:c3:1"
 443 #define XREG_CP15_INVAL_TLB_ASID_IS             "cp15:0:c8:c3:2"
 444 #define XREG_CP15_INVAL_TLB_MVA_ASID_IS         "cp15:0:c8:c3:3"
 445
 446 #define XREG_CP15_INVAL_ITLB_UNLOCKED           "cp15:0:c8:c5:0"
 447 #define XREG_CP15_INVAL_ITLB_MVA                "cp15:0:c8:c5:1"
 448 #define XREG_CP15_INVAL_ITLB_ASID               "cp15:0:c8:c5:2"
 449
 450 #define XREG_CP15_INVAL_DTLB_UNLOCKED           "cp15:0:c8:c6:0"
 451 #define XREG_CP15_INVAL_DTLB_MVA                "cp15:0:c8:c6:1"
 452 #define XREG_CP15_INVAL_DTLB_ASID               "cp15:0:c8:c6:2"
 453
 454 #define XREG_CP15_INVAL_UTLB_UNLOCKED           "cp15:0:c8:c7:0"
 455 #define XREG_CP15_INVAL_UTLB_MVA                "cp15:0:c8:c7:1"
 456 #define XREG_CP15_INVAL_UTLB_ASID               "cp15:0:c8:c7:2"
 457 #define XREG_CP15_INVAL_UTLB_MVA_ASID           "cp15:0:c8:c7:3"
 458
 459 /* C9 Register Defines */
 460 #define XREG_CP15_PERF_MONITOR_CTRL             "cp15:0:c9:c12:0"
 461 #define XREG_CP15_COUNT_ENABLE_SET              "cp15:0:c9:c12:1"
 462 #define XREG_CP15_COUNT_ENABLE_CLR              "cp15:0:c9:c12:2"
 463 #define XREG_CP15_V_FLAG_STATUS                 "cp15:0:c9:c12:3"
 464 #define XREG_CP15_SW_INC                        "cp15:0:c9:c12:4"
 465 #define XREG_CP15_EVENT_CNTR_SEL                "cp15:0:c9:c12:5"
 466
 467 #define XREG_CP15_PERF_CYCLE_COUNTER            "cp15:0:c9:c13:0"
 468 #define XREG_CP15_EVENT_TYPE_SEL                "cp15:0:c9:c13:1"
 469 #define XREG_CP15_PERF_MONITOR_COUNT            "cp15:0:c9:c13:2"
 470
 471 #define XREG_CP15_USER_ENABLE                   "cp15:0:c9:c14:0"
 472 #define XREG_CP15_INTR_ENABLE_SET               "cp15:0:c9:c14:1"
 473 #define XREG_CP15_INTR_ENABLE_CLR               "cp15:0:c9:c14:2"
 474
 475 /* C10 Register Defines */
 476 #define XREG_CP15_TLB_LOCKDWN                   "cp15:0:c10:c0:0"
 477
 478 #define XREG_CP15_PRI_MEM_REMAP                 "cp15:0:c10:c2:0"
 479 #define XREG_CP15_NORM_MEM_REMAP                "cp15:0:c10:c2:1"
 480
 481 /* C11 Register Defines */
 482 /* Not used */
 483
 484 /* C12 Register Defines */
 485 #define XREG_CP15_VEC_BASE_ADDR                 "cp15:0:c12:c0:0"
 486 #define XREG_CP15_MONITOR_VEC_BASE_ADDR         "cp15:0:c12:c0:1"
 487
 488 #define XREG_CP15_INTERRUPT_STATUS              "cp15:0:c12:c1:0"
 489 #define XREG_CP15_VIRTUALIZATION_INTR           "cp15:0:c12:c1:1"
 490
 491 /* C13 Register Defines */
 492 #define XREG_CP15_CONTEXT_ID                    "cp15:0:c13:c0:1"
 493 #define USER_RW_THREAD_PID                      "cp15:0:c13:c0:2"
 494 #define USER_RO_THREAD_PID                      "cp15:0:c13:c0:3"
 495 #define USER_PRIV_THREAD_PID                    "cp15:0:c13:c0:4"
 496
 497 /* C14 Register Defines */
 498 /* not used */
 499
 500 /* C15 Register Defines */
 501 #define XREG_CP15_POWER_CTRL                    "cp15:0:c15:c0:0"
 502 #define XREG_CP15_CONFIG_BASE_ADDR              "cp15:4:c15:c0:0"
 503
 504 #define XREG_CP15_READ_TLB_ENTRY                "cp15:5:c15:c4:2"
 505 #define XREG_CP15_WRITE_TLB_ENTRY               "cp15:5:c15:c4:4"
 506
 507 #define XREG_CP15_MAIN_TLB_VA                   "cp15:5:c15:c5:2"
 508
 509 #define XREG_CP15_MAIN_TLB_PA                   "cp15:5:c15:c6:2"
 510
 511 #define XREG_CP15_MAIN_TLB_ATTR                 "cp15:5:c15:c7:2"
 512 #endif
 513
 514
 515 /* MPE register definitions */
 516 #define XREG_FPSID                              c0
 517 #define XREG_FPSCR                              c1
 518 #define XREG_MVFR1                              c6
 519 #define XREG_MVFR0                              c7
 520 #define XREG_FPEXC                              c8
 521 #define XREG_FPINST                             c9
 522 #define XREG_FPINST2                            c10
 523
 524 /* FPSID bits */
 525 #define XREG_FPSID_IMPLEMENTER_BIT      (24)
 526 #define XREG_FPSID_IMPLEMENTER_MASK     (0xFF << FPSID_IMPLEMENTER_BIT)
 527 #define XREG_FPSID_SOFTWARE             (1<<23)
 528 #define XREG_FPSID_ARCH_BIT             (16)
 529 #define XREG_FPSID_ARCH_MASK            (0xF  << FPSID_ARCH_BIT)
 530 #define XREG_FPSID_PART_BIT             (8)
 531 #define XREG_FPSID_PART_MASK            (0xFF << FPSID_PART_BIT)
 532 #define XREG_FPSID_VARIANT_BIT          (4)
 533 #define XREG_FPSID_VARIANT_MASK         (0xF  << FPSID_VARIANT_BIT)
 534 #define XREG_FPSID_REV_BIT              (0)
 535 #define XREG_FPSID_REV_MASK             (0xF  << FPSID_REV_BIT)
 536
 537 /* FPSCR bits */
 538 #define XREG_FPSCR_N_BIT                (1 << 31)
 539 #define XREG_FPSCR_Z_BIT                (1 << 30)
 540 #define XREG_FPSCR_C_BIT                (1 << 29)
 541 #define XREG_FPSCR_V_BIT                (1 << 28)
 542 #define XREG_FPSCR_QC                   (1 << 27)
 543 #define XREG_FPSCR_AHP                  (1 << 26)
 544 #define XREG_FPSCR_DEFAULT_NAN          (1 << 25)
 545 #define XREG_FPSCR_FLUSHTOZERO          (1 << 24)
 546 #define XREG_FPSCR_ROUND_NEAREST        (0 << 22)
 547 #define XREG_FPSCR_ROUND_PLUSINF        (1 << 22)
 548 #define XREG_FPSCR_ROUND_MINUSINF       (2 << 22)
 549 #define XREG_FPSCR_ROUND_TOZERO         (3 << 22)
 550 #define XREG_FPSCR_RMODE_BIT            (22)
 551 #define XREG_FPSCR_RMODE_MASK           (3 << FPSCR_RMODE_BIT)
 552 #define XREG_FPSCR_STRIDE_BIT           (20)
 553 #define XREG_FPSCR_STRIDE_MASK          (3 << FPSCR_STRIDE_BIT)
 554 #define XREG_FPSCR_LENGTH_BIT           (16)
 555 #define XREG_FPSCR_LENGTH_MASK          (7 << FPSCR_LENGTH_BIT)
 556 #define XREG_FPSCR_IDC                  (1 << 7)
 557 #define XREG_FPSCR_IXC                  (1 << 4)
 558 #define XREG_FPSCR_UFC                  (1 << 3)
 559 #define XREG_FPSCR_OFC                  (1 << 2)
 560 #define XREG_FPSCR_DZC                  (1 << 1)
 561 #define XREG_FPSCR_IOC                  (1 << 0)
 562
 563 /* MVFR0 bits */
 564 #define XREG_MVFR0_RMODE_BIT            (28)
 565 #define XREG_MVFR0_RMODE_MASK           (0xF << XREG_MVFR0_RMODE_BIT)
 566 #define XREG_MVFR0_SHORT_VEC_BIT        (24)
 567 #define XREG_MVFR0_SHORT_VEC_MASK       (0xF << XREG_MVFR0_SHORT_VEC_BIT)
 568 #define XREG_MVFR0_SQRT_BIT             (20)
 569 #define XREG_MVFR0_SQRT_MASK            (0xF << XREG_MVFR0_SQRT_BIT)
 570 #define XREG_MVFR0_DIVIDE_BIT           (16)
 571 #define XREG_MVFR0_DIVIDE_MASK          (0xF << XREG_MVFR0_DIVIDE_BIT)
 572 #define XREG_MVFR0_EXEC_TRAP_BIT        (12)
 573 #define XREG_MVFR0_EXEC_TRAP_MASK       (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
 574 #define XREG_MVFR0_DP_BIT               (8)
 575 #define XREG_MVFR0_DP_MASK              (0xF << XREG_MVFR0_DP_BIT)
 576 #define XREG_MVFR0_SP_BIT               (4)
 577 #define XREG_MVFR0_SP_MASK              (0xF << XREG_MVFR0_SP_BIT)
 578 #define XREG_MVFR0_A_SIMD_BIT           (0)
 579 #define XREG_MVFR0_A_SIMD_MASK          (0xF << MVFR0_A_SIMD_BIT)
 580
 581 /* FPEXC bits */
 582 #define XREG_FPEXC_EX                   (1 << 31)
 583 #define XREG_FPEXC_EN                   (1 << 30)
 584 #define XREG_FPEXC_DEX                  (1 << 29)
 585
 586
 587 #ifdef __cplusplus
 588 }
 589 #endif /* __cplusplus */
 590
 591 #endif /* XREG_CORTEXA9_H */