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43 * @file xreg_cortexa9.h
45 * This header file contains definitions for using inline assembler code. It is
46 * written specifically for the GNU, ARMCC compiler.
48 * All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
49 * with the positions of the bits within the registers.
52 * MODIFICATION HISTORY:
54 * Ver Who Date Changes
55 * ----- -------- -------- -----------------------------------------------
56 * 1.00a ecm/sdm 10/20/09 First release
59 ******************************************************************************/
60 #ifndef XREG_CORTEXA9_H
61 #define XREG_CORTEXA9_H
65 #endif /* __cplusplus */
78 #define XREG_GPR10 r10
79 #define XREG_GPR11 r11
80 #define XREG_GPR12 r12
81 #define XREG_GPR13 r13
82 #define XREG_GPR14 r14
83 #define XREG_GPR15 r15
84 #define XREG_CPSR cpsr
86 /* Coprocessor number defines */
104 /* Coprocessor control register defines */
115 #define XREG_CR10 cr10
116 #define XREG_CR11 cr11
117 #define XREG_CR12 cr12
118 #define XREG_CR13 cr13
119 #define XREG_CR14 cr14
120 #define XREG_CR15 cr15
122 /* Current Processor Status Register (CPSR) Bits */
123 #define XREG_CPSR_THUMB_MODE 0x20
124 #define XREG_CPSR_MODE_BITS 0x1F
125 #define XREG_CPSR_SYSTEM_MODE 0x1F
126 #define XREG_CPSR_UNDEFINED_MODE 0x1B
127 #define XREG_CPSR_DATA_ABORT_MODE 0x17
128 #define XREG_CPSR_SVC_MODE 0x13
129 #define XREG_CPSR_IRQ_MODE 0x12
130 #define XREG_CPSR_FIQ_MODE 0x11
131 #define XREG_CPSR_USER_MODE 0x10
133 #define XREG_CPSR_IRQ_ENABLE 0x80
134 #define XREG_CPSR_FIQ_ENABLE 0x40
136 #define XREG_CPSR_N_BIT 0x80000000
137 #define XREG_CPSR_Z_BIT 0x40000000
138 #define XREG_CPSR_C_BIT 0x20000000
139 #define XREG_CPSR_V_BIT 0x10000000
143 #if defined (__GNUC__)
144 /* C0 Register defines */
145 #define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
146 #define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
147 #define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
148 #define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
149 #define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
151 #define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
152 #define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
153 #define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
154 #define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
155 #define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
156 #define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
157 #define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
159 #define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
160 #define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
161 #define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
162 #define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
163 #define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
165 #define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
166 #define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
167 #define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
169 #define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
171 /* C1 Register Defines */
172 #define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
173 #define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
174 #define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
176 #define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
177 #define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
178 #define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
179 #define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
182 /* C0 Register defines */
183 #define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
184 #define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
185 #define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
186 #define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
187 #define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
189 #define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
190 #define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
191 #define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
192 #define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
193 #define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
194 #define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
195 #define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
197 #define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
198 #define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
199 #define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
200 #define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
201 #define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
203 #define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
204 #define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
205 #define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
207 #define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
209 /* C1 Register Defines */
210 #define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
211 #define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
212 #define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
214 #define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
215 #define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
216 #define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
217 #define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
220 /* XREG_CP15_CONTROL bit defines */
221 #define XREG_CP15_CONTROL_TE_BIT 0x40000000
222 #define XREG_CP15_CONTROL_AFE_BIT 0x20000000
223 #define XREG_CP15_CONTROL_TRE_BIT 0x10000000
224 #define XREG_CP15_CONTROL_NMFI_BIT 0x08000000
225 #define XREG_CP15_CONTROL_EE_BIT 0x02000000
226 #define XREG_CP15_CONTROL_HA_BIT 0x00020000
227 #define XREG_CP15_CONTROL_RR_BIT 0x00004000
228 #define XREG_CP15_CONTROL_V_BIT 0x00002000
229 #define XREG_CP15_CONTROL_I_BIT 0x00001000
230 #define XREG_CP15_CONTROL_Z_BIT 0x00000800
231 #define XREG_CP15_CONTROL_SW_BIT 0x00000400
232 #define XREG_CP15_CONTROL_B_BIT 0x00000080
233 #define XREG_CP15_CONTROL_C_BIT 0x00000004
234 #define XREG_CP15_CONTROL_A_BIT 0x00000002
235 #define XREG_CP15_CONTROL_M_BIT 0x00000001
237 #if defined (__GNUC__)
238 /* C2 Register Defines */
239 #define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
240 #define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
241 #define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
243 /* C3 Register Defines */
244 #define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
246 /* C4 Register Defines */
249 /* C5 Register Defines */
250 #define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
251 #define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
253 #define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
254 #define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
256 /* C6 Register Defines */
257 #define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
258 #define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
260 /* C7 Register Defines */
261 #define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
263 #define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
264 #define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
266 #define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
268 #define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
269 #define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
271 /* The CP15 register access below has been deprecated in favor of the new
272 * isb instruction in Cortex A9.
274 #define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
275 #define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
277 #define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
278 #define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
280 #define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
281 #define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
282 #define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
283 #define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
285 #define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
286 #define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
287 #define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
288 #define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
290 #define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
291 #define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
293 /* The next two CP15 register accesses below have been deprecated in favor
294 * of the new dsb and dmb instructions in Cortex A9.
296 #define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
297 #define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
299 #define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
301 #define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
303 #define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
304 #define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
306 /* C8 Register Defines */
307 #define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
308 #define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
309 #define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
310 #define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
312 #define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
313 #define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
314 #define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
316 #define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
317 #define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
318 #define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
320 #define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
321 #define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
322 #define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
323 #define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
325 /* C9 Register Defines */
326 #define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
327 #define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
328 #define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
329 #define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
330 #define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
331 #define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
333 #define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
334 #define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
335 #define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
337 #define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
338 #define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
339 #define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
341 /* C10 Register Defines */
342 #define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
344 #define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
345 #define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
347 /* C11 Register Defines */
350 /* C12 Register Defines */
351 #define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
352 #define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
354 #define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
355 #define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
357 /* C13 Register Defines */
358 #define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
359 #define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
360 #define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
361 #define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
363 /* C14 Register Defines */
366 /* C15 Register Defines */
367 #define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
368 #define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
370 #define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
371 #define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
373 #define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
375 #define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
377 #define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
380 /* C2 Register Defines */
381 #define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
382 #define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
383 #define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
385 /* C3 Register Defines */
386 #define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
388 /* C4 Register Defines */
391 /* C5 Register Defines */
392 #define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
393 #define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
395 #define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
396 #define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
398 /* C6 Register Defines */
399 #define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
400 #define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
402 /* C7 Register Defines */
403 #define XREG_CP15_NOP "cp15:0:c7:c0:4"
405 #define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
406 #define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
408 #define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
410 #define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
411 #define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
413 /* The CP15 register access below has been deprecated in favor of the new
414 * isb instruction in Cortex A9.
416 #define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
417 #define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
419 #define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
420 #define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
422 #define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
423 #define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
424 #define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
425 #define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
427 #define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
428 #define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
429 #define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
430 #define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
432 #define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
433 #define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
435 /* The next two CP15 register accesses below have been deprecated in favor
436 * of the new dsb and dmb instructions in Cortex A9.
438 #define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
439 #define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
441 #define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
443 #define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
445 #define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
446 #define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
448 /* C8 Register Defines */
449 #define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
450 #define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
451 #define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
452 #define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
454 #define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
455 #define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
456 #define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
458 #define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
459 #define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
460 #define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
462 #define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
463 #define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
464 #define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
465 #define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
467 /* C9 Register Defines */
468 #define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
469 #define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
470 #define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
471 #define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
472 #define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
473 #define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
475 #define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
476 #define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
477 #define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
479 #define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
480 #define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
481 #define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
483 /* C10 Register Defines */
484 #define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
486 #define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
487 #define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
489 /* C11 Register Defines */
492 /* C12 Register Defines */
493 #define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
494 #define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
496 #define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
497 #define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
499 /* C13 Register Defines */
500 #define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
501 #define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
502 #define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
503 #define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
505 /* C14 Register Defines */
508 /* C15 Register Defines */
509 #define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
510 #define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
512 #define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
513 #define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
515 #define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
517 #define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
519 #define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
523 /* MPE register definitions */
524 #define XREG_FPSID c0
525 #define XREG_FPSCR c1
526 #define XREG_MVFR1 c6
527 #define XREG_MVFR0 c7
528 #define XREG_FPEXC c8
529 #define XREG_FPINST c9
530 #define XREG_FPINST2 c10
533 #define XREG_FPSID_IMPLEMENTER_BIT (24)
534 #define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
535 #define XREG_FPSID_SOFTWARE (1<<23)
536 #define XREG_FPSID_ARCH_BIT (16)
537 #define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
538 #define XREG_FPSID_PART_BIT (8)
539 #define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
540 #define XREG_FPSID_VARIANT_BIT (4)
541 #define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
542 #define XREG_FPSID_REV_BIT (0)
543 #define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
546 #define XREG_FPSCR_N_BIT (1 << 31)
547 #define XREG_FPSCR_Z_BIT (1 << 30)
548 #define XREG_FPSCR_C_BIT (1 << 29)
549 #define XREG_FPSCR_V_BIT (1 << 28)
550 #define XREG_FPSCR_QC (1 << 27)
551 #define XREG_FPSCR_AHP (1 << 26)
552 #define XREG_FPSCR_DEFAULT_NAN (1 << 25)
553 #define XREG_FPSCR_FLUSHTOZERO (1 << 24)
554 #define XREG_FPSCR_ROUND_NEAREST (0 << 22)
555 #define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
556 #define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
557 #define XREG_FPSCR_ROUND_TOZERO (3 << 22)
558 #define XREG_FPSCR_RMODE_BIT (22)
559 #define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
560 #define XREG_FPSCR_STRIDE_BIT (20)
561 #define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
562 #define XREG_FPSCR_LENGTH_BIT (16)
563 #define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
564 #define XREG_FPSCR_IDC (1 << 7)
565 #define XREG_FPSCR_IXC (1 << 4)
566 #define XREG_FPSCR_UFC (1 << 3)
567 #define XREG_FPSCR_OFC (1 << 2)
568 #define XREG_FPSCR_DZC (1 << 1)
569 #define XREG_FPSCR_IOC (1 << 0)
572 #define XREG_MVFR0_RMODE_BIT (28)
573 #define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
574 #define XREG_MVFR0_SHORT_VEC_BIT (24)
575 #define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
576 #define XREG_MVFR0_SQRT_BIT (20)
577 #define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
578 #define XREG_MVFR0_DIVIDE_BIT (16)
579 #define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
580 #define XREG_MVFR0_EXEC_TRAP_BIT (12)
581 #define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
582 #define XREG_MVFR0_DP_BIT (8)
583 #define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
584 #define XREG_MVFR0_SP_BIT (4)
585 #define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
586 #define XREG_MVFR0_A_SIMD_BIT (0)
587 #define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
590 #define XREG_FPEXC_EX (1 << 31)
591 #define XREG_FPEXC_EN (1 << 30)
592 #define XREG_FPEXC_DEX (1 << 29)
597 #endif /* __cplusplus */
599 #endif /* XREG_CORTEXA9_H */