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   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32l1xx_fsmc.c\r
   4   * @author  MCD Application Team\r
   5   * @version V1.1.1\r
   6   * @date    05-March-2012\r
   7   * @brief   This file provides firmware functions to manage the following \r
   8   *          functionalities of the FSMC peripheral:\r
   9   *           + Initialization \r
  10   *           + Interrupts and flags management\r
  11   *\r
  12   ******************************************************************************\r
  13   * @attention\r
  14   *\r
  15   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>\r
  16   *\r
  17   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
  18   * You may not use this file except in compliance with the License.\r
  19   * You may obtain a copy of the License at:\r
  20   *\r
  21   *        http://www.st.com/software_license_agreement_liberty_v2\r
  22   *\r
  23   * Unless required by applicable law or agreed to in writing, software \r
  24   * distributed under the License is distributed on an "AS IS" BASIS, \r
  25   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
  26   * See the License for the specific language governing permissions and\r
  27   * limitations under the License.\r
  28   *\r
  29   ******************************************************************************\r
  30   */\r
  31 \r
  32 /* Includes ------------------------------------------------------------------*/\r
  33 #include "stm32l1xx_fsmc.h"\r
  34 #include "stm32l1xx_rcc.h"\r
  35 \r
  36 /** @addtogroup STM32L1xx_StdPeriph_Driver\r
  37   * @{\r
  38   */\r
  39 \r
  40 /** @defgroup FSMC \r
  41   * @brief FSMC driver modules\r
  42   * @{\r
  43   */ \r
  44 \r
  45 /* Private typedef -----------------------------------------------------------*/\r
  46 /* Private define ------------------------------------------------------------*/\r
  47 /* Private macro -------------------------------------------------------------*/\r
  48 /* Private variables ---------------------------------------------------------*/\r
  49 /* Private function prototypes -----------------------------------------------*/\r
  50 /* Private functions ---------------------------------------------------------*/\r
  51 \r
  52 /** @defgroup FSMC_Private_Functions\r
  53   * @{\r
  54   */\r
  55 \r
  56 /** @defgroup FSMC_Group1 NOR/SRAM Controller functions\r
  57  *  @brief   NOR/SRAM Controller functions \r
  58  *\r
  59   @verbatim\r
  60   ==============================================================================\r
  61                   ##### NOR-SRAM Controller functions #####\r
  62   ==============================================================================\r
  63     [..] The following sequence should be followed to configure the FSMC to \r
  64          interface with SRAM, PSRAM, NOR or OneNAND memory connected to the \r
  65          NOR/SRAM Bank: \r
  66     (#) Enable the clock for the FSMC and associated GPIOs using the following \r
  67         functions: \r
  68         (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); \r
  69         (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); \r
  70     (#) FSMC pins configuration  \r
  71         (++) Connect the involved FSMC pins to AF12 using the following function  \r
  72              GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);\r
  73         (++) Configure these FSMC pins in alternate function mode by calling the\r
  74              function GPIO_Init();\r
  75     (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: \r
  76         FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure; and fill the \r
  77         FSMC_NORSRAMInitStructure variable with the allowed values of the \r
  78         structure member.\r
  79     (#) Initialize the NOR/SRAM Controller by calling the function \r
  80         FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  \r
  81     (#) Then enable the NOR/SRAM Bank, for example: \r
  82         FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);   \r
  83     (#) At this stage you can read/write from/to the memory connected to the \r
  84         NOR/SRAM Bank.\r
  85    \r
  86 @endverbatim\r
  87 \r
  88   * @{\r
  89   */\r
  90 \r
  91 /**\r
  92   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
  93   *   reset values.\r
  94   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
  95   *   This parameter can be one of the following values:\r
  96   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
  97   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
  98   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
  99   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
 100   * @retval None\r
 101   */\r
 102 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
 103 {\r
 104   /* Check the parameter */\r
 105   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 106   \r
 107   /* FSMC_Bank1_NORSRAM1 */\r
 108   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
 109   {\r
 110     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    \r
 111   }\r
 112   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
 113   else\r
 114   {   \r
 115     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
 116   }\r
 117   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
 118   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  \r
 119 }\r
 120 \r
 121 /**\r
 122   * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified\r
 123   *   parameters in the FSMC_NORSRAMInitStruct.\r
 124   * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
 125   *   structure that contains the configuration information for \r
 126   *   the FSMC NOR/SRAM specified Banks.                       \r
 127   * @retval None\r
 128   */\r
 129 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 130 { \r
 131   /* Check the parameters */\r
 132   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
 133   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
 134   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
 135   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
 136   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
 137   assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
 138   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
 139   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
 140   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
 141   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
 142   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
 143   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
 144   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  \r
 145   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
 146   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
 147   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
 148   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
 149   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
 150   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
 151   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
 152   \r
 153   /* Bank1 NOR/SRAM control register configuration */ \r
 154   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 155             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
 156             FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
 157             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
 158             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
 159             FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
 160             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
 161             FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
 162             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
 163             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
 164             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
 165             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
 166             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
 167 \r
 168   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
 169   {\r
 170     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;\r
 171   }\r
 172   \r
 173   /* Bank1 NOR/SRAM timing register configuration */\r
 174   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
 175             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
 176             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
 177             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 178             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
 179             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
 180             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
 181              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
 182             \r
 183     \r
 184   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
 185   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
 186   {\r
 187     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
 188     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
 189     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
 190     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
 191     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
 192     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
 193     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 194               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
 195               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
 196               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 197               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
 198               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
 199                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
 200   }\r
 201   else\r
 202   {\r
 203     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
 204   }\r
 205 }\r
 206 \r
 207 /**\r
 208   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.\r
 209   * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
 210   *   structure which will be initialized.\r
 211   * @retval None\r
 212   */\r
 213 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 214 {  \r
 215   /* Reset NOR/SRAM Init structure parameters values */\r
 216   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
 217   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
 218   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
 219   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 220   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
 221   FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
 222   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
 223   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
 224   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
 225   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
 226   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
 227   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
 228   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
 229   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 230   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 231   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 232   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 233   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 234   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
 235   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
 236   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 237   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 238   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 239   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 240   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 241   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
 242   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
 243 }\r
 244 \r
 245 /**\r
 246   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.\r
 247   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 248   *   This parameter can be one of the following values:\r
 249   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
 250   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
 251   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
 252   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
 253   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
 254   * @retval None\r
 255   */\r
 256 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 257 {\r
 258   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 259   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 260   \r
 261   if (NewState != DISABLE)\r
 262   {\r
 263     /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */\r
 264     FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;\r
 265   }\r
 266   else\r
 267   {\r
 268     /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */\r
 269     FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);\r
 270   }\r
 271 }\r
 272 \r
 273 /**\r
 274   * @}\r
 275   */ \r
 276 \r
 277 /**\r
 278   * @}\r
 279   */\r
 280 \r
 281 /**\r
 282   * @}\r
 283   */\r
 284 \r
 285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r