4 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM4E_USART_COMPONENT_
\r
43 #define _SAM4E_USART_COMPONENT_
\r
45 /* ============================================================================= */
\r
46 /** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
\r
47 /* ============================================================================= */
\r
48 /** \addtogroup SAM4E_USART Universal Synchronous Asynchronous Receiver Transmitter */
\r
51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
52 /** \brief Usart hardware registers */
\r
54 WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
\r
55 RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
\r
56 WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
\r
57 WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
\r
58 RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
\r
59 RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
\r
60 RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
\r
61 WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
\r
62 RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
\r
63 RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
\r
64 RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
\r
66 RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
\r
67 RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
\r
69 RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
\r
70 RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
\r
71 RoReg Reserved3[36];
\r
72 RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
\r
73 RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
\r
75 RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
\r
76 RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
\r
77 RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
\r
78 RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
\r
79 RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
\r
80 RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
\r
81 RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
\r
82 RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
\r
83 WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
\r
84 RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
\r
86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
87 /* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
\r
88 #define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
\r
89 #define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
\r
90 #define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
\r
91 #define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
\r
92 #define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
\r
93 #define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
\r
94 #define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
\r
95 #define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
\r
96 #define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
\r
97 #define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
\r
98 #define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
\r
99 #define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
\r
100 #define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
\r
101 #define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
\r
102 #define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
\r
103 #define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
\r
104 #define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
\r
105 #define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
\r
106 #define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
\r
107 #define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
\r
108 /* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
\r
109 #define US_MR_USART_MODE_Pos 0
\r
110 #define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
\r
111 #define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
\r
112 #define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
\r
113 #define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
\r
114 #define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
\r
115 #define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
\r
116 #define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
\r
117 #define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
\r
118 #define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
\r
119 #define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
\r
120 #define US_MR_USCLKS_Pos 4
\r
121 #define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
\r
122 #define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
\r
123 #define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
\r
124 #define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
\r
125 #define US_MR_CHRL_Pos 6
\r
126 #define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
\r
127 #define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
\r
128 #define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
\r
129 #define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
\r
130 #define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
\r
131 #define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
\r
132 #define US_MR_PAR_Pos 9
\r
133 #define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
\r
134 #define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
\r
135 #define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
\r
136 #define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
\r
137 #define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
\r
138 #define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
\r
139 #define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
\r
140 #define US_MR_NBSTOP_Pos 12
\r
141 #define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
\r
142 #define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
\r
143 #define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
\r
144 #define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
\r
145 #define US_MR_CHMODE_Pos 14
\r
146 #define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
\r
147 #define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
\r
148 #define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
\r
149 #define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
\r
150 #define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
\r
151 #define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
\r
152 #define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
\r
153 #define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
\r
154 #define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
\r
155 #define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
\r
156 #define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
\r
157 #define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
\r
158 #define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */
\r
159 #define US_MR_MAX_ITERATION_Pos 24
\r
160 #define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */
\r
161 #define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
\r
162 #define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
\r
163 #define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
\r
164 #define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
\r
165 #define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
\r
166 #define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
\r
167 #define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
\r
168 #define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */
\r
169 /* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
\r
170 #define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
\r
171 #define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
\r
172 #define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
\r
173 #define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */
\r
174 #define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */
\r
175 #define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
\r
176 #define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
\r
177 #define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
\r
178 #define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
\r
179 #define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
\r
180 #define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */
\r
181 #define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */
\r
182 #define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */
\r
183 #define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
\r
184 #define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
\r
185 #define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
\r
186 #define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
\r
187 #define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
\r
188 #define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
\r
189 #define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
\r
190 /* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
\r
191 #define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
\r
192 #define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
\r
193 #define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
\r
194 #define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */
\r
195 #define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */
\r
196 #define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
\r
197 #define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
\r
198 #define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
\r
199 #define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
\r
200 #define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
\r
201 #define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */
\r
202 #define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */
\r
203 #define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */
\r
204 #define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
\r
205 #define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
\r
206 #define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
\r
207 #define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
\r
208 #define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
\r
209 #define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
\r
210 #define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
\r
211 /* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
\r
212 #define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
\r
213 #define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
\r
214 #define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
\r
215 #define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */
\r
216 #define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */
\r
217 #define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
\r
218 #define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
\r
219 #define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
\r
220 #define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
\r
221 #define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
\r
222 #define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */
\r
223 #define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */
\r
224 #define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */
\r
225 #define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
\r
226 #define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
\r
227 #define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
\r
228 #define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
\r
229 #define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
\r
230 #define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
\r
231 #define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
\r
232 /* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
\r
233 #define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
\r
234 #define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
\r
235 #define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
\r
236 #define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
\r
237 #define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
\r
238 #define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
\r
239 #define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
\r
240 #define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
\r
241 #define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
\r
242 #define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
\r
243 #define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) MaxNumber of Repetitions Reached */
\r
244 #define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
\r
245 #define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
\r
246 #define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
\r
247 #define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
\r
248 #define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
\r
249 #define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
\r
250 #define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
\r
251 #define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
\r
252 #define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
\r
253 #define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
\r
254 #define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
\r
255 #define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
\r
256 #define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */
\r
257 /* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
\r
258 #define US_RHR_RXCHR_Pos 0
\r
259 #define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
\r
260 #define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
\r
261 /* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
\r
262 #define US_THR_TXCHR_Pos 0
\r
263 #define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
\r
264 #define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
\r
265 #define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */
\r
266 /* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
\r
267 #define US_BRGR_CD_Pos 0
\r
268 #define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
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269 #define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
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270 #define US_BRGR_FP_Pos 16
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271 #define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
\r
272 #define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
\r
273 /* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
\r
274 #define US_RTOR_TO_Pos 0
\r
275 #define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
\r
276 #define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
\r
277 /* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
\r
278 #define US_TTGR_TG_Pos 0
\r
279 #define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
\r
280 #define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
\r
281 /* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
\r
282 #define US_FIDI_FI_DI_RATIO_Pos 0
\r
283 #define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
\r
284 #define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
\r
285 /* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
\r
286 #define US_NER_NB_ERRORS_Pos 0
\r
287 #define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
\r
288 /* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
\r
289 #define US_IF_IRDA_FILTER_Pos 0
\r
290 #define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
\r
291 #define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
\r
292 /* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
\r
293 #define US_MAN_TX_PL_Pos 0
\r
294 #define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
\r
295 #define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
\r
296 #define US_MAN_TX_PP_Pos 8
\r
297 #define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
\r
298 #define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
\r
299 #define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
\r
300 #define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
\r
301 #define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
\r
302 #define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
\r
303 #define US_MAN_RX_PL_Pos 16
\r
304 #define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
\r
305 #define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
\r
306 #define US_MAN_RX_PP_Pos 24
\r
307 #define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
\r
308 #define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
\r
309 #define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
\r
310 #define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
\r
311 #define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
\r
312 #define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
\r
313 #define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */
\r
314 #define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */
\r
315 /* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
\r
316 #define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
\r
317 #define US_WPMR_WPKEY_Pos 8
\r
318 #define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
\r
319 #define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
\r
320 /* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
\r
321 #define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
\r
322 #define US_WPSR_WPVSRC_Pos 8
\r
323 #define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
\r
324 /* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
\r
325 #define US_RPR_RXPTR_Pos 0
\r
326 #define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
\r
327 #define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
\r
328 /* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
\r
329 #define US_RCR_RXCTR_Pos 0
\r
330 #define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
\r
331 #define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
\r
332 /* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
\r
333 #define US_TPR_TXPTR_Pos 0
\r
334 #define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
\r
335 #define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
\r
336 /* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
\r
337 #define US_TCR_TXCTR_Pos 0
\r
338 #define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
\r
339 #define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
\r
340 /* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
\r
341 #define US_RNPR_RXNPTR_Pos 0
\r
342 #define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
\r
343 #define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
\r
344 /* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
\r
345 #define US_RNCR_RXNCTR_Pos 0
\r
346 #define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
\r
347 #define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
\r
348 /* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
\r
349 #define US_TNPR_TXNPTR_Pos 0
\r
350 #define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
\r
351 #define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
\r
352 /* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
\r
353 #define US_TNCR_TXNCTR_Pos 0
\r
354 #define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
\r
355 #define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
\r
356 /* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
\r
357 #define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
\r
358 #define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
\r
359 #define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
\r
360 #define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
\r
361 /* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
\r
362 #define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
\r
363 #define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
\r
368 #endif /* _SAM4E_USART_COMPONENT_ */
\r
projects / freertos / blob