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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32
  33 /*****************************************************************************/
  34 /**
  35 *
  36 * @file xcsudma.c
  37 *
  38 * This file contains the implementation of the interface functions for CSU_DMA
  39 * driver. Refer to the header file xcsudma.h for more detailed information.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who     Date     Changes
  45 * ----- ------  -------- ---------------------------------------------------
  46 * 1.0   vnsld   22/10/14 First release
  47 * </pre>
  48 *
  49 ******************************************************************************/
  50
  51 /***************************** Include Files *********************************/
  52
  53 #include "xcsudma.h"
  54
  55 /************************** Function Prototypes ******************************/
  56
  57
  58 /************************** Function Definitions *****************************/
  59
  60 /*****************************************************************************/
  61 /**
  62 *
  63 * This function initializes an CSU_DMA core. This function must be called
  64 * prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting
  65 * up the instance data and ensuring the hardware is in a quiescent state.
  66 *
  67 * @param        InstancePtr is a pointer to the XCsuDma instance.
  68 * @param        CfgPtr is a reference to a structure containing information
  69 *               about a specific XCsuDma instance.
  70 * @param        EffectiveAddr is the device base address in the virtual memory
  71 *               address space. The caller is responsible for keeping the
  72 *               address mapping from EffectiveAddr to the device physical
  73 *               base address unchanged once this function is invoked.
  74 *               Unexpected errors may occur if the address mapping changes
  75 *               after this function is called. If address translation is not
  76 *               used, pass in the physical address instead.
  77 *
  78 * @return
  79 *               - XST_SUCCESS if initialization was successful.
  80 *
  81 * @note         None.
  82 *
  83 ******************************************************************************/
  84 s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
  85                         u32 EffectiveAddr)
  86 {
  87
  88         /* Verify arguments. */
  89         Xil_AssertNonvoid(InstancePtr != NULL);
  90         Xil_AssertNonvoid(CfgPtr != NULL);
  91         Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
  92
  93         /* Setup the instance */
  94         (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
  95                                                 sizeof(XCsuDma_Config));
  96         InstancePtr->Config.BaseAddress = EffectiveAddr;
  97
  98         XCsuDma_Reset();
  99
 100         InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
 101
 102         return (XST_SUCCESS);
 103
 104 }
 105
 106 /*****************************************************************************/
 107 /**
 108 *
 109 * This function sets the starting address and amount(size) of the data to be
 110 * transfered from/to the memory through the AXI interface.
 111 *
 112 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 113 * @param        Channel represents the type of channel either it is Source or
 114 *               Destination.
 115 *               Source channel      - XCSUDMA_SRC_CHANNEL
 116 *               Destination Channel - XCSUDMA_DST_CHANNEL
 117 * @param        Addr is a 64 bit variable which holds the starting address of
 118 *               data which needs to write into the memory(DST) (or read from
 119 *               the memory(SRC)).
 120 * @param        Size is a 32 bit variable which represents the number of 4 byte
 121 *               words needs to be transfered from starting address.
 122 * @param        EnDataLast is to trigger an end of message. It will enable or
 123 *               disable data_inp_last signal to stream interface when current
 124 *               command is completed. It is applicable only to source channel
 125 *               and neglected for destination channel.
 126 *               -       1 - Asserts data_inp_last signal.
 127 *               -       0 - data_inp_last will not be asserted.
 128 *
 129 * @return       None.
 130 *
 131 * @note         Data_inp_last signal is asserted simultaneously with the
 132 *               data_inp_valid signal associated with the final 32-bit word
 133 *               transfer.
 134 *
 135 ******************************************************************************/
 136 void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 137                                         UINTPTR Addr, u32 Size, u8 EnDataLast)
 138 {
 139         /* Verify arguments */
 140         Xil_AssertVoid(InstancePtr != NULL);
 141         Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00);
 142         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 143                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 144         Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
 145         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 146
 147         /* Flushing cache memory */
 148         if (Channel == (XCSUDMA_SRC_CHANNEL)) {
 149                 Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
 150         }
 151         /* Invalidating cache memory */
 152         else {
 153                 Xil_DCacheInvalidateRange(Addr, Size <<
 154                                         (u32)(XCSUDMA_SIZE_SHIFT));
 155         }
 156
 157         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 158                 ((u32)(XCSUDMA_ADDR_OFFSET) +
 159                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 160                                 ((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK)));
 161
 162         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 163                 ((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
 164                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 165                 (((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) &
 166                                         (u32)(XCSUDMA_MSB_ADDR_MASK)));
 167
 168         if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
 169                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 170                         ((u32)(XCSUDMA_SIZE_OFFSET) +
 171                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 172                         ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
 173                                         (u32)(XCSUDMA_LAST_WORD_MASK)));
 174         }
 175         else {
 176                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 177                         ((u32)(XCSUDMA_SIZE_OFFSET) +
 178                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 179                                 (Size << (u32)(XCSUDMA_SIZE_SHIFT)));
 180         }
 181 }
 182
 183 /*****************************************************************************/
 184 /**
 185 *
 186 * This function returns the current address location of the memory, from where
 187 * it has to read the data(SRC) or the location where it has to write the data
 188 * (DST) based on the channel selection.
 189 *
 190 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 191 * @param        Channel represents the type of channel either it is Source or
 192 *               Destination.
 193 *               Source channel      - XCSUDMA_SRC_CHANNEL
 194 *               Destination Channel - XCSUDMA_DST_CHANNEL
 195 *
 196 * @return       Address is a 64 bit variable which holds the current address.
 197 *               - From this location data has to be read(SRC)
 198 *               - At this location data has to be written(DST)
 199 *
 200 * @note         None.
 201 *
 202 ******************************************************************************/
 203 u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 204 {
 205         u64 FullAddr;
 206
 207         /* Verify arguments */
 208         Xil_AssertNonvoid(InstancePtr != NULL);
 209         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 210                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 211
 212         FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 213                                 ((u32)(XCSUDMA_ADDR_OFFSET) +
 214                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 215
 216         FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 217                         ((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
 218                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) <<
 219                                 (u64)(XCSUDMA_MSB_ADDR_SHIFT));
 220
 221         return FullAddr;
 222 }
 223
 224 /*****************************************************************************/
 225 /**
 226 *
 227 * This function returns the size of the data yet to be transfered from memory
 228 * to CSU_DMA or CSU_DMA to memory based on the channel selection.
 229 *
 230 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 231 * @param        Channel represents the type of channel either it is Source or
 232 *               Destination.
 233 *               Source channel      - XCSUDMA_SRC_CHANNEL
 234 *               Destination Channel - XCSUDMA_DST_CHANNEL
 235 *
 236 * @return       Size is amount of data yet to be transfered.
 237 *
 238 * @note         None.
 239 *
 240 ******************************************************************************/
 241 u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 242 {
 243         u32 Size;
 244
 245         /* Verify arguments. */
 246         Xil_AssertNonvoid(InstancePtr != NULL);
 247         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 248                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 249
 250         Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 251                 ((u32)(XCSUDMA_SIZE_OFFSET) +
 252                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >>
 253                                         (u32)(XCSUDMA_SIZE_SHIFT);
 254
 255         return Size;
 256 }
 257
 258 /*****************************************************************************/
 259 /**
 260 *
 261 * This function pause the Channel data tranfer to/from memory or to/from stream
 262 * based on pause type.
 263 *
 264 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 265 * @param        Channel represents the type of channel either it is Source or
 266 *               Destination.
 267 *               Source channel      - XCSUDMA_SRC_CHANNEL
 268 *               Destination Channel - XCSUDMA_DST_CHANNEL
 269 * @param        Type is type of the pause to be enabled.
 270 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 271 *                       - SRC Stops issuing of new read commands to memory.
 272 *                       - DST Stops issuing of new write commands to memory.
 273 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 274 *                       - SRC Stops transfer of data from FIFO to Stream.
 275 *                       - DST Stops transfer of data from stream to FIFO.
 276 *
 277 * @return       None.
 278 *
 279 * @note         None.
 280 *
 281 ******************************************************************************/
 282 void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 283                                                 XCsuDma_PauseType Type)
 284 {
 285         /* Verify arguments. */
 286         Xil_AssertVoid(InstancePtr != NULL);
 287         Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 288                                 (Type == (XCSUDMA_PAUSE_STREAM)));
 289         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 290                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 291         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 292
 293         /* Pause Memory Read/Write/Stream operations */
 294         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 295                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 296                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 297                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 298                         (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 299                                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 300                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) |
 301                                         (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)));
 302         }
 303         if (Type == (XCSUDMA_PAUSE_STREAM)) {
 304                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 305                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 306                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 307                         (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 308                                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 309                                 (Channel * (u32)XCSUDMA_OFFSET_DIFF))) |
 310                                 (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)));
 311         }
 312 }
 313
 314 /*****************************************************************************/
 315 /**
 316 *
 317 * This functions checks whether Channel's memory or stream is paused or not
 318 * based on the given pause type.
 319 *
 320 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 321 * @param        Channel represents the type of channel either it is Source or
 322 *               Destination.
 323 *               Source channel      - XCSUDMA_SRC_CHANNEL
 324 *               Destination Channel - XCSUDMA_DST_CHANNEL
 325 * @param        Type is type of the pause which needs to be checked.
 326 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 327 *                       - SRC Stops issuing of new read commands to memory.
 328 *                       - DST Stops issuing of new write commands to memory.
 329 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 330 *                       - SRC Stops transfer of data from FIFO to Stream.
 331 *                       - DST Stops transfer of data from stream to FIFO.
 332 *
 333 * @return       Returns the pause status.
 334 *               - TRUE if it is in paused state.
 335 *               - FALSE if it is not in pause state.
 336 *
 337 * @note         None.
 338 *
 339 ******************************************************************************/
 340 s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 341                 XCsuDma_PauseType Type)
 342 {
 343
 344         u32 Data;
 345         s32 PauseState;
 346
 347         /* Verify arguments. */
 348         Xil_AssertNonvoid(InstancePtr != NULL);
 349         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 350                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 351         Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 352                                         (Type == (XCSUDMA_PAUSE_STREAM)));
 353
 354         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 355                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 356                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 357
 358         /* To know Pause condition of Memory Read/Write/Stream operations */
 359         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 360                 if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) ==
 361                                                                 (u32)0x00) {
 362                         PauseState = (s32)(FALSE);
 363                 }
 364                 else {
 365                         PauseState = (s32)(TRUE);
 366                 }
 367         }
 368         else {
 369                 if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) ==
 370                                                                 (u32)0x00) {
 371                                 PauseState = (s32)(FALSE);
 372                 }
 373                 else {
 374                         PauseState = (s32)(TRUE);
 375                 }
 376         }
 377
 378         return (s32)PauseState;
 379
 380 }
 381
 382 /*****************************************************************************/
 383 /**
 384 *
 385 * This function resumes the channel if it is in paused state and continues
 386 * where it has left or no effect if it is not in paused state, based on the
 387 * type of pause.
 388 *
 389 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 390 * @param        Channel represents the type of channel either it is Source or
 391 *               Destination.
 392 *               Source channel      - XCSUDMA_SRC_CHANNEL
 393 *               Destination Channel - XCSUDMA_DST_CHANNEL
 394 * @param        Type is type of the pause to be Resume if it is in pause
 395 *               state.
 396 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 397 *                       - SRC Stops issuing of new read commands to memory.
 398 *                       - DST Stops issuing of new write commands to memory.
 399 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 400 *                       - SRC Stops transfer of data from FIFO to Stream.
 401 *                       - DST Stops transfer of data from stream to FIFO.
 402 *
 403 * @return       None.
 404 *
 405 * @note         None.
 406 *
 407 ******************************************************************************/
 408 void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 409                 XCsuDma_PauseType Type)
 410 {
 411         u32 Data;
 412         /* Verify arguments. */
 413         Xil_AssertVoid(InstancePtr != NULL);
 414         Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 415                         (Type == (XCSUDMA_PAUSE_STREAM)));
 416         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 417                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 418         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 419
 420         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 421                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 422                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 423
 424         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 425                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 426                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 427                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 428                 (Data &
 429                                 (~(XCSUDMA_CTRL_PAUSE_MEM_MASK))));
 430         }
 431         if (Type == (XCSUDMA_PAUSE_STREAM)) {
 432                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 433                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 434                 (((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))),
 435                         ( Data &
 436                         (~(XCSUDMA_CTRL_PAUSE_STRM_MASK))));
 437         }
 438 }
 439
 440 /*****************************************************************************/
 441 /**
 442 *
 443 * This function returns the sum of all the data read from AXI memory. It is
 444 * valid only one we use CSU_DMA source channel.
 445 *
 446 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 447 *
 448 * @return       Returns the sum of all the data read from memory.
 449 *
 450 * @note         Before start of the transfer need to clear this register to get
 451 *               correct sum otherwise it adds to previous value which results
 452 *               to wrong output.
 453 *               Valid only for source channel
 454 *
 455 ******************************************************************************/
 456 u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr)
 457 {
 458         u32 ChkSum;
 459
 460         /* Verify arguments. */
 461         Xil_AssertNonvoid(InstancePtr != NULL);
 462         Xil_AssertNonvoid(InstancePtr->IsReady ==
 463                                 (u32)(XIL_COMPONENT_IS_READY));
 464
 465         ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 466                                                 (u32)(XCSUDMA_CRC_OFFSET));
 467
 468         return ChkSum;
 469
 470 }
 471 /*****************************************************************************/
 472 /**
 473 *
 474 * This function clears the check sum of the data read from AXI memory. It is
 475 * valid only for CSU_DMA source channel.
 476 *
 477 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 478 *
 479 * @return       Returns the sum of all the data read from memory.
 480 *
 481 * @note         Before start of the transfer need to clear this register to get
 482 *               correct sum otherwise it adds to previous value which results
 483 *               to wrong output.
 484 *
 485 ******************************************************************************/
 486 void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr)
 487 {
 488
 489         /* Verify arguments. */
 490         Xil_AssertVoid(InstancePtr != NULL);
 491
 492         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 493                 (u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK));
 494 }
 495
 496 /*****************************************************************************/
 497 /**
 498 * This function cofigures all the values of CSU_DMA's Channels with the values
 499 * of updated XCsuDma_Configure structure.
 500 *
 501 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 502 * @param        Channel represents the type of channel either it is Source or
 503 *               Destination.
 504 *               Source channel      - XCSUDMA_SRC_CHANNEL
 505 *               Destination Channel - XCSUDMA_DST_CHANNEL
 506 * @param        ConfigurValues is a pointer to the structure XCsuDma_Configure
 507 *               whose values are used to configure CSU_DMA core.
 508 *               - SssFifoThesh   When the DST FIFO level >= this value,
 509 *                 the SSS interface signal, "data_out_fifo_level_hit" will be
 510 *                 asserted. This mechanism can be used by the SSS to flow
 511 *                 control data that is being looped back from the SRC DMA.
 512 *                       - Range is (0x10 to 0x7A) threshold is 17 to 123
 513 *                       entries.
 514 *                       - It is valid only for DST CSU_DMA IP.
 515 *               - ApbErr          When accessed to invalid APB the resulting
 516 *                 pslerr will be
 517 *                       - 0 - 1'b0
 518 *                       - 1 - 1'b1
 519 *               - EndianType      Type of endianness
 520 *                       - 0 doesn't change order
 521 *                       - 1 will flip the order.
 522 *               - AxiBurstType....Type of the burst
 523 *                       - 0 will issue INCR type burst
 524 *                       - 1 will issue FIXED type burst
 525 *               - TimeoutValue    Time out value for timers
 526 *                       - 0x000 to 0xFFE are valid inputs
 527 *                       - 0xFFF clears both timers
 528 *               - FifoThresh......Programmed watermark value
 529 *                       - Range is 0x00 to 0x80 (0 to 128 entries).
 530 *               - Acache         Sets the AXI CACHE bits on the AXI Write/Read
 531 *               channel.
 532 *                       - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
 533 *                         for DST channel are always 1, we need to configure
 534 *                         remaining 3 signal support
 535 *                         (Bufferable, Read allocate and Write allocate).
 536 *                       Valid inputs are:
 537 *                       - 0x000 - Cacheable, but do not allocate
 538 *                       - 0x001 - Cacheable and bufferable, but do not allocate
 539 *                       - 0x010 - Cacheable write-through, allocate on reads
 540 *                                 only
 541 *                       - 0x011 - Cacheable write-back, allocate on reads only
 542 *                       - 0x100 - Cacheable write-through, allocate on writes
 543 *                                 only
 544 *                       - 0x101 - Cacheable write-back, allocate on writes only
 545 *                       - 0x110 - Cacheable write-through, allocate on both
 546 *                                 reads and writes
 547 *                       - 0x111 - Cacheable write-back, allocate on both reads
 548 *                                 and writes
 549 *               - RouteBit        To select route
 550 *                       - 0 : Command will be routed normally
 551 *                       - 1 : Command will be routed to APU's cache controller
 552 *               - TimeoutEn       To enable or disable time out counters
 553 *                       - 0 : The 2 Timeout counters are disabled
 554 *                       - 1 : The 2 Timeout counters are enabled
 555 *               - TimeoutPre      Set the prescaler value for the timeout in
 556 *               clk (~2.5ns) cycles
 557 *                       - Range is 0x000(Prescaler enables timer every cycles)
 558 *                         to 0xFFF(Prescaler enables timer every 4096 cycles)
 559 *               - MaxOutCmds      Controls the maximumum number of outstanding
 560 *               AXI read commands issued.
 561 *                       - Range is 0x0(Up to 1 Outstanding Read command
 562 *                         allowed) to 0x8 (Up to 9 Outstanding Read
 563 *                         command allowed)
 564 *
 565 * @return       None.
 566 *
 567 * @note         To use timers timeout value Timeout enable field should be
 568 *               enabled.
 569 *
 570 ******************************************************************************/
 571 void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 572                                         XCsuDma_Configure *ConfigurValues)
 573 {
 574         u32 Data;
 575
 576         /* Verify arguments. */
 577         Xil_AssertVoid(InstancePtr != NULL);
 578         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 579         Xil_AssertVoid(ConfigurValues != NULL);
 580         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 581                                 (Channel == (XCSUDMA_DST_CHANNEL)));
 582         Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE));
 583
 584         Data = (((ConfigurValues->EndianType <<
 585                         (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
 586                         (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) |
 587                 ((ConfigurValues->ApbErr <<
 588                         (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) &
 589                         (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) |
 590                 ((ConfigurValues->AxiBurstType <<
 591                         (u32)(XCSUDMA_CTRL_BURST_SHIFT)) &
 592                         (u32)(XCSUDMA_CTRL_BURST_MASK)) |
 593                 ((ConfigurValues->TimeoutValue <<
 594                         (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) &
 595                         (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) |
 596                 ((ConfigurValues->FifoThresh <<
 597                         (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) &
 598                         (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)));
 599         if(Channel == XCSUDMA_DST_CHANNEL) {
 600                 Data = Data | (u32)((ConfigurValues->SssFifoThesh <<
 601                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) &
 602                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK));
 603         }
 604
 605         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 606                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 607                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
 608
 609         Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 610                         ((u32)(XCSUDMA_CTRL2_OFFSET) +
 611                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) &
 612                                 (u32)(XCSUDMA_CTRL2_RESERVED_MASK));
 613         Data |= (((ConfigurValues->Acache <<
 614                         (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) &
 615                         (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) |
 616                 ((ConfigurValues->RouteBit <<
 617                         (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) &
 618                         (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) |
 619                 ((ConfigurValues->TimeoutEn <<
 620                         (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) &
 621                         (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) |
 622                 ((ConfigurValues->TimeoutPre <<
 623                         (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) &
 624                         (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) |
 625                 ((ConfigurValues->MaxOutCmds) &
 626                         (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
 627
 628         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 629                 ((u32)(XCSUDMA_CTRL2_OFFSET) +
 630                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
 631 }
 632
 633 /*****************************************************************************/
 634 /**
 635 *
 636 * This function updates XCsuDma_Configure structure members with the cofigured
 637 * values of CSU_DMA's Channel.
 638 *
 639 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 640 * @param        Channel represents the type of channel either it is Source or
 641 *               Destination.
 642 *               Source channel      - XCSUDMA_SRC_CHANNEL
 643 *               Destination Channel - XCSUDMA_DST_CHANNEL
 644 * @param        ConfigurValues is a pointer to the structure XCsuDma_Configure
 645 *               whose members are updated with configurations of CSU_DMA core.
 646 *               - SssFifoThesh   When the DST FIFO level >= this value,
 647 *                 the SSS interface signal, "data_out_fifo_level_hit" will be
 648 *                 asserted. This mechanism can be used by the SSS to flow
 649 *                 control data that is being looped back from the SRC DMA.
 650 *                       - Range is (0x10 to 0x7A) threshold is 17 to 123
 651 *                       entries.
 652 *                       - It is valid only for DST CSU_DMA IP.
 653 *               - ApbErr          When accessed to invalid APB the resulting
 654 *                 pslerr will be
 655 *                       - 0 - 1'b0
 656 *                       - 1 - 1'b1
 657 *               - EndianType      Type of endianness
 658 *                       - 0 doesn't change order
 659 *                       - 1 will flip the order.
 660 *               - AxiBurstType....Type of the burst
 661 *                       - 0 will issue INCR type burst
 662 *                       - 1 will issue FIXED type burst
 663 *               - TimeoutValue    Time out value for timers
 664 *                       - 0x000 to 0xFFE are valid inputs
 665 *                       - 0xFFF clears both timers
 666 *               - FifoThresh......Programmed watermark value
 667 *                       - Range is 0x00 to 0x80 (0 to 128 entries).
 668 *               - Acache         Sets the AXI CACHE bits on the AXI Write/Read
 669 *               channel.
 670 *                       - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
 671 *                         for DST channel are always 1, we need to configure
 672 *                         remaining 3 signal support
 673 *                         (Bufferable, Read allocate and Write allocate).
 674 *                       Valid inputs are:
 675 *                       - 0x000 - Cacheable, but do not allocate
 676 *                       - 0x001 - Cacheable and bufferable, but do not allocate
 677 *                       - 0x010 - Cacheable write-through, allocate on reads
 678 *                                 only
 679 *                       - 0x011 - Cacheable write-back, allocate on reads only
 680 *                       - 0x100 - Cacheable write-through, allocate on writes
 681 *                                 only
 682 *                       - 0x101 - Cacheable write-back, allocate on writes only
 683 *                       - 0x110 - Cacheable write-through, allocate on both
 684 *                                 reads and writes
 685 *                       - 0x111 - Cacheable write-back, allocate on both reads
 686 *                                 and writes
 687 *               - RouteBit        To select route
 688 *                       - 0 : Command will be routed based normally
 689 *                       - 1 : Command will be routed to APU's cache controller
 690 *               - TimeoutEn       To enable or disable time out counters
 691 *                       - 0 : The 2 Timeout counters are disabled
 692 *                       - 1 : The 2 Timeout counters are enabled
 693 *               - TimeoutPre      Set the prescaler value for the timeout in
 694 *               clk (~2.5ns) cycles
 695 *                       - Range is 0x000(Prescaler enables timer every cycles)
 696 *                        to 0xFFF(Prescaler enables timer every 4096 cycles)
 697 *               - MaxOutCmds      Controls the maximumum number of outstanding
 698 *               AXI read commands issued.
 699 *                       - Range is 0x0(Up to 1 Outstanding Read command
 700 *                       allowed) to 0x8 (Up to 9 Outstanding Read command
 701 *                       allowed)
 702 *
 703 * @return       None.
 704 *
 705 * @note         None.
 706 *
 707 ******************************************************************************/
 708 void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 709                                 XCsuDma_Configure *ConfigurValues)
 710 {
 711         u32 Data;
 712
 713         /* Verify arguments. */
 714         Xil_AssertVoid(InstancePtr != NULL);
 715         Xil_AssertVoid(ConfigurValues != NULL);
 716         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 717                                 (Channel == (XCSUDMA_DST_CHANNEL)));
 718
 719         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 720                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 721                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 722
 723         if (Channel == (XCSUDMA_DST_CHANNEL)) {
 724                 ConfigurValues->SssFifoThesh =
 725                         (u8)((Data &
 726                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >>
 727                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT));
 728         }
 729         ConfigurValues->ApbErr =
 730                 (u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >>
 731                                 (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT));
 732         ConfigurValues->EndianType =
 733                 (u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >>
 734                                 (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT));
 735         ConfigurValues->AxiBurstType =
 736                 (u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >>
 737                                 (u32)(XCSUDMA_CTRL_BURST_SHIFT));
 738         ConfigurValues->TimeoutValue =
 739                 ((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >>
 740                                 (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT));
 741         ConfigurValues->FifoThresh =
 742                 (u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >>
 743                                 (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT));
 744
 745         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 746                         ((u32)(XCSUDMA_CTRL2_OFFSET) +
 747                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 748
 749         ConfigurValues->Acache =
 750                         (u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >>
 751                                         (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT));
 752         ConfigurValues->RouteBit =
 753                         (u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >>
 754                                         (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT));
 755         ConfigurValues->TimeoutEn =
 756                         (u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >>
 757                                 (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT));
 758         ConfigurValues->TimeoutPre =
 759                         (u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >>
 760                                 (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT));
 761         ConfigurValues->MaxOutCmds =
 762                         (u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
 763
 764 }