1 //////////////////////////////////////////////////////////////////////
3 // Copyright (c) 2004-11 Xilinx, Inc. All rights reserved.
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14 // ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
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16 // AND FITNESS FOR A PARTICULAR PURPOSE.
18 // $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
20 // _program_timer_hw.h:
21 // Timer related functions
23 //////////////////////////////////////////////////////////////////////
25 #ifndef _PROFILE_TIMER_HW_H
26 #define _PROFILE_TIMER_HW_H
32 # define SYNCHRONIZE_IO __asm__ volatile ("eieio")
34 # define SYNCHRONIZE_IO __asm volatile(" eieio")
36 # define SYNCHRONIZE_IO
41 #define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
42 #define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
44 #define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
45 #define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
48 #define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
49 ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
50 (RegOffset)), (ValueToWrite))
52 #define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
53 ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
55 #define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
56 ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
59 #define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
60 ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
69 #include "xexception_l.h"
71 #include "xpseudo_asm.h"
74 #ifdef TIMER_CONNECT_INTC
77 #endif // TIMER_CONNECT_INTC
79 #if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
80 #include "xtmrctr_l.h"
84 #include "xscutimer_hw.h"
88 extern unsigned int timer_clk_ticks ;
90 //--------------------------------------------------------------------
91 // PowerPC Target - Timer related functions
92 //--------------------------------------------------------------------
95 #ifdef PPC_PIT_INTERRUPT
96 unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
100 #define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
101 #define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
102 #define XREG_SPR_PIT XREG_SPR_DEC
103 #define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
106 //--------------------------------------------------------------------
107 // Disable the Timer - During Profiling
110 // 1. XTime_PITDisableInterrupt() ;
111 // 2. Store the remaining timer clk tick
112 // 3. Stop the PIT Timer
113 //--------------------------------------------------------------------
115 #ifdef PPC_PIT_INTERRUPT
116 #define disable_timer() \
119 val=mfspr(XREG_SPR_TCR); \
120 mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
121 timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
122 mtspr(XREG_SPR_PIT, 0); \
125 #define disable_timer() \
127 u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
128 u32 tmp_v = ProfIo_In32(addr); \
129 tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
130 ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
136 //--------------------------------------------------------------------
140 // 1. Load the remaining timer clk ticks
141 // 2. XTime_PITEnableInterrupt() ;
142 //--------------------------------------------------------------------
143 #ifdef PPC_PIT_INTERRUPT
144 #define enable_timer() \
147 val=mfspr(XREG_SPR_TCR); \
148 mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
149 mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
152 #define enable_timer() \
154 u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
155 u32 tmp_v = ProfIo_In32(addr); \
156 tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
157 ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
163 //--------------------------------------------------------------------
164 // Send Ack to Timer Interrupt
167 // 1. Load the timer clk ticks
168 // 2. Enable AutoReload and Interrupt
169 // 3. Clear PIT Timer Status bits
170 //--------------------------------------------------------------------
171 #ifdef PPC_PIT_INTERRUPT
172 #define timer_ack() \
175 mtspr(XREG_SPR_PIT, timer_clk_ticks); \
176 mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
177 val=mfspr(XREG_SPR_TCR); \
178 mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
181 #define timer_ack() \
184 csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
185 ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
189 //--------------------------------------------------------------------
191 //--------------------------------------------------------------------
196 //--------------------------------------------------------------------
197 // MicroBlaze Target - Timer related functions
198 //--------------------------------------------------------------------
199 #ifdef PROC_MICROBLAZE
201 //--------------------------------------------------------------------
202 // Disable the Timer during Call-Graph Data collection
204 //--------------------------------------------------------------------
205 #define disable_timer() \
207 u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
208 u32 tmp_v = ProfIo_In32(addr); \
209 tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
210 ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
214 //--------------------------------------------------------------------
215 // Enable the Timer after Call-Graph Data collection
217 //--------------------------------------------------------------------
218 #define enable_timer() \
220 u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
221 u32 tmp_v = ProfIo_In32(addr); \
222 tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
223 ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
227 //--------------------------------------------------------------------
228 // Send Ack to Timer Interrupt
230 //--------------------------------------------------------------------
231 #define timer_ack() \
234 csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
235 ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
238 //--------------------------------------------------------------------
239 #endif // PROC_MICROBLAZE
240 //--------------------------------------------------------------------
242 //--------------------------------------------------------------------
243 // Cortex A9 Target - Timer related functions
244 //--------------------------------------------------------------------
247 //--------------------------------------------------------------------
248 // Disable the Timer during Call-Graph Data collection
250 //--------------------------------------------------------------------
251 #define disable_timer() \
254 Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
255 Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
256 Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
260 //--------------------------------------------------------------------
261 // Enable the Timer after Call-Graph Data collection
263 //--------------------------------------------------------------------
264 #define enable_timer() \
267 Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
268 Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
269 Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
273 //--------------------------------------------------------------------
274 // Send Ack to Timer Interrupt
276 //--------------------------------------------------------------------
277 #define timer_ack() \
279 Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
280 XSCUTIMER_ISR_EVENT_FLAG_MASK);\
283 //--------------------------------------------------------------------
284 #endif // PROC_CORTEXA9
285 //--------------------------------------------------------------------