2 ******************************************************************************
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3 * @file tsl_time_stm8tl5x.c
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4 * @author MCD Application Team
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6 * @date 22-January-2013
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7 * @brief This file contains all functions to manage the timing with STM8TL5x products.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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14 * You may not use this file except in compliance with the License.
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15 * You may obtain a copy of the License at:
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17 * http://www.st.com/software_license_agreement_liberty_v2
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19 * Unless required by applicable law or agreed to in writing, software
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20 * distributed under the License is distributed on an "AS IS" BASIS,
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21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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22 * See the License for the specific language governing permissions and
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23 * limitations under the License.
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25 ******************************************************************************
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28 /* Includes ------------------------------------------------------------------*/
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29 #include "tsl_time_stm8tl5x.h"
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30 #include "tsl_time.h"
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31 #include "stm8tl5x_it.h"
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33 /* Private typedefs ----------------------------------------------------------*/
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34 /* Private defines -----------------------------------------------------------*/
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35 /* Private macros ------------------------------------------------------------*/
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36 /* Private variables ---------------------------------------------------------*/
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37 /* Private functions prototype -----------------------------------------------*/
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40 * @brief Initialization of the timing module to generate periodic interruptions
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41 * @warning The CPU frequency must be equal to 16 MHz
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43 * @retval Status Return TSL_STATUS_ERROR if the CPU freq in uncorrect.
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45 TSL_Status_enum_T TSL_tim_Init(void)
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47 CLK->PCKENR1 |= CLK_PCKENR1_TIM4; // The peripheral clock are not enable by default
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49 if (CLK->CKDIVR != 0x00) // The CPU frequency must be equal to 16 MHz
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51 return TSL_STATUS_ERROR;
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54 TIM4->SR1 = 0; // Clear overflow flag
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56 #if (TSLPRM_TICK_FREQ == 2000)
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57 TIM4->PSCR = 6; // 16 MHz / 64 = 4 us clock
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58 TIM4->ARR = 124; // 125 * 4 us = 0.5 ms
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61 #if (TSLPRM_TICK_FREQ == 1000)
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62 TIM4->PSCR = 6; // 16 MHz / 64 = 4 us clock
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63 TIM4->ARR = 249; // 250 * 4 us = 1 ms
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66 #if (TSLPRM_TICK_FREQ == 500)
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67 TIM4->PSCR = 8; // 16 MHz / 256 = 16 us clock
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68 TIM4->ARR = 124; // 125 * 16 us = 2 ms
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71 #if (TSLPRM_TICK_FREQ == 250)
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72 TIM4->PSCR = 8; // 16 MHz / 256 = 16 us clock
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73 TIM4->ARR = 249; // 250 * 16 us = 4 ms
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76 #if (TSLPRM_TICK_FREQ == 125)
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77 TIM4->PSCR = 10; // 16 MHz / 1024 = 64 us clock
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78 TIM4->ARR = 124; // 125 * 64 us = 8 ms
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81 TIM4->IER = 0x01; // Enable interrupt
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82 TIM4->CR1 = 0x01; // Start timer
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84 return TSL_STATUS_OK;
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89 * @brief Interrupt handler for TIM4 dedicated to ECS
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93 #if defined(_COSMIC_)
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94 // 'svlreg option' is added to force the saving of the virtual long register
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95 @svlreg INTERRUPT_HANDLER(TSL_Timer_ISR, 25)
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97 INTERRUPT_HANDLER(TSL_Timer_ISR, 25)
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100 TIM4->SR1 &= (uint8_t)(~TIM4_SR1_UIF);
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101 TSL_tim_ProcessIT();
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104 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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