1 /***********************************************************************//**
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2 * @file lpc17xx_emac.h
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3 * @brief Contains all macro definitions and function prototypes
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4 * support for Ethernet MAC firmware library on LPC17xx
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6 * @date 21. May. 2010
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7 * @author NXP MCU SW Application Team
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8 **************************************************************************
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9 * Software that is described herein is for illustrative purposes only
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10 * which provides customers with programming information regarding the
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11 * products. This software is supplied "AS IS" without any warranties.
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12 * NXP Semiconductors assumes no responsibility or liability for the
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13 * use of the software, conveys no license or title under any patent,
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14 * copyright, or mask work right to the product. NXP Semiconductors
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15 * reserves the right to make changes in the software without
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16 * notification. NXP Semiconductors also make no representation or
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17 * warranty that such application will be suitable for the specified
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18 * use without further testing or modification.
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19 **************************************************************************/
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21 /* Peripheral group ----------------------------------------------------------- */
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22 /** @defgroup EMAC EMAC
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23 * @ingroup LPC1700CMSIS_FwLib_Drivers
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27 #ifndef LPC18XX_EMAC_H_
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28 #define LPC18XX_EMAC_H_
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30 /* Includes ------------------------------------------------------------------- */
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31 #include "LPC18xx.h"
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40 #include "lpc_types.h"
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44 /* Interface Selection */
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45 #define MII 0 // =0 RMII - =1 MII
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47 /* End of Configuration */
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49 /* Descriptors Fields bits */
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50 #define OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
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51 #define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
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52 #define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
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53 #define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
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54 #define RX_LAST_SEGM (1<<9)
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55 #define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
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56 #define RX_FIRST_SEGM (1<<8) /* First Segment bit in TDES0 */
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57 #define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
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58 #define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
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60 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
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61 #define EMAC_ETH_MAX_FLEN ipETHERNET_FRAME_SIZE_TO_USE
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63 /* NOTE: EMAC_NUM_RX_FRAG is not used by the example FreeRTOS drivers - use
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64 configNUM_RX_ETHERNET_DMA_DESCRIPTORS. */
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65 #define EMAC_NUM_RX_FRAG 6 /**< Num.of RX Fragments */
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67 /* NOTE: EMAC_NUM_TX_FRAG is not used by the example FreeRTOS drivers - use
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68 configNUM_TX_ETHERNET_DMA_DESCRIPTORS. */
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69 #define EMAC_NUM_TX_FRAG 2 /**< Num.of TX Fragments */
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71 /* EMAC Control and Status bits */
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72 #define MAC_RX_ENABLE (1<<2) /* Receiver Enable in MAC_CONFIG reg */
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73 #define MAC_TX_ENABLE (1<<3) /* Transmitter Enable in MAC_CONFIG reg */
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74 #define MAC_PADCRC_STRIP (1<<7) /* Automatic Pad-CRC Stripping in MAC_CONFIG reg */
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75 #define MAC_DUPMODE (1<<11) /* Duplex Mode in MAC_CONFIG reg */
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76 #define MAC_100MPS (1<<14) /* Speed is 100Mbps in MAC_CONFIG reg */
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77 #define MAC_PROMISCUOUS (1U<<0) /* Promiscuous Mode bit in MAC_FRAME_FILTER reg */
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78 #define MAC_DIS_BROAD (1U<<5) /* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */
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79 #define MAC_RECEIVEALL (1U<<31) /* Receive All bit in MAC_FRAME_FILTER reg */
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80 #define DMA_SOFT_RESET 0x01 /* Software Reset bit in DMA_BUS_MODE reg */
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81 #define DMA_SS_RECEIVE (1<<1) /* Start/Stop Receive bit in DMA_OP_MODE reg */
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82 #define DMA_SS_TRANSMIT (1<<13) /* Start/Stop Transmission bit in DMA_OP_MODE reg */
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83 #define DMA_INT_TRANSMIT (1<<0) /* Transmit Interrupt Enable bit in DMA_INT_EN reg */
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84 #define DMA_INT_OVERFLOW (1<<4) /* Overflow Interrupt Enable bit in DMA_INT_EN reg */
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85 #define DMA_INT_UNDERFLW (1<<5) /* Underflow Interrupt Enable bit in DMA_INT_EN reg */
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86 #define DMA_INT_RECEIVE (1<<6) /* Receive Interrupt Enable bit in DMA_INT_EN reg */
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87 #define DMA_INT_ABN_SUM (1<<15) /* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */
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88 #define DMA_INT_NOR_SUM (1<<16) /* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */
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90 /* MII Management Command Register */
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91 #define GMII_READ (0<<1) /* GMII Read PHY */
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92 #define GMII_WRITE (1<<1) /* GMII Write PHY */
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93 #define GMII_BUSY 0x00000001 /* GMII is Busy / Start Read/Write */
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94 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
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95 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
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97 /* MII Management Address Register */
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98 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
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100 /* LAN8720 PHY Registers */
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101 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
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102 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
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103 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
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104 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
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105 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
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106 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
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107 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
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108 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
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110 /* LAN8720 PHY Speed identify */
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111 #define PHY_REG_SPCON 0x1f /* Speed indication Register */
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112 #define PHY_REG_HCDSPEED_MASK 0x1c /* Speed indication Register mask*/
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113 #define PHY_REG_HCDSPEED_10MB_HALFD 0x04 /* Speed is 10Mbps HALF-duplex */
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114 #define PHY_REG_HCDSPEED_10MB_FULLD 0x14 /* Speed is 10Mbps FULL-duplex */
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115 #define PHY_REG_HCDSPEED_100MB_HALFD 0x08 /* Speed is 100Mbps HALF-duplex */
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116 #define PHY_REG_HCDSPEED_100MB_FULLD 0x18 /* Speed is 100Mbps FULL-duplex */
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119 /* PHY Extended Registers */
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120 #define PHY_REG_STS 0x10 /* Status Register */
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121 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
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122 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
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123 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
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124 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
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125 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
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126 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
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127 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
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128 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
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129 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
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130 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
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131 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
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133 /* PHY Control and Status bits */
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134 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
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135 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
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136 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
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137 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
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138 #define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
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139 #define PHY_AUTO_NEG_DONE 0x0020 /* AutoNegotiation Complete in BMSR PHY reg */
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140 #define PHY_BMCR_RESET 0x8000 /* Reset bit at BMCR PHY reg */
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141 #define LINK_VALID_STS 0x0001 /* Link Valid Status at REG_STS PHY reg */
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142 #define FULL_DUP_STS 0x0004 /* Full Duplex Status at REG_STS PHY reg */
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143 #define SPEED_10M_STS 0x0002 /* 10Mbps Status at REG_STS PHY reg */
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145 #define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
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146 #define DP83848C_ID 0x20005C90 /* PHY Identifier (without Rev. info */
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147 #define LAN8720_ID 0x0007C0F1 /* PHY Identifier for SMSC PHY */
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150 #define ETHERNET_RST 22 /* Reset Output for EMAC at RGU */
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151 #define RMII_SELECT 0x04 /* Select RMII in EMACCFG */
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155 * @brief EMAC configuration structure definition
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158 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
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160 - EMAC_MODE_10M_FULL
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161 - EMAC_MODE_10M_HALF
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162 - EMAC_MODE_100M_FULL
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163 - EMAC_MODE_100M_HALF
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165 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
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166 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
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170 /* Descriptor and status formats ---------------------------------------------- */
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172 * @brief RX Descriptor structure type definition
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175 uint32_t Status; /**< Receive Status Descriptor */
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176 uint32_t Ctrl; /**< Receive Control Descriptor */
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177 uint32_t Packet; /**< Receive Packet Descriptor */
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178 uint32_t NextDescripter;/**< Receive Next Descriptor Address */
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182 * @brief RX Status structure type definition
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185 uint32_t Info; /**< Receive Information Status */
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186 uint32_t HashCRC; /**< Receive Hash CRC Status */
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190 * @brief TX Descriptor structure type definition
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193 uint32_t Status; /**< Transmit Status Descriptor */
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194 uint32_t Ctrl; /**< Transmit Control Descriptor */
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195 uint32_t Packet; /**< Transmit Packet Descriptor */
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196 uint32_t NextDescripter; /**< Transmit Next Descriptor Address */
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200 * @brief TX Status structure type definition
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203 uint32_t Info; /**< Transmit Information Status */
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208 * @brief TX Data Buffer structure definition
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211 uint32_t ulDataLen; /**< Data length */
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212 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
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213 } EMAC_PACKETBUF_Type;
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218 BaseType_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
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219 int32_t EMAC_UpdatePHYStatus(void);
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220 uint32_t EMAC_GetReceiveDataSize(void);
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221 void EMAC_StartTransmitNextBuffer( uint32_t ulLength );
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222 void EMAC_SetNextPacketToSend( uint8_t * pucBuffer );
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223 void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer );
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224 void EMAC_UpdateRxConsumeIndex(void);
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225 BaseType_t EMAC_CheckReceiveIndex(void);
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226 BaseType_t EMAC_CheckTransmitIndex(void);
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232 #endif /* LPC18XX_EMAC_H_ */
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238 /* --------------------------------- End Of File ------------------------------ */
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projects / freertos / blob