4 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
\r
10 * Redistribution and use in source and binary forms, with or without
\r
11 * modification, are permitted provided that the following conditions are met:
\r
13 * 1. Redistributions of source code must retain the above copyright notice,
\r
14 * this list of conditions and the following disclaimer.
\r
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
17 * this list of conditions and the following disclaimer in the documentation
\r
18 * and/or other materials provided with the distribution.
\r
20 * 3. The name of Atmel may not be used to endorse or promote products derived
\r
21 * from this software without specific prior written permission.
\r
23 * 4. This software may only be redistributed and used in connection with an
\r
24 * Atmel microcontroller product.
\r
26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
\r
27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
\r
29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
\r
30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
\r
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
\r
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
\r
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\r
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\r
36 * POSSIBILITY OF SUCH DAMAGE.
\r
42 #ifndef _SAM4E_AFEC_COMPONENT_
\r
43 #define _SAM4E_AFEC_COMPONENT_
\r
45 /* ============================================================================= */
\r
46 /** SOFTWARE API DEFINITION FOR Analog-Front-End Controller */
\r
47 /* ============================================================================= */
\r
48 /** \addtogroup SAM4E_AFEC Analog-Front-End Controller */
\r
51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
52 /** \brief Afec hardware registers */
\r
54 WoReg AFEC_CR; /**< \brief (Afec Offset: 0x00) Control Register */
\r
55 RwReg AFEC_MR; /**< \brief (Afec Offset: 0x04) Mode Register */
\r
56 RwReg AFEC_EMR; /**< \brief (Afec Offset: 0x08) Extended Mode Register */
\r
57 RwReg AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) Channel Sequence 1 Register */
\r
58 RwReg AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) Channel Sequence 2 Register */
\r
59 WoReg AFEC_CHER; /**< \brief (Afec Offset: 0x14) Channel Enable Register */
\r
60 WoReg AFEC_CHDR; /**< \brief (Afec Offset: 0x18) Channel Disable Register */
\r
61 RoReg AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) Channel Status Register */
\r
62 RoReg AFEC_LCDR; /**< \brief (Afec Offset: 0x20) Last Converted Data Register */
\r
63 WoReg AFEC_IER; /**< \brief (Afec Offset: 0x24) Interrupt Enable Register */
\r
64 WoReg AFEC_IDR; /**< \brief (Afec Offset: 0x28) Interrupt Disable Register */
\r
65 RoReg AFEC_IMR; /**< \brief (Afec Offset: 0x2C) Interrupt Mask Register */
\r
66 RoReg AFEC_ISR; /**< \brief (Afec Offset: 0x30) Interrupt Status Register */
\r
68 RoReg AFEC_OVER; /**< \brief (Afec Offset: 0x4C) Overrun Status Register */
\r
69 RwReg AFEC_CWR; /**< \brief (Afec Offset: 0x50) Compare Window Register */
\r
70 RwReg AFEC_CGR; /**< \brief (Afec Offset: 0x54) Channel Gain Register */
\r
72 RwReg AFEC_CDOR; /**< \brief (Afec Offset: 0x5C) Channel Calibration DC Offset Register */
\r
73 RwReg AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) Channel Differential Register */
\r
74 RwReg AFEC_CSELR; /**< \brief (Afec Offset: 0x64) Channel Register Selection */
\r
75 RoReg AFEC_CDR; /**< \brief (Afec Offset: 0x68) Channel Data Register */
\r
76 RwReg AFEC_COCR; /**< \brief (Afec Offset: 0x6C) Channel Offset Compensation Register */
\r
77 RwReg AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) Temperature Sensor Mode Register */
\r
78 RwReg AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) Temperature Compare Window Register */
\r
80 RwReg AFEC_ACR; /**< \brief (Afec Offset: 0x94) Analog Control Register */
\r
81 RoReg Reserved4[19];
\r
82 RwReg AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) Write Protect Mode Register */
\r
83 RoReg AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) Write Protect Status Register */
\r
85 RwReg AFEC_RPR; /**< \brief (Afec Offset: 0x100) Receive Pointer Register */
\r
86 RwReg AFEC_RCR; /**< \brief (Afec Offset: 0x104) Receive Counter Register */
\r
88 RwReg AFEC_RNPR; /**< \brief (Afec Offset: 0x110) Receive Next Pointer Register */
\r
89 RwReg AFEC_RNCR; /**< \brief (Afec Offset: 0x114) Receive Next Counter Register */
\r
91 WoReg AFEC_PTCR; /**< \brief (Afec Offset: 0x120) Transfer Control Register */
\r
92 RoReg AFEC_PTSR; /**< \brief (Afec Offset: 0x124) Transfer Status Register */
\r
94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
95 /* -------- AFEC_CR : (AFEC Offset: 0x00) Control Register -------- */
\r
96 #define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */
\r
97 #define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */
\r
98 #define AFEC_CR_AUTOCAL (0x1u << 3) /**< \brief (AFEC_CR) Automatic Calibration of AFEC */
\r
99 /* -------- AFEC_MR : (AFEC Offset: 0x04) Mode Register -------- */
\r
100 #define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */
\r
101 #define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
\r
102 #define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */
\r
103 #define AFEC_MR_TRGSEL_Pos 1
\r
104 #define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */
\r
105 #define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) ADTRG pin */
\r
106 #define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 0 */
\r
107 #define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 1 */
\r
108 #define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 2 */
\r
109 #define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM Event Line 0 */
\r
110 #define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM Event Line 1 */
\r
111 #define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */
\r
112 #define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal Mode: The AFEC Core and reference voltage circuitry are kept ON between conversions */
\r
113 #define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode: The AFEC Core and reference voltage circuitry are OFF between conversions */
\r
114 #define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up */
\r
115 #define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
\r
116 #define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and AFEC Core is OFF */
\r
117 #define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */
\r
118 #define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal Mode */
\r
119 #define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode: Never wait for any trigger. */
\r
120 #define AFEC_MR_PRESCAL_Pos 8
\r
121 #define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */
\r
122 #define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))
\r
123 #define AFEC_MR_STARTUP_Pos 16
\r
124 #define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start Up Time */
\r
125 #define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFEClock */
\r
126 #define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFEClock */
\r
127 #define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFEClock */
\r
128 #define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFEClock */
\r
129 #define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFEClock */
\r
130 #define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFEClock */
\r
131 #define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFEClock */
\r
132 #define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFEClock */
\r
133 #define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFEClock */
\r
134 #define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFEClock */
\r
135 #define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFEClock */
\r
136 #define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFEClock */
\r
137 #define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFEClock */
\r
138 #define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFEClock */
\r
139 #define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFEClock */
\r
140 #define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFEClock */
\r
141 #define AFEC_MR_SETTLING_Pos 20
\r
142 #define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) /**< \brief (AFEC_MR) Analog Settling Time */
\r
143 #define AFEC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (AFEC_MR) 3 periods of AFEClock */
\r
144 #define AFEC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (AFEC_MR) 5 periods of AFEClock */
\r
145 #define AFEC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (AFEC_MR) 9 periods of AFEClock */
\r
146 #define AFEC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (AFEC_MR) 17 periods of AFEClock */
\r
147 #define AFEC_MR_ANACH (0x1u << 23) /**< \brief (AFEC_MR) Analog Change */
\r
148 #define AFEC_MR_ANACH_NONE (0x0u << 23) /**< \brief (AFEC_MR) No analog change on channel switching: DIFF0, GAIN0 are used for all channels */
\r
149 #define AFEC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (AFEC_MR) Allows different analog settings for each channel. See AFEC_CGR Register. */
\r
150 #define AFEC_MR_TRACKTIM_Pos 24
\r
151 #define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */
\r
152 #define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))
\r
153 #define AFEC_MR_TRANSFER_Pos 28
\r
154 #define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */
\r
155 #define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))
\r
156 #define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) Use Sequence Enable */
\r
157 #define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
\r
158 #define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Mode: The sequence respects what is defined in AFEC_SEQR1 and AFEC_SEQR2 registers. */
\r
159 /* -------- AFEC_EMR : (AFEC Offset: 0x08) Extended Mode Register -------- */
\r
160 #define AFEC_EMR_CMPMODE_Pos 0
\r
161 #define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */
\r
162 #define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
\r
163 #define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
\r
164 #define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */
\r
165 #define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */
\r
166 #define AFEC_EMR_CMPSEL_Pos 3
\r
167 #define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */
\r
168 #define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))
\r
169 #define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */
\r
170 #define AFEC_EMR_CMPFILTER_Pos 12
\r
171 #define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */
\r
172 #define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))
\r
173 #define AFEC_EMR_RES_Pos 16
\r
174 #define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */
\r
175 #define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFEC sample rate is maximum (no averaging). */
\r
176 #define AFEC_EMR_RES_LOW_RES (0x1u << 16) /**< \brief (AFEC_EMR) 10-bit resolution, AFEC sample rate is maximum (no averaging). */
\r
177 #define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFEC sample rate divided by 4 (averaging). */
\r
178 #define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFEC sample rate divided by 16 (averaging). */
\r
179 #define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFEC sample rate divided by 64 (averaging). */
\r
180 #define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFEC sample rate divided by 256 (averaging). */
\r
181 #define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of AFEC_LDCR register */
\r
182 #define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */
\r
183 /* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) Channel Sequence 1 Register -------- */
\r
184 #define AFEC_SEQ1R_USCH0_Pos 0
\r
185 #define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */
\r
186 #define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))
\r
187 #define AFEC_SEQ1R_USCH1_Pos 4
\r
188 #define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */
\r
189 #define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))
\r
190 #define AFEC_SEQ1R_USCH2_Pos 8
\r
191 #define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */
\r
192 #define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))
\r
193 #define AFEC_SEQ1R_USCH3_Pos 12
\r
194 #define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */
\r
195 #define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))
\r
196 #define AFEC_SEQ1R_USCH4_Pos 16
\r
197 #define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */
\r
198 #define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))
\r
199 #define AFEC_SEQ1R_USCH5_Pos 20
\r
200 #define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */
\r
201 #define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))
\r
202 #define AFEC_SEQ1R_USCH6_Pos 24
\r
203 #define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */
\r
204 #define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))
\r
205 #define AFEC_SEQ1R_USCH7_Pos 28
\r
206 #define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */
\r
207 #define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))
\r
208 /* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) Channel Sequence 2 Register -------- */
\r
209 #define AFEC_SEQ2R_USCH8_Pos 0
\r
210 #define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */
\r
211 #define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))
\r
212 #define AFEC_SEQ2R_USCH9_Pos 4
\r
213 #define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */
\r
214 #define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))
\r
215 #define AFEC_SEQ2R_USCH10_Pos 8
\r
216 #define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */
\r
217 #define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))
\r
218 #define AFEC_SEQ2R_USCH11_Pos 12
\r
219 #define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */
\r
220 #define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))
\r
221 #define AFEC_SEQ2R_USCH12_Pos 16
\r
222 #define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */
\r
223 #define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))
\r
224 #define AFEC_SEQ2R_USCH13_Pos 20
\r
225 #define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */
\r
226 #define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))
\r
227 #define AFEC_SEQ2R_USCH14_Pos 24
\r
228 #define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */
\r
229 #define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))
\r
230 #define AFEC_SEQ2R_USCH15_Pos 28
\r
231 #define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */
\r
232 #define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))
\r
233 /* -------- AFEC_CHER : (AFEC Offset: 0x14) Channel Enable Register -------- */
\r
234 #define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */
\r
235 #define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */
\r
236 #define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */
\r
237 #define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */
\r
238 #define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */
\r
239 #define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */
\r
240 #define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */
\r
241 #define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */
\r
242 #define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */
\r
243 #define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */
\r
244 #define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */
\r
245 #define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */
\r
246 #define AFEC_CHER_CH12 (0x1u << 12) /**< \brief (AFEC_CHER) Channel 12 Enable */
\r
247 #define AFEC_CHER_CH13 (0x1u << 13) /**< \brief (AFEC_CHER) Channel 13 Enable */
\r
248 #define AFEC_CHER_CH14 (0x1u << 14) /**< \brief (AFEC_CHER) Channel 14 Enable */
\r
249 #define AFEC_CHER_CH15 (0x1u << 15) /**< \brief (AFEC_CHER) Channel 15 Enable */
\r
250 /* -------- AFEC_CHDR : (AFEC Offset: 0x18) Channel Disable Register -------- */
\r
251 #define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */
\r
252 #define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */
\r
253 #define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */
\r
254 #define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */
\r
255 #define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */
\r
256 #define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */
\r
257 #define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */
\r
258 #define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */
\r
259 #define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */
\r
260 #define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */
\r
261 #define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */
\r
262 #define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */
\r
263 #define AFEC_CHDR_CH12 (0x1u << 12) /**< \brief (AFEC_CHDR) Channel 12 Disable */
\r
264 #define AFEC_CHDR_CH13 (0x1u << 13) /**< \brief (AFEC_CHDR) Channel 13 Disable */
\r
265 #define AFEC_CHDR_CH14 (0x1u << 14) /**< \brief (AFEC_CHDR) Channel 14 Disable */
\r
266 #define AFEC_CHDR_CH15 (0x1u << 15) /**< \brief (AFEC_CHDR) Channel 15 Disable */
\r
267 /* -------- AFEC_CHSR : (AFEC Offset: 0x1C) Channel Status Register -------- */
\r
268 #define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */
\r
269 #define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */
\r
270 #define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */
\r
271 #define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */
\r
272 #define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */
\r
273 #define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */
\r
274 #define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */
\r
275 #define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */
\r
276 #define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */
\r
277 #define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */
\r
278 #define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */
\r
279 #define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */
\r
280 #define AFEC_CHSR_CH12 (0x1u << 12) /**< \brief (AFEC_CHSR) Channel 12 Status */
\r
281 #define AFEC_CHSR_CH13 (0x1u << 13) /**< \brief (AFEC_CHSR) Channel 13 Status */
\r
282 #define AFEC_CHSR_CH14 (0x1u << 14) /**< \brief (AFEC_CHSR) Channel 14 Status */
\r
283 #define AFEC_CHSR_CH15 (0x1u << 15) /**< \brief (AFEC_CHSR) Channel 15 Status */
\r
284 /* -------- AFEC_LCDR : (AFEC Offset: 0x20) Last Converted Data Register -------- */
\r
285 #define AFEC_LCDR_LDATA_Pos 0
\r
286 #define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */
\r
287 #define AFEC_LCDR_CHNB_Pos 24
\r
288 #define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */
\r
289 /* -------- AFEC_IER : (AFEC Offset: 0x24) Interrupt Enable Register -------- */
\r
290 #define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */
\r
291 #define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */
\r
292 #define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */
\r
293 #define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */
\r
294 #define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */
\r
295 #define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */
\r
296 #define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */
\r
297 #define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */
\r
298 #define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */
\r
299 #define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */
\r
300 #define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */
\r
301 #define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */
\r
302 #define AFEC_IER_EOC12 (0x1u << 12) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 12 */
\r
303 #define AFEC_IER_EOC13 (0x1u << 13) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 13 */
\r
304 #define AFEC_IER_EOC14 (0x1u << 14) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 14 */
\r
305 #define AFEC_IER_EOC15 (0x1u << 15) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 15 */
\r
306 #define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */
\r
307 #define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */
\r
308 #define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable+ */
\r
309 #define AFEC_IER_ENDRX (0x1u << 27) /**< \brief (AFEC_IER) End of Receive Buffer Interrupt Enable */
\r
310 #define AFEC_IER_RXBUFF (0x1u << 28) /**< \brief (AFEC_IER) Receive Buffer Full Interrupt Enable */
\r
311 #define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */
\r
312 #define AFEC_IER_EOCAL (0x1u << 31) /**< \brief (AFEC_IER) End of Calibration Sequence Interrupt Enable */
\r
313 /* -------- AFEC_IDR : (AFEC Offset: 0x28) Interrupt Disable Register -------- */
\r
314 #define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */
\r
315 #define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */
\r
316 #define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */
\r
317 #define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */
\r
318 #define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */
\r
319 #define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */
\r
320 #define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */
\r
321 #define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */
\r
322 #define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */
\r
323 #define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */
\r
324 #define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */
\r
325 #define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */
\r
326 #define AFEC_IDR_EOC12 (0x1u << 12) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 12 */
\r
327 #define AFEC_IDR_EOC13 (0x1u << 13) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 13 */
\r
328 #define AFEC_IDR_EOC14 (0x1u << 14) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 14 */
\r
329 #define AFEC_IDR_EOC15 (0x1u << 15) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 15 */
\r
330 #define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */
\r
331 #define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */
\r
332 #define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */
\r
333 #define AFEC_IDR_ENDRX (0x1u << 27) /**< \brief (AFEC_IDR) End of Receive Buffer Interrupt Disable */
\r
334 #define AFEC_IDR_RXBUFF (0x1u << 28) /**< \brief (AFEC_IDR) Receive Buffer Full Interrupt Disable */
\r
335 #define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */
\r
336 #define AFEC_IDR_EOCAL (0x1u << 31) /**< \brief (AFEC_IDR) End of Calibration Sequence Interrupt Disable */
\r
337 /* -------- AFEC_IMR : (AFEC Offset: 0x2C) Interrupt Mask Register -------- */
\r
338 #define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */
\r
339 #define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */
\r
340 #define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */
\r
341 #define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */
\r
342 #define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */
\r
343 #define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */
\r
344 #define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */
\r
345 #define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */
\r
346 #define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */
\r
347 #define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */
\r
348 #define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */
\r
349 #define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */
\r
350 #define AFEC_IMR_EOC12 (0x1u << 12) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 12 */
\r
351 #define AFEC_IMR_EOC13 (0x1u << 13) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 13 */
\r
352 #define AFEC_IMR_EOC14 (0x1u << 14) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 14 */
\r
353 #define AFEC_IMR_EOC15 (0x1u << 15) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 15 */
\r
354 #define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */
\r
355 #define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */
\r
356 #define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */
\r
357 #define AFEC_IMR_ENDRX (0x1u << 27) /**< \brief (AFEC_IMR) End of Receive Buffer Interrupt Mask */
\r
358 #define AFEC_IMR_RXBUFF (0x1u << 28) /**< \brief (AFEC_IMR) Receive Buffer Full Interrupt Mask */
\r
359 #define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */
\r
360 #define AFEC_IMR_EOCAL (0x1u << 31) /**< \brief (AFEC_IMR) End of Calibration Sequence Interrupt Mask */
\r
361 /* -------- AFEC_ISR : (AFEC Offset: 0x30) Interrupt Status Register -------- */
\r
362 #define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 */
\r
363 #define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 */
\r
364 #define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 */
\r
365 #define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 */
\r
366 #define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 */
\r
367 #define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 */
\r
368 #define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 */
\r
369 #define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 */
\r
370 #define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 */
\r
371 #define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 */
\r
372 #define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 */
\r
373 #define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 */
\r
374 #define AFEC_ISR_EOC12 (0x1u << 12) /**< \brief (AFEC_ISR) End of Conversion 12 */
\r
375 #define AFEC_ISR_EOC13 (0x1u << 13) /**< \brief (AFEC_ISR) End of Conversion 13 */
\r
376 #define AFEC_ISR_EOC14 (0x1u << 14) /**< \brief (AFEC_ISR) End of Conversion 14 */
\r
377 #define AFEC_ISR_EOC15 (0x1u << 15) /**< \brief (AFEC_ISR) End of Conversion 15 */
\r
378 #define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready */
\r
379 #define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error */
\r
380 #define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error */
\r
381 #define AFEC_ISR_ENDRX (0x1u << 27) /**< \brief (AFEC_ISR) End of RX Buffer */
\r
382 #define AFEC_ISR_RXBUFF (0x1u << 28) /**< \brief (AFEC_ISR) RX Buffer Full */
\r
383 #define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change */
\r
384 #define AFEC_ISR_EOCAL (0x1u << 31) /**< \brief (AFEC_ISR) End of Calibration Sequence */
\r
385 /* -------- AFEC_OVER : (AFEC Offset: 0x4C) Overrun Status Register -------- */
\r
386 #define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */
\r
387 #define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */
\r
388 #define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */
\r
389 #define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */
\r
390 #define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */
\r
391 #define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */
\r
392 #define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */
\r
393 #define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */
\r
394 #define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */
\r
395 #define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */
\r
396 #define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */
\r
397 #define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */
\r
398 #define AFEC_OVER_OVRE12 (0x1u << 12) /**< \brief (AFEC_OVER) Overrun Error 12 */
\r
399 #define AFEC_OVER_OVRE13 (0x1u << 13) /**< \brief (AFEC_OVER) Overrun Error 13 */
\r
400 #define AFEC_OVER_OVRE14 (0x1u << 14) /**< \brief (AFEC_OVER) Overrun Error 14 */
\r
401 #define AFEC_OVER_OVRE15 (0x1u << 15) /**< \brief (AFEC_OVER) Overrun Error 15 */
\r
402 /* -------- AFEC_CWR : (AFEC Offset: 0x50) Compare Window Register -------- */
\r
403 #define AFEC_CWR_LOWTHRES_Pos 0
\r
404 #define AFEC_CWR_LOWTHRES_Msk (0xfffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */
\r
405 #define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))
\r
406 #define AFEC_CWR_HIGHTHRES_Pos 16
\r
407 #define AFEC_CWR_HIGHTHRES_Msk (0xfffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */
\r
408 #define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))
\r
409 /* -------- AFEC_CGR : (AFEC Offset: 0x54) Channel Gain Register -------- */
\r
410 #define AFEC_CGR_GAIN0_Pos 0
\r
411 #define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for channel 0 */
\r
412 #define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))
\r
413 #define AFEC_CGR_GAIN1_Pos 2
\r
414 #define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for channel 1 */
\r
415 #define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))
\r
416 #define AFEC_CGR_GAIN2_Pos 4
\r
417 #define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for channel 2 */
\r
418 #define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))
\r
419 #define AFEC_CGR_GAIN3_Pos 6
\r
420 #define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for channel 3 */
\r
421 #define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))
\r
422 #define AFEC_CGR_GAIN4_Pos 8
\r
423 #define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for channel 4 */
\r
424 #define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))
\r
425 #define AFEC_CGR_GAIN5_Pos 10
\r
426 #define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for channel 5 */
\r
427 #define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))
\r
428 #define AFEC_CGR_GAIN6_Pos 12
\r
429 #define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for channel 6 */
\r
430 #define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))
\r
431 #define AFEC_CGR_GAIN7_Pos 14
\r
432 #define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for channel 7 */
\r
433 #define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))
\r
434 #define AFEC_CGR_GAIN8_Pos 16
\r
435 #define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for channel 8 */
\r
436 #define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))
\r
437 #define AFEC_CGR_GAIN9_Pos 18
\r
438 #define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for channel 9 */
\r
439 #define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))
\r
440 #define AFEC_CGR_GAIN10_Pos 20
\r
441 #define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for channel 10 */
\r
442 #define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))
\r
443 #define AFEC_CGR_GAIN11_Pos 22
\r
444 #define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for channel 11 */
\r
445 #define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))
\r
446 #define AFEC_CGR_GAIN12_Pos 24
\r
447 #define AFEC_CGR_GAIN12_Msk (0x3u << AFEC_CGR_GAIN12_Pos) /**< \brief (AFEC_CGR) Gain for channel 12 */
\r
448 #define AFEC_CGR_GAIN12(value) ((AFEC_CGR_GAIN12_Msk & ((value) << AFEC_CGR_GAIN12_Pos)))
\r
449 #define AFEC_CGR_GAIN13_Pos 26
\r
450 #define AFEC_CGR_GAIN13_Msk (0x3u << AFEC_CGR_GAIN13_Pos) /**< \brief (AFEC_CGR) Gain for channel 13 */
\r
451 #define AFEC_CGR_GAIN13(value) ((AFEC_CGR_GAIN13_Msk & ((value) << AFEC_CGR_GAIN13_Pos)))
\r
452 #define AFEC_CGR_GAIN14_Pos 28
\r
453 #define AFEC_CGR_GAIN14_Msk (0x3u << AFEC_CGR_GAIN14_Pos) /**< \brief (AFEC_CGR) Gain for channel 14 */
\r
454 #define AFEC_CGR_GAIN14(value) ((AFEC_CGR_GAIN14_Msk & ((value) << AFEC_CGR_GAIN14_Pos)))
\r
455 #define AFEC_CGR_GAIN15_Pos 30
\r
456 #define AFEC_CGR_GAIN15_Msk (0x3u << AFEC_CGR_GAIN15_Pos) /**< \brief (AFEC_CGR) Gain for channel 15 */
\r
457 #define AFEC_CGR_GAIN15(value) ((AFEC_CGR_GAIN15_Msk & ((value) << AFEC_CGR_GAIN15_Pos)))
\r
458 /* -------- AFEC_CDOR : (AFEC Offset: 0x5C) Channel Calibration DC Offset Register -------- */
\r
459 #define AFEC_CDOR_OFF0 (0x1u << 0) /**< \brief (AFEC_CDOR) Offset for channel 0, used in automatic calibration procedure */
\r
460 #define AFEC_CDOR_OFF1 (0x1u << 1) /**< \brief (AFEC_CDOR) Offset for channel 1, used in automatic calibration procedure */
\r
461 #define AFEC_CDOR_OFF2 (0x1u << 2) /**< \brief (AFEC_CDOR) Offset for channel 2, used in automatic calibration procedure */
\r
462 #define AFEC_CDOR_OFF3 (0x1u << 3) /**< \brief (AFEC_CDOR) Offset for channel 3, used in automatic calibration procedure */
\r
463 #define AFEC_CDOR_OFF4 (0x1u << 4) /**< \brief (AFEC_CDOR) Offset for channel 4, used in automatic calibration procedure */
\r
464 #define AFEC_CDOR_OFF5 (0x1u << 5) /**< \brief (AFEC_CDOR) Offset for channel 5, used in automatic calibration procedure */
\r
465 #define AFEC_CDOR_OFF6 (0x1u << 6) /**< \brief (AFEC_CDOR) Offset for channel 6, used in automatic calibration procedure */
\r
466 #define AFEC_CDOR_OFF7 (0x1u << 7) /**< \brief (AFEC_CDOR) Offset for channel 7, used in automatic calibration procedure */
\r
467 #define AFEC_CDOR_OFF8 (0x1u << 8) /**< \brief (AFEC_CDOR) Offset for channel 8, used in automatic calibration procedure */
\r
468 #define AFEC_CDOR_OFF9 (0x1u << 9) /**< \brief (AFEC_CDOR) Offset for channel 9, used in automatic calibration procedure */
\r
469 #define AFEC_CDOR_OFF10 (0x1u << 10) /**< \brief (AFEC_CDOR) Offset for channel 10, used in automatic calibration procedure */
\r
470 #define AFEC_CDOR_OFF11 (0x1u << 11) /**< \brief (AFEC_CDOR) Offset for channel 11, used in automatic calibration procedure */
\r
471 #define AFEC_CDOR_OFF12 (0x1u << 12) /**< \brief (AFEC_CDOR) Offset for channel 12, used in automatic calibration procedure */
\r
472 #define AFEC_CDOR_OFF13 (0x1u << 13) /**< \brief (AFEC_CDOR) Offset for channel 13, used in automatic calibration procedure */
\r
473 #define AFEC_CDOR_OFF14 (0x1u << 14) /**< \brief (AFEC_CDOR) Offset for channel 14, used in automatic calibration procedure */
\r
474 #define AFEC_CDOR_OFF15 (0x1u << 15) /**< \brief (AFEC_CDOR) Offset for channel 15, used in automatic calibration procedure */
\r
475 /* -------- AFEC_DIFFR : (AFEC Offset: 0x60) Channel Differential Register -------- */
\r
476 #define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */
\r
477 #define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */
\r
478 #define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */
\r
479 #define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */
\r
480 #define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */
\r
481 #define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */
\r
482 #define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */
\r
483 #define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */
\r
484 #define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */
\r
485 #define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */
\r
486 #define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */
\r
487 #define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */
\r
488 #define AFEC_DIFFR_DIFF12 (0x1u << 12) /**< \brief (AFEC_DIFFR) Differential inputs for channel 12 */
\r
489 #define AFEC_DIFFR_DIFF13 (0x1u << 13) /**< \brief (AFEC_DIFFR) Differential inputs for channel 13 */
\r
490 #define AFEC_DIFFR_DIFF14 (0x1u << 14) /**< \brief (AFEC_DIFFR) Differential inputs for channel 14 */
\r
491 #define AFEC_DIFFR_DIFF15 (0x1u << 15) /**< \brief (AFEC_DIFFR) Differential inputs for channel 15 */
\r
492 /* -------- AFEC_CSELR : (AFEC Offset: 0x64) Channel Register Selection -------- */
\r
493 #define AFEC_CSELR_CSEL_Pos 0
\r
494 #define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */
\r
495 #define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))
\r
496 /* -------- AFEC_CDR : (AFEC Offset: 0x68) Channel Data Register -------- */
\r
497 #define AFEC_CDR_DATA_Pos 0
\r
498 #define AFEC_CDR_DATA_Msk (0xfffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */
\r
499 /* -------- AFEC_COCR : (AFEC Offset: 0x6C) Channel Offset Compensation Register -------- */
\r
500 #define AFEC_COCR_AOFF_Pos 0
\r
501 #define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */
\r
502 #define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))
\r
503 /* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) Temperature Sensor Mode Register -------- */
\r
504 #define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger mode */
\r
505 #define AFEC_TEMPMR_TEMPCMPMOD_Pos 4
\r
506 #define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */
\r
507 #define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */
\r
508 #define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */
\r
509 #define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */
\r
510 #define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */
\r
511 /* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) Temperature Compare Window Register -------- */
\r
512 #define AFEC_TEMPCWR_TLOWTHRES_Pos 0
\r
513 #define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */
\r
514 #define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))
\r
515 #define AFEC_TEMPCWR_THIGHTHRES_Pos 16
\r
516 #define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */
\r
517 #define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))
\r
518 /* -------- AFEC_ACR : (AFEC Offset: 0x94) Analog Control Register -------- */
\r
519 #define AFEC_ACR_IBCTL_Pos 8
\r
520 #define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFEC Bias Current Control */
\r
521 #define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))
\r
522 /* -------- AFEC_WPMR : (AFEC Offset: 0xE4) Write Protect Mode Register -------- */
\r
523 #define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protect Enable */
\r
524 #define AFEC_WPMR_WPKEY_Pos 8
\r
525 #define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */
\r
526 #define AFEC_WPMR_WPKEY_ADC (0x414443u << 8) /**< \brief (AFEC_WPMR) Should be written at value 0x414443 ("ADC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
\r
527 /* -------- AFEC_WPSR : (AFEC Offset: 0xE8) Write Protect Status Register -------- */
\r
528 #define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */
\r
529 #define AFEC_WPSR_WPVSRC_Pos 8
\r
530 #define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */
\r
531 /* -------- AFEC_RPR : (AFEC Offset: 0x100) Receive Pointer Register -------- */
\r
532 #define AFEC_RPR_RXPTR_Pos 0
\r
533 #define AFEC_RPR_RXPTR_Msk (0xffffffffu << AFEC_RPR_RXPTR_Pos) /**< \brief (AFEC_RPR) Receive Pointer Register */
\r
534 #define AFEC_RPR_RXPTR(value) ((AFEC_RPR_RXPTR_Msk & ((value) << AFEC_RPR_RXPTR_Pos)))
\r
535 /* -------- AFEC_RCR : (AFEC Offset: 0x104) Receive Counter Register -------- */
\r
536 #define AFEC_RCR_RXCTR_Pos 0
\r
537 #define AFEC_RCR_RXCTR_Msk (0xffffu << AFEC_RCR_RXCTR_Pos) /**< \brief (AFEC_RCR) Receive Counter Register */
\r
538 #define AFEC_RCR_RXCTR(value) ((AFEC_RCR_RXCTR_Msk & ((value) << AFEC_RCR_RXCTR_Pos)))
\r
539 /* -------- AFEC_RNPR : (AFEC Offset: 0x110) Receive Next Pointer Register -------- */
\r
540 #define AFEC_RNPR_RXNPTR_Pos 0
\r
541 #define AFEC_RNPR_RXNPTR_Msk (0xffffffffu << AFEC_RNPR_RXNPTR_Pos) /**< \brief (AFEC_RNPR) Receive Next Pointer */
\r
542 #define AFEC_RNPR_RXNPTR(value) ((AFEC_RNPR_RXNPTR_Msk & ((value) << AFEC_RNPR_RXNPTR_Pos)))
\r
543 /* -------- AFEC_RNCR : (AFEC Offset: 0x114) Receive Next Counter Register -------- */
\r
544 #define AFEC_RNCR_RXNCTR_Pos 0
\r
545 #define AFEC_RNCR_RXNCTR_Msk (0xffffu << AFEC_RNCR_RXNCTR_Pos) /**< \brief (AFEC_RNCR) Receive Next Counter */
\r
546 #define AFEC_RNCR_RXNCTR(value) ((AFEC_RNCR_RXNCTR_Msk & ((value) << AFEC_RNCR_RXNCTR_Pos)))
\r
547 /* -------- AFEC_PTCR : (AFEC Offset: 0x120) Transfer Control Register -------- */
\r
548 #define AFEC_PTCR_RXTEN (0x1u << 0) /**< \brief (AFEC_PTCR) Receiver Transfer Enable */
\r
549 #define AFEC_PTCR_RXTDIS (0x1u << 1) /**< \brief (AFEC_PTCR) Receiver Transfer Disable */
\r
550 #define AFEC_PTCR_TXTEN (0x1u << 8) /**< \brief (AFEC_PTCR) Transmitter Transfer Enable */
\r
551 #define AFEC_PTCR_TXTDIS (0x1u << 9) /**< \brief (AFEC_PTCR) Transmitter Transfer Disable */
\r
552 /* -------- AFEC_PTSR : (AFEC Offset: 0x124) Transfer Status Register -------- */
\r
553 #define AFEC_PTSR_RXTEN (0x1u << 0) /**< \brief (AFEC_PTSR) Receiver Transfer Enable */
\r
554 #define AFEC_PTSR_TXTEN (0x1u << 8) /**< \brief (AFEC_PTSR) Transmitter Transfer Enable */
\r
559 #endif /* _SAM4E_AFEC_COMPONENT_ */
\r
projects / freertos / blob