1 /**************************************************************************//**
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2 * @file efm32gg_adc.h
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3 * @brief EFM32GG_ADC register and bit field definitions
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5 ******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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33 * @defgroup EFM32GG_ADC
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35 * @brief EFM32GG_ADC Register Declaration
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36 *****************************************************************************/
\r
39 __IO uint32_t CTRL; /**< Control Register */
\r
40 __IO uint32_t CMD; /**< Command Register */
\r
41 __I uint32_t STATUS; /**< Status Register */
\r
42 __IO uint32_t SINGLECTRL; /**< Single Sample Control Register */
\r
43 __IO uint32_t SCANCTRL; /**< Scan Control Register */
\r
44 __IO uint32_t IEN; /**< Interrupt Enable Register */
\r
45 __I uint32_t IF; /**< Interrupt Flag Register */
\r
46 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
\r
47 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
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48 __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
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49 __I uint32_t SCANDATA; /**< Scan Conversion Result Data */
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50 __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
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51 __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
\r
52 __IO uint32_t CAL; /**< Calibration Register */
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54 uint32_t RESERVED0[1]; /**< Reserved for future use **/
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55 __IO uint32_t BIASPROG; /**< Bias Programming Register */
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56 } ADC_TypeDef; /** @} */
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58 /**************************************************************************//**
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59 * @defgroup EFM32GG_ADC_BitFields
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61 *****************************************************************************/
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63 /* Bit fields for ADC CTRL */
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64 #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
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65 #define _ADC_CTRL_MASK 0x0F1F7F3BUL /**< Mask for ADC_CTRL */
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66 #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
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67 #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
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68 #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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69 #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
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70 #define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */
\r
71 #define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */
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72 #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
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73 #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
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74 #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
\r
75 #define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */
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76 #define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */
\r
77 #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
\r
78 #define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */
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79 #define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */
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80 #define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */
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81 #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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82 #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
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83 #define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */
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84 #define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */
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85 #define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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86 #define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */
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87 #define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */
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88 #define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */
\r
89 #define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
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90 #define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */
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91 #define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */
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92 #define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */
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93 #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
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94 #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
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95 #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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96 #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
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97 #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
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98 #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
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99 #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
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100 #define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL /**< Bit mask for ADC_TIMEBASE */
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101 #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
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102 #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
\r
103 #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
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104 #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
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105 #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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106 #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
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107 #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
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108 #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
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109 #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
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110 #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
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111 #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
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112 #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
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113 #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
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114 #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
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115 #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
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116 #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
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117 #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
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118 #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
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119 #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
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120 #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
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121 #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
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122 #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
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123 #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
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124 #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
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125 #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
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126 #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
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127 #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
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128 #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
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129 #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
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130 #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
\r
132 /* Bit fields for ADC CMD */
\r
133 #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
\r
134 #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
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135 #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */
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136 #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
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137 #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
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138 #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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139 #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
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140 #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */
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141 #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
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142 #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
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143 #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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144 #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
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145 #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
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146 #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
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147 #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
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148 #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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149 #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
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150 #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
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151 #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
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152 #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
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153 #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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154 #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
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156 /* Bit fields for ADC STATUS */
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157 #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
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158 #define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */
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159 #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */
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160 #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
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161 #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
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162 #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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163 #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
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164 #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
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165 #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
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166 #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
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167 #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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168 #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
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169 #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */
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170 #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
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171 #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
\r
172 #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
173 #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
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174 #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
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175 #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
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176 #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
\r
177 #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
178 #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
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179 #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
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180 #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
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181 #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
\r
182 #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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183 #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
184 #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */
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185 #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
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186 #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
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187 #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
188 #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
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189 #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
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190 #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
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191 #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
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192 #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
193 #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
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194 #define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */
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195 #define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */
\r
196 #define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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197 #define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */
\r
198 #define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */
\r
199 #define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */
\r
200 #define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */
\r
201 #define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */
\r
202 #define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */
\r
203 #define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */
\r
204 #define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */
\r
205 #define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
206 #define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */
\r
207 #define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */
\r
208 #define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */
\r
209 #define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */
\r
210 #define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */
\r
211 #define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */
\r
212 #define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */
\r
213 #define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */
\r
215 /* Bit fields for ADC SINGLECTRL */
\r
216 #define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */
\r
217 #define _ADC_SINGLECTRL_MASK 0xF1F70F37UL /**< Mask for ADC_SINGLECTRL */
\r
218 #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */
\r
219 #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
\r
220 #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
\r
221 #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
222 #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
223 #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */
\r
224 #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
\r
225 #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
\r
226 #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
227 #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
228 #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */
\r
229 #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
\r
230 #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
\r
231 #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
232 #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
\r
233 #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
\r
234 #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
235 #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
\r
236 #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
\r
237 #define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
\r
238 #define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
\r
239 #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
240 #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
\r
241 #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
\r
242 #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
\r
243 #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
\r
244 #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
245 #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
\r
246 #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
\r
247 #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
\r
248 #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */
\r
249 #define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
\r
250 #define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
\r
251 #define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
252 #define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
\r
253 #define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
\r
254 #define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
\r
255 #define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
\r
256 #define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
\r
257 #define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
\r
258 #define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
\r
259 #define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
\r
260 #define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
\r
261 #define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
\r
262 #define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
\r
263 #define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
\r
264 #define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
\r
265 #define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */
\r
266 #define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */
\r
267 #define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */
\r
268 #define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */
\r
269 #define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */
\r
270 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
\r
271 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
\r
272 #define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
273 #define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
\r
274 #define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
\r
275 #define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
\r
276 #define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
\r
277 #define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
\r
278 #define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
\r
279 #define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
\r
280 #define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
\r
281 #define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
\r
282 #define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
\r
283 #define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
\r
284 #define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
\r
285 #define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
\r
286 #define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
\r
287 #define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */
\r
288 #define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */
\r
289 #define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
\r
290 #define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */
\r
291 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
\r
292 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
\r
293 #define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
\r
294 #define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
\r
295 #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
296 #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
\r
297 #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
\r
298 #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
\r
299 #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */
\r
300 #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
\r
301 #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
\r
302 #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
\r
303 #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
304 #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
\r
305 #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
\r
306 #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */
\r
307 #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
\r
308 #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
\r
309 #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
\r
310 #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
\r
311 #define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
\r
312 #define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
\r
313 #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
314 #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
\r
315 #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
\r
316 #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
\r
317 #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
\r
318 #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
\r
319 #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
\r
320 #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
\r
321 #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
\r
322 #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
\r
323 #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
324 #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
\r
325 #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
\r
326 #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
\r
327 #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
\r
328 #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
\r
329 #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
\r
330 #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
\r
331 #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
\r
332 #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
\r
333 #define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */
\r
334 #define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
\r
335 #define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
\r
336 #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
337 #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
338 #define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
\r
339 #define _ADC_SINGLECTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
\r
340 #define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
341 #define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */
\r
342 #define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */
\r
343 #define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */
\r
344 #define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */
\r
345 #define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */
\r
346 #define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */
\r
347 #define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */
\r
348 #define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */
\r
349 #define _ADC_SINGLECTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRL */
\r
350 #define _ADC_SINGLECTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRL */
\r
351 #define _ADC_SINGLECTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRL */
\r
352 #define _ADC_SINGLECTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRL */
\r
353 #define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
354 #define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */
\r
355 #define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */
\r
356 #define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */
\r
357 #define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */
\r
358 #define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */
\r
359 #define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */
\r
360 #define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */
\r
361 #define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */
\r
362 #define ADC_SINGLECTRL_PRSSEL_PRSCH8 (_ADC_SINGLECTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SINGLECTRL */
\r
363 #define ADC_SINGLECTRL_PRSSEL_PRSCH9 (_ADC_SINGLECTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SINGLECTRL */
\r
364 #define ADC_SINGLECTRL_PRSSEL_PRSCH10 (_ADC_SINGLECTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SINGLECTRL */
\r
365 #define ADC_SINGLECTRL_PRSSEL_PRSCH11 (_ADC_SINGLECTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SINGLECTRL */
\r
367 /* Bit fields for ADC SCANCTRL */
\r
368 #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
\r
369 #define _ADC_SCANCTRL_MASK 0xF1F7FF37UL /**< Mask for ADC_SCANCTRL */
\r
370 #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
\r
371 #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
\r
372 #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
\r
373 #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
374 #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
375 #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
\r
376 #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
\r
377 #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
\r
378 #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
379 #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
380 #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
\r
381 #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
\r
382 #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
\r
383 #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
384 #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
\r
385 #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
\r
386 #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
387 #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
\r
388 #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
\r
389 #define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
\r
390 #define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
\r
391 #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
392 #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
\r
393 #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
\r
394 #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
\r
395 #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
\r
396 #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
397 #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */
\r
398 #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */
\r
399 #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */
\r
400 #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */
\r
401 #define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
\r
402 #define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
\r
403 #define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
404 #define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
\r
405 #define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
\r
406 #define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
\r
407 #define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
\r
408 #define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
\r
409 #define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
\r
410 #define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
\r
411 #define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
\r
412 #define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
\r
413 #define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */
\r
414 #define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
\r
415 #define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
\r
416 #define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
417 #define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
\r
418 #define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
\r
419 #define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
\r
420 #define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
\r
421 #define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
\r
422 #define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
\r
423 #define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
\r
424 #define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
\r
425 #define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
\r
426 #define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */
\r
427 #define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */
\r
428 #define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */
\r
429 #define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
\r
430 #define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
\r
431 #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
432 #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
\r
433 #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
\r
434 #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
\r
435 #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */
\r
436 #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
\r
437 #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
\r
438 #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
\r
439 #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
440 #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */
\r
441 #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */
\r
442 #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */
\r
443 #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
\r
444 #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
\r
445 #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
\r
446 #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
\r
447 #define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
\r
448 #define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
\r
449 #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
450 #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
\r
451 #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
\r
452 #define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */
\r
453 #define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */
\r
454 #define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */
\r
455 #define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */
\r
456 #define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */
\r
457 #define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */
\r
458 #define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */
\r
459 #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
460 #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
\r
461 #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
\r
462 #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
\r
463 #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
\r
464 #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
\r
465 #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
\r
466 #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
\r
467 #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
\r
468 #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
\r
469 #define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */
\r
470 #define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
\r
471 #define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
\r
472 #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
473 #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
474 #define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
\r
475 #define _ADC_SCANCTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
\r
476 #define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
477 #define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */
\r
478 #define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */
\r
479 #define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */
\r
480 #define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */
\r
481 #define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */
\r
482 #define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */
\r
483 #define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */
\r
484 #define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */
\r
485 #define _ADC_SCANCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRL */
\r
486 #define _ADC_SCANCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRL */
\r
487 #define _ADC_SCANCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRL */
\r
488 #define _ADC_SCANCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRL */
\r
489 #define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
490 #define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */
\r
491 #define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */
\r
492 #define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */
\r
493 #define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */
\r
494 #define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */
\r
495 #define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */
\r
496 #define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */
\r
497 #define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */
\r
498 #define ADC_SCANCTRL_PRSSEL_PRSCH8 (_ADC_SCANCTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SCANCTRL */
\r
499 #define ADC_SCANCTRL_PRSSEL_PRSCH9 (_ADC_SCANCTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SCANCTRL */
\r
500 #define ADC_SCANCTRL_PRSSEL_PRSCH10 (_ADC_SCANCTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SCANCTRL */
\r
501 #define ADC_SCANCTRL_PRSSEL_PRSCH11 (_ADC_SCANCTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SCANCTRL */
\r
503 /* Bit fields for ADC IEN */
\r
504 #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
\r
505 #define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */
\r
506 #define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */
\r
507 #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
\r
508 #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
\r
509 #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
510 #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
\r
511 #define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */
\r
512 #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
\r
513 #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
\r
514 #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
515 #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
\r
516 #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */
\r
517 #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
518 #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
519 #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
520 #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
\r
521 #define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */
\r
522 #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
523 #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
524 #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
525 #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
\r
527 /* Bit fields for ADC IF */
\r
528 #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
\r
529 #define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */
\r
530 #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
\r
531 #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
\r
532 #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
\r
533 #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
534 #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
\r
535 #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
\r
536 #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
\r
537 #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
\r
538 #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
539 #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
\r
540 #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */
\r
541 #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
542 #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
543 #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
544 #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
\r
545 #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */
\r
546 #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
547 #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
548 #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
549 #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
\r
551 /* Bit fields for ADC IFS */
\r
552 #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
\r
553 #define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */
\r
554 #define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */
\r
555 #define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
\r
556 #define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
\r
557 #define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
558 #define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */
\r
559 #define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */
\r
560 #define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
\r
561 #define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
\r
562 #define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
563 #define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */
\r
564 #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */
\r
565 #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
566 #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
567 #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
568 #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
\r
569 #define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */
\r
570 #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
571 #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
572 #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
573 #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
\r
575 /* Bit fields for ADC IFC */
\r
576 #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
\r
577 #define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */
\r
578 #define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */
\r
579 #define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
\r
580 #define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
\r
581 #define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
582 #define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */
\r
583 #define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */
\r
584 #define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
\r
585 #define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
\r
586 #define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
587 #define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */
\r
588 #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */
\r
589 #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
590 #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
591 #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
592 #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
\r
593 #define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */
\r
594 #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
595 #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
596 #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
597 #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
\r
599 /* Bit fields for ADC SINGLEDATA */
\r
600 #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
\r
601 #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
\r
602 #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
\r
603 #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
\r
604 #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
\r
605 #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
\r
607 /* Bit fields for ADC SCANDATA */
\r
608 #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
\r
609 #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
\r
610 #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
\r
611 #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
\r
612 #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
\r
613 #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
\r
615 /* Bit fields for ADC SINGLEDATAP */
\r
616 #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
\r
617 #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
\r
618 #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
\r
619 #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
\r
620 #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
\r
621 #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
\r
623 /* Bit fields for ADC SCANDATAP */
\r
624 #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
\r
625 #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
\r
626 #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
\r
627 #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
\r
628 #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
\r
629 #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
\r
631 /* Bit fields for ADC CAL */
\r
632 #define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */
\r
633 #define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */
\r
634 #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
\r
635 #define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */
\r
636 #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
\r
637 #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
\r
638 #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
\r
639 #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
\r
640 #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
\r
641 #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
\r
642 #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
\r
643 #define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */
\r
644 #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
\r
645 #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
\r
646 #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
\r
647 #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
\r
648 #define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
\r
649 #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
\r
651 /* Bit fields for ADC BIASPROG */
\r
652 #define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */
\r
653 #define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */
\r
654 #define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */
\r
655 #define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */
\r
656 #define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
\r
657 #define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
\r
658 #define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
\r
659 #define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */
\r
660 #define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */
\r
661 #define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */
\r
662 #define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */
\r
663 #define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */
\r
664 #define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */
\r
665 #define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
\r
666 #define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
\r
668 /** @} End of group EFM32GG_ADC */
\r
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