1 /**************************************************************************//**
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2 * @file core_armv8mml.h
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3 * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
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5 * @date 06. July 2018
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__clang__)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef __CORE_ARMV8MML_H_GENERIC
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32 #define __CORE_ARMV8MML_H_GENERIC
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41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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42 CMSIS violates the following MISRA-C:2004 rules:
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44 \li Required Rule 8.5, object/function definition in header file.<br>
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45 Function definitions in header files are used to allow 'inlining'.
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47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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48 Unions are used for effective representation of core registers.
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50 \li Advisory Rule 19.7, Function-like macro defined.<br>
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51 Function-like macros are used to allow more efficient code.
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55 /*******************************************************************************
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57 ******************************************************************************/
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59 \ingroup Cortex_ARMv8MML
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63 #include "cmsis_version.h"
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65 /* CMSIS Armv8MML definitions */
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66 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
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67 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
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68 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
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69 __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
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71 #define __CORTEX_M (81U) /*!< Cortex-M Core */
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73 /** __FPU_USED indicates whether an FPU is used or not.
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74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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76 #if defined ( __CC_ARM )
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77 #if defined __TARGET_FPU_VFP
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78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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79 #define __FPU_USED 1U
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81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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82 #define __FPU_USED 0U
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85 #define __FPU_USED 0U
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88 #if defined(__ARM_FEATURE_DSP)
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89 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
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90 #define __DSP_USED 1U
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92 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
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93 #define __DSP_USED 0U
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96 #define __DSP_USED 0U
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99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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100 #if defined __ARM_PCS_VFP
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101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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102 #define __FPU_USED 1U
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104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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105 #define __FPU_USED 0U
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108 #define __FPU_USED 0U
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111 #if defined(__ARM_FEATURE_DSP)
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112 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
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113 #define __DSP_USED 1U
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115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
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116 #define __DSP_USED 0U
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119 #define __DSP_USED 0U
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122 #elif defined ( __GNUC__ )
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123 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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125 #define __FPU_USED 1U
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127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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128 #define __FPU_USED 0U
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131 #define __FPU_USED 0U
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134 #if defined(__ARM_FEATURE_DSP)
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135 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
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136 #define __DSP_USED 1U
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138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
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139 #define __DSP_USED 0U
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142 #define __DSP_USED 0U
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145 #elif defined ( __ICCARM__ )
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146 #if defined __ARMVFP__
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147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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148 #define __FPU_USED 1U
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150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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151 #define __FPU_USED 0U
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154 #define __FPU_USED 0U
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157 #if defined(__ARM_FEATURE_DSP)
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158 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
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159 #define __DSP_USED 1U
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161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
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162 #define __DSP_USED 0U
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165 #define __DSP_USED 0U
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168 #elif defined ( __TI_ARM__ )
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169 #if defined __TI_VFP_SUPPORT__
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170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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171 #define __FPU_USED 1U
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173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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174 #define __FPU_USED 0U
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177 #define __FPU_USED 0U
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180 #elif defined ( __TASKING__ )
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181 #if defined __FPU_VFP__
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182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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183 #define __FPU_USED 1U
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185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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186 #define __FPU_USED 0U
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189 #define __FPU_USED 0U
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192 #elif defined ( __CSMC__ )
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193 #if ( __CSMC__ & 0x400U)
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194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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195 #define __FPU_USED 1U
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197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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198 #define __FPU_USED 0U
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201 #define __FPU_USED 0U
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206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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213 #endif /* __CORE_ARMV8MML_H_GENERIC */
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215 #ifndef __CMSIS_GENERIC
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217 #ifndef __CORE_ARMV8MML_H_DEPENDANT
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218 #define __CORE_ARMV8MML_H_DEPENDANT
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224 /* check device defines and use defaults */
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225 #if defined __CHECK_DEVICE_DEFINES
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226 #ifndef __ARMv8MML_REV
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227 #define __ARMv8MML_REV 0x0000U
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228 #warning "__ARMv8MML_REV not defined in device header file; using default!"
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231 #ifndef __FPU_PRESENT
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232 #define __FPU_PRESENT 0U
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233 #warning "__FPU_PRESENT not defined in device header file; using default!"
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236 #ifndef __MPU_PRESENT
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237 #define __MPU_PRESENT 0U
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238 #warning "__MPU_PRESENT not defined in device header file; using default!"
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241 #ifndef __SAUREGION_PRESENT
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242 #define __SAUREGION_PRESENT 0U
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243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
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246 #ifndef __DSP_PRESENT
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247 #define __DSP_PRESENT 0U
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248 #warning "__DSP_PRESENT not defined in device header file; using default!"
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251 #ifndef __NVIC_PRIO_BITS
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252 #define __NVIC_PRIO_BITS 3U
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253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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256 #ifndef __Vendor_SysTickConfig
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257 #define __Vendor_SysTickConfig 0U
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258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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262 /* IO definitions (access restrictions to peripheral registers) */
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264 \defgroup CMSIS_glob_defs CMSIS Global Defines
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266 <strong>IO Type Qualifiers</strong> are used
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267 \li to specify the access to peripheral variables.
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268 \li for automatic generation of peripheral register debug information.
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271 #define __I volatile /*!< Defines 'read only' permissions */
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273 #define __I volatile const /*!< Defines 'read only' permissions */
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275 #define __O volatile /*!< Defines 'write only' permissions */
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276 #define __IO volatile /*!< Defines 'read / write' permissions */
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278 /* following defines should be used for structure members */
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279 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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280 #define __OM volatile /*! Defines 'write only' structure member permissions */
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281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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283 /*@} end of group ARMv8MML */
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287 /*******************************************************************************
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288 * Register Abstraction
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289 Core Register contain:
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291 - Core NVIC Register
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292 - Core SCB Register
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293 - Core SysTick Register
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294 - Core Debug Register
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295 - Core MPU Register
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296 - Core SAU Register
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297 - Core FPU Register
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298 ******************************************************************************/
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300 \defgroup CMSIS_core_register Defines and Type Definitions
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301 \brief Type definitions and defines for Cortex-M processor based devices.
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305 \ingroup CMSIS_core_register
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306 \defgroup CMSIS_CORE Status and Control Registers
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307 \brief Core Register type definitions.
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312 \brief Union type to access the Application Program Status Register (APSR).
\r
318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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326 } b; /*!< Structure used for bit access */
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327 uint32_t w; /*!< Type used for word access */
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330 /* APSR Register Definitions */
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331 #define APSR_N_Pos 31U /*!< APSR: N Position */
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332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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337 #define APSR_C_Pos 29U /*!< APSR: C Position */
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338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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340 #define APSR_V_Pos 28U /*!< APSR: V Position */
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341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
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344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
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347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
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351 \brief Union type to access the Interrupt Program Status Register (IPSR).
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357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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359 } b; /*!< Structure used for bit access */
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360 uint32_t w; /*!< Type used for word access */
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363 /* IPSR Register Definitions */
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364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
\r
379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
\r
381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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386 } b; /*!< Structure used for bit access */
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387 uint32_t w; /*!< Type used for word access */
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390 /* xPSR Register Definitions */
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391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
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404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
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406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
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407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
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409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
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413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
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415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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420 \brief Union type to access the Control Registers (CONTROL).
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426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
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428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
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429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
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430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
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431 } b; /*!< Structure used for bit access */
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432 uint32_t w; /*!< Type used for word access */
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435 /* CONTROL Register Definitions */
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436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
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437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
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439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
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440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
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442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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448 /*@} end of group CMSIS_CORE */
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452 \ingroup CMSIS_core_register
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453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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454 \brief Type definitions for the NVIC Registers
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459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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464 uint32_t RESERVED0[16U];
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465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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466 uint32_t RSERVED1[16U];
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467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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468 uint32_t RESERVED2[16U];
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469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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470 uint32_t RESERVED3[16U];
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471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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472 uint32_t RESERVED4[16U];
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473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
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474 uint32_t RESERVED5[16U];
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475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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476 uint32_t RESERVED6[580U];
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477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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480 /* Software Triggered Interrupt Register Definitions */
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481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
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482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
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484 /*@} end of group CMSIS_NVIC */
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488 \ingroup CMSIS_core_register
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489 \defgroup CMSIS_SCB System Control Block (SCB)
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490 \brief Type definitions for the System Control Block Registers
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495 \brief Structure type to access the System Control Block (SCB).
\r
499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
\r
500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
\r
501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
\r
502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
\r
503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
\r
506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
\r
508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
\r
509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
\r
510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
\r
511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
\r
512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
\r
513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
\r
514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
\r
515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
\r
516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
\r
517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
\r
518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
\r
519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
\r
520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
\r
521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
\r
522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
\r
523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
\r
524 uint32_t RESERVED3[92U];
\r
525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
\r
526 uint32_t RESERVED4[15U];
\r
527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
\r
528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
\r
529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
\r
530 uint32_t RESERVED5[1U];
\r
531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
\r
532 uint32_t RESERVED6[1U];
\r
533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
\r
534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
\r
535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
\r
536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
\r
537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
\r
538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
\r
539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
\r
540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
\r
541 uint32_t RESERVED7[6U];
\r
542 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
\r
543 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
\r
544 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
\r
545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
\r
546 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
\r
547 uint32_t RESERVED8[1U];
\r
548 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
\r
551 /* SCB CPUID Register Definitions */
\r
552 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
\r
553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
\r
555 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
\r
556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
\r
558 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
\r
559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
\r
561 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
\r
562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
\r
564 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
\r
565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
\r
567 /* SCB Interrupt Control State Register Definitions */
\r
568 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
\r
569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
\r
571 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
\r
572 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
\r
574 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
\r
575 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
\r
577 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
\r
578 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
\r
580 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
\r
581 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
\r
583 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
\r
584 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
\r
586 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
\r
587 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
589 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
\r
590 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
\r
592 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
\r
593 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
595 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
\r
596 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
598 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
\r
599 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
601 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
\r
602 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
\r
604 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
\r
605 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
\r
607 /* SCB Vector Table Offset Register Definitions */
\r
608 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
\r
609 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
611 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
612 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
\r
613 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
615 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
616 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
618 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
\r
619 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
621 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
\r
622 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
\r
624 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
\r
625 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
\r
627 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
\r
628 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
\r
630 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
\r
631 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
\r
633 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
\r
634 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
636 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
637 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
639 /* SCB System Control Register Definitions */
\r
640 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
\r
641 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
643 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
\r
644 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
\r
646 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
\r
647 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
649 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
\r
650 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
652 /* SCB Configuration Control Register Definitions */
\r
653 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
\r
654 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
\r
656 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
\r
657 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
\r
659 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
\r
660 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
\r
662 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
\r
663 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
\r
665 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
\r
666 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
668 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
\r
669 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
671 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
\r
672 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
674 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
\r
675 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
677 /* SCB System Handler Control and State Register Definitions */
\r
678 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
\r
679 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
\r
681 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
\r
682 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
\r
684 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
\r
685 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
\r
687 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
\r
688 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
\r
690 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
\r
691 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
\r
693 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
\r
694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
\r
696 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
\r
697 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
699 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
\r
700 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
\r
702 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
\r
703 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
\r
705 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
\r
706 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
\r
708 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
\r
709 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
711 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
\r
712 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
714 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
\r
715 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
\r
717 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
\r
718 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
720 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
\r
721 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
\r
723 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
\r
724 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
\r
726 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
\r
727 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
\r
729 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
\r
730 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
\r
732 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
\r
733 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
\r
735 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
\r
736 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
\r
738 /* SCB Configurable Fault Status Register Definitions */
\r
739 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
\r
740 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
\r
742 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
\r
743 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
\r
745 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
\r
746 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
\r
748 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
\r
749 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
\r
750 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
\r
752 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
\r
753 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
\r
755 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
\r
756 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
\r
758 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
\r
759 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
\r
761 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
\r
762 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
\r
764 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
\r
765 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
\r
767 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
\r
768 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
\r
769 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
\r
771 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
\r
772 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
\r
774 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
\r
775 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
\r
777 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
\r
778 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
\r
780 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
\r
781 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
\r
783 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
\r
784 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
\r
786 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
\r
787 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
\r
789 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
\r
790 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
\r
791 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
\r
793 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
\r
794 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
\r
796 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
\r
797 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
\r
799 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
\r
800 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
\r
802 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
\r
803 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
\r
805 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
\r
806 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
\r
808 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
\r
809 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
\r
811 /* SCB Hard Fault Status Register Definitions */
\r
812 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
\r
813 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
\r
815 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
\r
816 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
\r
818 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
\r
819 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
\r
821 /* SCB Debug Fault Status Register Definitions */
\r
822 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
\r
823 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
\r
825 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
\r
826 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
\r
828 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
\r
829 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
\r
831 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
\r
832 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
\r
834 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
\r
835 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
\r
837 /* SCB Non-Secure Access Control Register Definitions */
\r
838 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
\r
839 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
\r
841 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
\r
842 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
\r
844 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
\r
845 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
\r
847 /* SCB Cache Level ID Register Definitions */
\r
848 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
\r
849 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
\r
851 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
\r
852 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
\r
854 /* SCB Cache Type Register Definitions */
\r
855 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
\r
856 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
\r
858 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
\r
859 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
\r
861 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
\r
862 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
\r
864 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
\r
865 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
\r
867 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
\r
868 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
\r
870 /* SCB Cache Size ID Register Definitions */
\r
871 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
\r
872 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
\r
874 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
\r
875 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
\r
877 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
\r
878 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
\r
880 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
\r
881 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
\r
883 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
\r
884 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
\r
886 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
\r
887 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
\r
889 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
\r
890 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
\r
892 /* SCB Cache Size Selection Register Definitions */
\r
893 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
\r
894 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
\r
896 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
\r
897 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
\r
899 /* SCB Software Triggered Interrupt Register Definitions */
\r
900 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
\r
901 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
\r
903 /* SCB D-Cache Invalidate by Set-way Register Definitions */
\r
904 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
\r
905 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
\r
907 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
\r
908 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
\r
910 /* SCB D-Cache Clean by Set-way Register Definitions */
\r
911 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
\r
912 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
\r
914 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
\r
915 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
\r
917 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
\r
918 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
\r
919 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
\r
921 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
\r
922 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
\r
924 /* Instruction Tightly-Coupled Memory Control Register Definitions */
\r
925 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
\r
926 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
\r
928 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
\r
929 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
\r
931 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
\r
932 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
\r
934 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
\r
935 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
\r
937 /* Data Tightly-Coupled Memory Control Register Definitions */
\r
938 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
\r
939 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
\r
941 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
\r
942 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
\r
944 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
\r
945 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
\r
947 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
\r
948 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
\r
950 /* AHBP Control Register Definitions */
\r
951 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
\r
952 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
\r
954 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
\r
955 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
\r
957 /* L1 Cache Control Register Definitions */
\r
958 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
\r
959 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
\r
961 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
\r
962 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
\r
964 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
\r
965 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
\r
967 /* AHBS Control Register Definitions */
\r
968 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
\r
969 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
\r
971 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
\r
972 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
\r
974 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
\r
975 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
\r
977 /* Auxiliary Bus Fault Status Register Definitions */
\r
978 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
\r
979 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
\r
981 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
\r
982 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
\r
984 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
\r
985 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
\r
987 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
\r
988 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
\r
990 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
\r
991 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
\r
993 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
\r
994 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
\r
996 /*@} end of group CMSIS_SCB */
\r
1000 \ingroup CMSIS_core_register
\r
1001 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\r
1002 \brief Type definitions for the System Control and ID Register not in the SCB
\r
1007 \brief Structure type to access the System Control and ID Register not in the SCB.
\r
1011 uint32_t RESERVED0[1U];
\r
1012 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
\r
1013 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
\r
1014 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
\r
1017 /* Interrupt Controller Type Register Definitions */
\r
1018 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
\r
1019 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
\r
1021 /*@} end of group CMSIS_SCnotSCB */
\r
1025 \ingroup CMSIS_core_register
\r
1026 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
1027 \brief Type definitions for the System Timer Registers.
\r
1032 \brief Structure type to access the System Timer (SysTick).
\r
1036 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
1037 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
1038 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
1039 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
1042 /* SysTick Control / Status Register Definitions */
\r
1043 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
\r
1044 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
1046 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
\r
1047 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
1049 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
\r
1050 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
1052 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
\r
1053 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
1055 /* SysTick Reload Register Definitions */
\r
1056 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
\r
1057 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
1059 /* SysTick Current Register Definitions */
\r
1060 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
\r
1061 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
1063 /* SysTick Calibration Register Definitions */
\r
1064 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
\r
1065 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
1067 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
\r
1068 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
1070 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
\r
1071 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
1073 /*@} end of group CMSIS_SysTick */
\r
1077 \ingroup CMSIS_core_register
\r
1078 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\r
1079 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
\r
1084 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
\r
1090 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
\r
1091 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
\r
1092 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
\r
1093 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
\r
1094 uint32_t RESERVED0[864U];
\r
1095 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
\r
1096 uint32_t RESERVED1[15U];
\r
1097 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
\r
1098 uint32_t RESERVED2[15U];
\r
1099 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
\r
1100 uint32_t RESERVED3[29U];
\r
1101 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
\r
1102 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
\r
1103 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
\r
1104 uint32_t RESERVED4[43U];
\r
1105 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
\r
1106 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
\r
1107 uint32_t RESERVED5[1U];
\r
1108 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
\r
1109 uint32_t RESERVED6[4U];
\r
1110 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
\r
1111 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
\r
1112 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
\r
1113 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
\r
1114 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
\r
1115 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
\r
1116 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
\r
1117 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
\r
1118 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
\r
1119 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
\r
1120 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
\r
1121 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
\r
1124 /* ITM Stimulus Port Register Definitions */
\r
1125 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
\r
1126 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
\r
1128 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
\r
1129 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
\r
1131 /* ITM Trace Privilege Register Definitions */
\r
1132 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
\r
1133 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
\r
1135 /* ITM Trace Control Register Definitions */
\r
1136 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
\r
1137 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
\r
1139 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
\r
1140 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
\r
1142 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
\r
1143 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
\r
1145 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
\r
1146 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
\r
1148 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
\r
1149 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
\r
1151 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
\r
1152 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
\r
1154 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
\r
1155 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
\r
1157 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
\r
1158 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
\r
1160 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
\r
1161 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
\r
1163 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
\r
1164 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
\r
1166 /* ITM Integration Write Register Definitions */
\r
1167 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
\r
1168 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
\r
1170 /* ITM Integration Read Register Definitions */
\r
1171 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
\r
1172 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
\r
1174 /* ITM Integration Mode Control Register Definitions */
\r
1175 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
\r
1176 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
\r
1178 /* ITM Lock Status Register Definitions */
\r
1179 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
\r
1180 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
\r
1182 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
\r
1183 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
\r
1185 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
\r
1186 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
\r
1188 /*@}*/ /* end of group CMSIS_ITM */
\r
1192 \ingroup CMSIS_core_register
\r
1193 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
1194 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
1199 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
1203 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
1204 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
\r
1205 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
\r
1206 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
\r
1207 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
\r
1208 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
\r
1209 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
\r
1210 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
1211 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
1212 uint32_t RESERVED1[1U];
\r
1213 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
1214 uint32_t RESERVED2[1U];
\r
1215 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
1216 uint32_t RESERVED3[1U];
\r
1217 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
1218 uint32_t RESERVED4[1U];
\r
1219 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
1220 uint32_t RESERVED5[1U];
\r
1221 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
1222 uint32_t RESERVED6[1U];
\r
1223 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
1224 uint32_t RESERVED7[1U];
\r
1225 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
1226 uint32_t RESERVED8[1U];
\r
1227 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
\r
1228 uint32_t RESERVED9[1U];
\r
1229 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
\r
1230 uint32_t RESERVED10[1U];
\r
1231 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
\r
1232 uint32_t RESERVED11[1U];
\r
1233 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
\r
1234 uint32_t RESERVED12[1U];
\r
1235 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
\r
1236 uint32_t RESERVED13[1U];
\r
1237 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
\r
1238 uint32_t RESERVED14[1U];
\r
1239 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
\r
1240 uint32_t RESERVED15[1U];
\r
1241 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
\r
1242 uint32_t RESERVED16[1U];
\r
1243 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
\r
1244 uint32_t RESERVED17[1U];
\r
1245 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
\r
1246 uint32_t RESERVED18[1U];
\r
1247 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
\r
1248 uint32_t RESERVED19[1U];
\r
1249 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
\r
1250 uint32_t RESERVED20[1U];
\r
1251 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
\r
1252 uint32_t RESERVED21[1U];
\r
1253 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
\r
1254 uint32_t RESERVED22[1U];
\r
1255 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
\r
1256 uint32_t RESERVED23[1U];
\r
1257 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
\r
1258 uint32_t RESERVED24[1U];
\r
1259 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
\r
1260 uint32_t RESERVED25[1U];
\r
1261 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
\r
1262 uint32_t RESERVED26[1U];
\r
1263 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
\r
1264 uint32_t RESERVED27[1U];
\r
1265 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
\r
1266 uint32_t RESERVED28[1U];
\r
1267 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
\r
1268 uint32_t RESERVED29[1U];
\r
1269 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
\r
1270 uint32_t RESERVED30[1U];
\r
1271 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
\r
1272 uint32_t RESERVED31[1U];
\r
1273 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
\r
1274 uint32_t RESERVED32[934U];
\r
1275 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
\r
1276 uint32_t RESERVED33[1U];
\r
1277 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
\r
1280 /* DWT Control Register Definitions */
\r
1281 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
\r
1282 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
1284 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
\r
1285 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
1287 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
\r
1288 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
1290 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
\r
1291 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
1293 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
\r
1294 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
1296 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
\r
1297 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
\r
1299 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
\r
1300 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
\r
1302 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
\r
1303 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
\r
1305 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
\r
1306 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
\r
1308 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
\r
1309 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
\r
1311 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
\r
1312 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
\r
1314 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
\r
1315 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
\r
1317 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
\r
1318 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
\r
1320 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
\r
1321 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
\r
1323 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
\r
1324 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
\r
1326 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
\r
1327 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
\r
1329 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
\r
1330 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
\r
1332 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
\r
1333 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
\r
1335 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
\r
1336 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
\r
1338 /* DWT CPI Count Register Definitions */
\r
1339 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
\r
1340 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
\r
1342 /* DWT Exception Overhead Count Register Definitions */
\r
1343 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
\r
1344 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
\r
1346 /* DWT Sleep Count Register Definitions */
\r
1347 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
\r
1348 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
\r
1350 /* DWT LSU Count Register Definitions */
\r
1351 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
\r
1352 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
\r
1354 /* DWT Folded-instruction Count Register Definitions */
\r
1355 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
\r
1356 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
\r
1358 /* DWT Comparator Function Register Definitions */
\r
1359 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
\r
1360 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
\r
1362 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
\r
1363 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
1365 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
\r
1366 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
1368 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
\r
1369 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
\r
1371 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
\r
1372 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
\r
1374 /*@}*/ /* end of group CMSIS_DWT */
\r
1378 \ingroup CMSIS_core_register
\r
1379 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
1380 \brief Type definitions for the Trace Port Interface (TPI)
\r
1385 \brief Structure type to access the Trace Port Interface Register (TPI).
\r
1389 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
\r
1390 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
\r
1391 uint32_t RESERVED0[2U];
\r
1392 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
1393 uint32_t RESERVED1[55U];
\r
1394 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
1395 uint32_t RESERVED2[131U];
\r
1396 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
1397 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
1398 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
\r
1399 uint32_t RESERVED3[809U];
\r
1400 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
\r
1401 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
\r
1402 uint32_t RESERVED4[4U];
\r
1403 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
\r
1404 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
\r
1407 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
1408 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
\r
1409 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
\r
1411 /* TPI Selected Pin Protocol Register Definitions */
\r
1412 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
\r
1413 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
1415 /* TPI Formatter and Flush Status Register Definitions */
\r
1416 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
\r
1417 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
1419 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
\r
1420 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
1422 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
\r
1423 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
1425 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
\r
1426 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
1428 /* TPI Formatter and Flush Control Register Definitions */
\r
1429 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
\r
1430 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
1432 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
\r
1433 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
\r
1435 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
\r
1436 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
1438 /* TPI Periodic Synchronization Control Register Definitions */
\r
1439 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
\r
1440 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
\r
1442 /* TPI Software Lock Status Register Definitions */
\r
1443 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
\r
1444 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
\r
1446 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
\r
1447 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
\r
1449 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
\r
1450 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
\r
1452 /* TPI DEVID Register Definitions */
\r
1453 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
\r
1454 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
1456 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
\r
1457 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
1459 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
\r
1460 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
1462 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
\r
1463 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
\r
1465 /* TPI DEVTYPE Register Definitions */
\r
1466 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
\r
1467 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
1469 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
\r
1470 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
1472 /*@}*/ /* end of group CMSIS_TPI */
\r
1475 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1477 \ingroup CMSIS_core_register
\r
1478 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
1479 \brief Type definitions for the Memory Protection Unit (MPU)
\r
1484 \brief Structure type to access the Memory Protection Unit (MPU).
\r
1488 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
1489 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
1490 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
\r
1491 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
1492 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
\r
1493 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
\r
1494 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
\r
1495 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
\r
1496 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
\r
1497 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
\r
1498 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
\r
1499 uint32_t RESERVED0[1];
\r
1501 __IOM uint32_t MAIR[2];
\r
1503 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
\r
1504 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
\r
1509 #define MPU_TYPE_RALIASES 4U
\r
1511 /* MPU Type Register Definitions */
\r
1512 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
\r
1513 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
1515 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
\r
1516 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
1518 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
\r
1519 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
1521 /* MPU Control Register Definitions */
\r
1522 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
\r
1523 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
1525 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
\r
1526 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
1528 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
\r
1529 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
1531 /* MPU Region Number Register Definitions */
\r
1532 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
\r
1533 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
1535 /* MPU Region Base Address Register Definitions */
\r
1536 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
\r
1537 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
\r
1539 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
\r
1540 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
\r
1542 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
\r
1543 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
\r
1545 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
\r
1546 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
\r
1548 /* MPU Region Limit Address Register Definitions */
\r
1549 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
\r
1550 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
\r
1552 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
\r
1553 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
\r
1555 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
\r
1556 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
\r
1558 /* MPU Memory Attribute Indirection Register 0 Definitions */
\r
1559 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
\r
1560 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
\r
1562 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
\r
1563 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
\r
1565 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
\r
1566 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
\r
1568 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
\r
1569 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
\r
1571 /* MPU Memory Attribute Indirection Register 1 Definitions */
\r
1572 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
\r
1573 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
\r
1575 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
\r
1576 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
\r
1578 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
\r
1579 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
\r
1581 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
\r
1582 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
\r
1584 /*@} end of group CMSIS_MPU */
\r
1588 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1590 \ingroup CMSIS_core_register
\r
1591 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
\r
1592 \brief Type definitions for the Security Attribution Unit (SAU)
\r
1597 \brief Structure type to access the Security Attribution Unit (SAU).
\r
1601 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
\r
1602 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
\r
1603 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
\r
1604 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
\r
1605 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
\r
1606 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
\r
1608 uint32_t RESERVED0[3];
\r
1610 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
\r
1611 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
\r
1614 /* SAU Control Register Definitions */
\r
1615 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
\r
1616 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
\r
1618 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
\r
1619 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
\r
1621 /* SAU Type Register Definitions */
\r
1622 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
\r
1623 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
\r
1625 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
\r
1626 /* SAU Region Number Register Definitions */
\r
1627 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
\r
1628 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
\r
1630 /* SAU Region Base Address Register Definitions */
\r
1631 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
\r
1632 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
\r
1634 /* SAU Region Limit Address Register Definitions */
\r
1635 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
\r
1636 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
\r
1638 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
\r
1639 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
\r
1641 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
\r
1642 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
\r
1644 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
\r
1646 /* Secure Fault Status Register Definitions */
\r
1647 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
\r
1648 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
\r
1650 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
\r
1651 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
\r
1653 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
\r
1654 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
\r
1656 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
\r
1657 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
\r
1659 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
\r
1660 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
\r
1662 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
\r
1663 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
\r
1665 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
\r
1666 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
\r
1668 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
\r
1669 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
\r
1671 /*@} end of group CMSIS_SAU */
\r
1672 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1676 \ingroup CMSIS_core_register
\r
1677 \defgroup CMSIS_FPU Floating Point Unit (FPU)
\r
1678 \brief Type definitions for the Floating Point Unit (FPU)
\r
1683 \brief Structure type to access the Floating Point Unit (FPU).
\r
1687 uint32_t RESERVED0[1U];
\r
1688 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
\r
1689 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
\r
1690 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
\r
1691 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
\r
1692 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
\r
1695 /* Floating-Point Context Control Register Definitions */
\r
1696 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
\r
1697 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
\r
1699 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
\r
1700 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
\r
1702 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
\r
1703 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
\r
1705 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
\r
1706 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
\r
1708 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
\r
1709 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
\r
1711 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
\r
1712 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
\r
1714 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
\r
1715 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
\r
1717 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
\r
1718 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
\r
1720 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
\r
1721 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
\r
1723 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
\r
1724 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
\r
1726 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
\r
1727 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
\r
1729 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
\r
1730 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
\r
1732 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
\r
1733 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
\r
1735 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
\r
1736 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
\r
1738 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
\r
1739 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
\r
1741 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
\r
1742 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
\r
1744 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
\r
1745 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
\r
1747 /* Floating-Point Context Address Register Definitions */
\r
1748 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
\r
1749 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
\r
1751 /* Floating-Point Default Status Control Register Definitions */
\r
1752 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
\r
1753 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
\r
1755 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
\r
1756 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
\r
1758 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
\r
1759 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
\r
1761 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
\r
1762 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
\r
1764 /* Media and FP Feature Register 0 Definitions */
\r
1765 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
\r
1766 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
\r
1768 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
\r
1769 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
\r
1771 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
\r
1772 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
\r
1774 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
\r
1775 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
\r
1777 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
\r
1778 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
\r
1780 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
\r
1781 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
\r
1783 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
\r
1784 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
\r
1786 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
\r
1787 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
\r
1789 /* Media and FP Feature Register 1 Definitions */
\r
1790 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
\r
1791 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
\r
1793 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
\r
1794 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
\r
1796 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
\r
1797 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
\r
1799 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
\r
1800 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
\r
1802 /*@} end of group CMSIS_FPU */
\r
1806 \ingroup CMSIS_core_register
\r
1807 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1808 \brief Type definitions for the Core Debug Registers
\r
1813 \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1817 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1818 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1819 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1820 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1821 uint32_t RESERVED4[1U];
\r
1822 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
\r
1823 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
\r
1826 /* Debug Halting Control and Status Register Definitions */
\r
1827 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1828 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1830 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
\r
1831 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
\r
1833 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1834 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1836 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1837 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1839 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1840 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1842 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1843 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1845 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
\r
1846 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1848 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1849 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1851 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
\r
1852 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
\r
1854 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1855 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1857 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
\r
1858 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1860 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
\r
1861 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1863 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1864 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1866 /* Debug Core Register Selector Register Definitions */
\r
1867 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
\r
1868 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1870 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
\r
1871 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1873 /* Debug Exception and Monitor Control Register Definitions */
\r
1874 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
\r
1875 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
\r
1877 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
\r
1878 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
\r
1880 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
\r
1881 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
\r
1883 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
\r
1884 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
\r
1886 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
\r
1887 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
\r
1889 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1890 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1892 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
\r
1893 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
\r
1895 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
\r
1896 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
\r
1898 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
\r
1899 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
\r
1901 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
\r
1902 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
\r
1904 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
\r
1905 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
\r
1907 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
\r
1908 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
\r
1910 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1911 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1913 /* Debug Authentication Control Register Definitions */
\r
1914 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
\r
1915 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
\r
1917 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
\r
1918 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
\r
1920 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
\r
1921 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
\r
1923 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
\r
1924 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
\r
1926 /* Debug Security Control and Status Register Definitions */
\r
1927 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
\r
1928 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
\r
1930 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
\r
1931 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
\r
1933 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
\r
1934 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
\r
1936 /*@} end of group CMSIS_CoreDebug */
\r
1940 \ingroup CMSIS_core_register
\r
1941 \defgroup CMSIS_core_bitfield Core register bit field macros
\r
1942 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
\r
1947 \brief Mask and shift a bit field value for use in a register bit range.
\r
1948 \param[in] field Name of the register bit field.
\r
1949 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\r
1950 \return Masked and shifted value.
\r
1952 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
\r
1955 \brief Mask and shift a register value to extract a bit filed value.
\r
1956 \param[in] field Name of the register bit field.
\r
1957 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\r
1958 \return Masked and shifted bit field value.
\r
1960 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
\r
1962 /*@} end of group CMSIS_core_bitfield */
\r
1966 \ingroup CMSIS_core_register
\r
1967 \defgroup CMSIS_core_base Core Definitions
\r
1968 \brief Definitions for base addresses, unions, and structures.
\r
1972 /* Memory mapping of Core Hardware */
\r
1973 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1974 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
\r
1975 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1976 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1977 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1978 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1979 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1980 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1982 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
\r
1983 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1984 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1985 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1986 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
\r
1987 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1988 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1989 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
\r
1991 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1992 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1993 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1996 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1997 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
\r
1998 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
\r
2001 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
\r
2002 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
\r
2004 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
2005 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
\r
2006 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
\r
2007 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
\r
2008 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
\r
2009 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
\r
2011 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
\r
2012 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
\r
2013 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
\r
2014 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
\r
2015 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
\r
2017 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
2018 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
\r
2019 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
\r
2022 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
\r
2023 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
\r
2025 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
2030 /*******************************************************************************
\r
2031 * Hardware Abstraction Layer
\r
2032 Core Function Interface contains:
\r
2033 - Core NVIC Functions
\r
2034 - Core SysTick Functions
\r
2035 - Core Debug Functions
\r
2036 - Core Register Access Functions
\r
2037 ******************************************************************************/
\r
2039 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
2044 /* ########################## NVIC functions #################################### */
\r
2046 \ingroup CMSIS_Core_FunctionInterface
\r
2047 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
2048 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
2052 #ifdef CMSIS_NVIC_VIRTUAL
\r
2053 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
2054 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
\r
2056 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
2058 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
\r
2059 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
\r
2060 #define NVIC_EnableIRQ __NVIC_EnableIRQ
\r
2061 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
\r
2062 #define NVIC_DisableIRQ __NVIC_DisableIRQ
\r
2063 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
\r
2064 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
\r
2065 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
\r
2066 #define NVIC_GetActive __NVIC_GetActive
\r
2067 #define NVIC_SetPriority __NVIC_SetPriority
\r
2068 #define NVIC_GetPriority __NVIC_GetPriority
\r
2069 #define NVIC_SystemReset __NVIC_SystemReset
\r
2070 #endif /* CMSIS_NVIC_VIRTUAL */
\r
2072 #ifdef CMSIS_VECTAB_VIRTUAL
\r
2073 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
2074 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
\r
2076 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
2078 #define NVIC_SetVector __NVIC_SetVector
\r
2079 #define NVIC_GetVector __NVIC_GetVector
\r
2080 #endif /* (CMSIS_VECTAB_VIRTUAL) */
\r
2082 #define NVIC_USER_IRQ_OFFSET 16
\r
2085 /* Special LR values for Secure/Non-Secure call handling and exception handling */
\r
2087 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
\r
2088 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
\r
2090 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
\r
2091 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
\r
2092 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
\r
2093 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
\r
2094 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
\r
2095 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
\r
2096 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
\r
2097 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
\r
2099 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
\r
2100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
\r
2101 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
\r
2103 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
\r
2108 \brief Set Priority Grouping
\r
2109 \details Sets the priority grouping field using the required unlock sequence.
\r
2110 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
\r
2111 Only values from 0..7 are used.
\r
2112 In case of a conflict between priority grouping and available
\r
2113 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
2114 \param [in] PriorityGroup Priority grouping field.
\r
2116 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\r
2118 uint32_t reg_value;
\r
2119 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
2121 reg_value = SCB->AIRCR; /* read old register configuration */
\r
2122 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
\r
2123 reg_value = (reg_value |
\r
2124 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
2125 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
\r
2126 SCB->AIRCR = reg_value;
\r
2131 \brief Get Priority Grouping
\r
2132 \details Reads the priority grouping field from the NVIC Interrupt Controller.
\r
2133 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
\r
2135 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
\r
2137 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
\r
2142 \brief Enable Interrupt
\r
2143 \details Enables a device specific interrupt in the NVIC interrupt controller.
\r
2144 \param [in] IRQn Device specific interrupt number.
\r
2145 \note IRQn must not be negative.
\r
2147 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\r
2149 if ((int32_t)(IRQn) >= 0)
\r
2151 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2157 \brief Get Interrupt Enable status
\r
2158 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\r
2159 \param [in] IRQn Device specific interrupt number.
\r
2160 \return 0 Interrupt is not enabled.
\r
2161 \return 1 Interrupt is enabled.
\r
2162 \note IRQn must not be negative.
\r
2164 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
\r
2166 if ((int32_t)(IRQn) >= 0)
\r
2168 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2178 \brief Disable Interrupt
\r
2179 \details Disables a device specific interrupt in the NVIC interrupt controller.
\r
2180 \param [in] IRQn Device specific interrupt number.
\r
2181 \note IRQn must not be negative.
\r
2183 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\r
2185 if ((int32_t)(IRQn) >= 0)
\r
2187 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2195 \brief Get Pending Interrupt
\r
2196 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\r
2197 \param [in] IRQn Device specific interrupt number.
\r
2198 \return 0 Interrupt status is not pending.
\r
2199 \return 1 Interrupt status is pending.
\r
2200 \note IRQn must not be negative.
\r
2202 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
2204 if ((int32_t)(IRQn) >= 0)
\r
2206 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2216 \brief Set Pending Interrupt
\r
2217 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\r
2218 \param [in] IRQn Device specific interrupt number.
\r
2219 \note IRQn must not be negative.
\r
2221 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
2223 if ((int32_t)(IRQn) >= 0)
\r
2225 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2231 \brief Clear Pending Interrupt
\r
2232 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\r
2233 \param [in] IRQn Device specific interrupt number.
\r
2234 \note IRQn must not be negative.
\r
2236 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
2238 if ((int32_t)(IRQn) >= 0)
\r
2240 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2246 \brief Get Active Interrupt
\r
2247 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\r
2248 \param [in] IRQn Device specific interrupt number.
\r
2249 \return 0 Interrupt status is not active.
\r
2250 \return 1 Interrupt status is active.
\r
2251 \note IRQn must not be negative.
\r
2253 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\r
2255 if ((int32_t)(IRQn) >= 0)
\r
2257 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2266 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
2268 \brief Get Interrupt Target State
\r
2269 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
2270 \param [in] IRQn Device specific interrupt number.
\r
2271 \return 0 if interrupt is assigned to Secure
\r
2272 \return 1 if interrupt is assigned to Non Secure
\r
2273 \note IRQn must not be negative.
\r
2275 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
\r
2277 if ((int32_t)(IRQn) >= 0)
\r
2279 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2289 \brief Set Interrupt Target State
\r
2290 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
2291 \param [in] IRQn Device specific interrupt number.
\r
2292 \return 0 if interrupt is assigned to Secure
\r
2293 1 if interrupt is assigned to Non Secure
\r
2294 \note IRQn must not be negative.
\r
2296 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
\r
2298 if ((int32_t)(IRQn) >= 0)
\r
2300 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
\r
2301 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2311 \brief Clear Interrupt Target State
\r
2312 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
2313 \param [in] IRQn Device specific interrupt number.
\r
2314 \return 0 if interrupt is assigned to Secure
\r
2315 1 if interrupt is assigned to Non Secure
\r
2316 \note IRQn must not be negative.
\r
2318 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
\r
2320 if ((int32_t)(IRQn) >= 0)
\r
2322 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
\r
2323 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2330 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
2334 \brief Set Interrupt Priority
\r
2335 \details Sets the priority of a device specific interrupt or a processor exception.
\r
2336 The interrupt number can be positive to specify a device specific interrupt,
\r
2337 or negative to specify a processor exception.
\r
2338 \param [in] IRQn Interrupt number.
\r
2339 \param [in] priority Priority to set.
\r
2340 \note The priority cannot be set for every processor exception.
\r
2342 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
2344 if ((int32_t)(IRQn) >= 0)
\r
2346 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
2350 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
2356 \brief Get Interrupt Priority
\r
2357 \details Reads the priority of a device specific interrupt or a processor exception.
\r
2358 The interrupt number can be positive to specify a device specific interrupt,
\r
2359 or negative to specify a processor exception.
\r
2360 \param [in] IRQn Interrupt number.
\r
2361 \return Interrupt Priority.
\r
2362 Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
2364 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\r
2367 if ((int32_t)(IRQn) >= 0)
\r
2369 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
\r
2373 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
\r
2379 \brief Encode Priority
\r
2380 \details Encodes the priority for an interrupt with the given priority group,
\r
2381 preemptive priority value, and subpriority value.
\r
2382 In case of a conflict between priority grouping and available
\r
2383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
2384 \param [in] PriorityGroup Used priority group.
\r
2385 \param [in] PreemptPriority Preemptive priority value (starting from 0).
\r
2386 \param [in] SubPriority Subpriority value (starting from 0).
\r
2387 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
\r
2389 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
2391 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
2392 uint32_t PreemptPriorityBits;
\r
2393 uint32_t SubPriorityBits;
\r
2395 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
2396 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
2399 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
\r
2400 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
\r
2406 \brief Decode Priority
\r
2407 \details Decodes an interrupt priority value with a given priority group to
\r
2408 preemptive priority value and subpriority value.
\r
2409 In case of a conflict between priority grouping and available
\r
2410 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
2411 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\r
2412 \param [in] PriorityGroup Used priority group.
\r
2413 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\r
2414 \param [out] pSubPriority Subpriority value (starting from 0).
\r
2416 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
\r
2418 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
2419 uint32_t PreemptPriorityBits;
\r
2420 uint32_t SubPriorityBits;
\r
2422 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
2423 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
2425 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
\r
2426 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
\r
2431 \brief Set Interrupt Vector
\r
2432 \details Sets an interrupt vector in SRAM based interrupt vector table.
\r
2433 The interrupt number can be positive to specify a device specific interrupt,
\r
2434 or negative to specify a processor exception.
\r
2435 VTOR must been relocated to SRAM before.
\r
2436 \param [in] IRQn Interrupt number
\r
2437 \param [in] vector Address of interrupt handler function
\r
2439 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\r
2441 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
2442 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
\r
2447 \brief Get Interrupt Vector
\r
2448 \details Reads an interrupt vector from interrupt vector table.
\r
2449 The interrupt number can be positive to specify a device specific interrupt,
\r
2450 or negative to specify a processor exception.
\r
2451 \param [in] IRQn Interrupt number.
\r
2452 \return Address of interrupt handler function
\r
2454 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
\r
2456 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
2457 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
\r
2462 \brief System Reset
\r
2463 \details Initiates a system reset request to reset the MCU.
\r
2465 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
\r
2467 __DSB(); /* Ensure all outstanding memory accesses included
\r
2468 buffered write are completed before reset */
\r
2469 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
2470 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
\r
2471 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
\r
2472 __DSB(); /* Ensure completion of memory access */
\r
2474 for(;;) /* wait until reset */
\r
2480 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
2482 \brief Set Priority Grouping (non-secure)
\r
2483 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
\r
2484 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
\r
2485 Only values from 0..7 are used.
\r
2486 In case of a conflict between priority grouping and available
\r
2487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
2488 \param [in] PriorityGroup Priority grouping field.
\r
2490 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
\r
2492 uint32_t reg_value;
\r
2493 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
2495 reg_value = SCB_NS->AIRCR; /* read old register configuration */
\r
2496 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
\r
2497 reg_value = (reg_value |
\r
2498 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
2499 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
\r
2500 SCB_NS->AIRCR = reg_value;
\r
2505 \brief Get Priority Grouping (non-secure)
\r
2506 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
\r
2507 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
\r
2509 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
\r
2511 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
\r
2516 \brief Enable Interrupt (non-secure)
\r
2517 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\r
2518 \param [in] IRQn Device specific interrupt number.
\r
2519 \note IRQn must not be negative.
\r
2521 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
\r
2523 if ((int32_t)(IRQn) >= 0)
\r
2525 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2531 \brief Get Interrupt Enable status (non-secure)
\r
2532 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\r
2533 \param [in] IRQn Device specific interrupt number.
\r
2534 \return 0 Interrupt is not enabled.
\r
2535 \return 1 Interrupt is enabled.
\r
2536 \note IRQn must not be negative.
\r
2538 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
\r
2540 if ((int32_t)(IRQn) >= 0)
\r
2542 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2552 \brief Disable Interrupt (non-secure)
\r
2553 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\r
2554 \param [in] IRQn Device specific interrupt number.
\r
2555 \note IRQn must not be negative.
\r
2557 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
\r
2559 if ((int32_t)(IRQn) >= 0)
\r
2561 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2567 \brief Get Pending Interrupt (non-secure)
\r
2568 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\r
2569 \param [in] IRQn Device specific interrupt number.
\r
2570 \return 0 Interrupt status is not pending.
\r
2571 \return 1 Interrupt status is pending.
\r
2572 \note IRQn must not be negative.
\r
2574 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
\r
2576 if ((int32_t)(IRQn) >= 0)
\r
2578 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2588 \brief Set Pending Interrupt (non-secure)
\r
2589 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\r
2590 \param [in] IRQn Device specific interrupt number.
\r
2591 \note IRQn must not be negative.
\r
2593 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
\r
2595 if ((int32_t)(IRQn) >= 0)
\r
2597 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2603 \brief Clear Pending Interrupt (non-secure)
\r
2604 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\r
2605 \param [in] IRQn Device specific interrupt number.
\r
2606 \note IRQn must not be negative.
\r
2608 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
\r
2610 if ((int32_t)(IRQn) >= 0)
\r
2612 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
2618 \brief Get Active Interrupt (non-secure)
\r
2619 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\r
2620 \param [in] IRQn Device specific interrupt number.
\r
2621 \return 0 Interrupt status is not active.
\r
2622 \return 1 Interrupt status is active.
\r
2623 \note IRQn must not be negative.
\r
2625 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
\r
2627 if ((int32_t)(IRQn) >= 0)
\r
2629 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
2639 \brief Set Interrupt Priority (non-secure)
\r
2640 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
\r
2641 The interrupt number can be positive to specify a device specific interrupt,
\r
2642 or negative to specify a processor exception.
\r
2643 \param [in] IRQn Interrupt number.
\r
2644 \param [in] priority Priority to set.
\r
2645 \note The priority cannot be set for every non-secure processor exception.
\r
2647 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
\r
2649 if ((int32_t)(IRQn) >= 0)
\r
2651 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
2655 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
2661 \brief Get Interrupt Priority (non-secure)
\r
2662 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
\r
2663 The interrupt number can be positive to specify a device specific interrupt,
\r
2664 or negative to specify a processor exception.
\r
2665 \param [in] IRQn Interrupt number.
\r
2666 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
2668 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
\r
2671 if ((int32_t)(IRQn) >= 0)
\r
2673 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
\r
2677 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
\r
2680 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
\r
2682 /*@} end of CMSIS_Core_NVICFunctions */
\r
2684 /* ########################## MPU functions #################################### */
\r
2686 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
2688 #include "mpu_armv8.h"
\r
2692 /* ########################## FPU functions #################################### */
\r
2694 \ingroup CMSIS_Core_FunctionInterface
\r
2695 \defgroup CMSIS_Core_FpuFunctions FPU Functions
\r
2696 \brief Function that provides FPU type.
\r
2701 \brief get FPU type
\r
2702 \details returns the FPU type
\r
2705 - \b 1: Single precision FPU
\r
2706 - \b 2: Double + Single precision FPU
\r
2708 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
\r
2712 mvfr0 = FPU->MVFR0;
\r
2713 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
\r
2715 return 2U; /* Double + Single precision FPU */
\r
2717 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
\r
2719 return 1U; /* Single precision FPU */
\r
2723 return 0U; /* No FPU */
\r
2728 /*@} end of CMSIS_Core_FpuFunctions */
\r
2732 /* ########################## SAU functions #################################### */
\r
2734 \ingroup CMSIS_Core_FunctionInterface
\r
2735 \defgroup CMSIS_Core_SAUFunctions SAU Functions
\r
2736 \brief Functions that configure the SAU.
\r
2740 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
2744 \details Enables the Security Attribution Unit (SAU).
\r
2746 __STATIC_INLINE void TZ_SAU_Enable(void)
\r
2748 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
\r
2754 \brief Disable SAU
\r
2755 \details Disables the Security Attribution Unit (SAU).
\r
2757 __STATIC_INLINE void TZ_SAU_Disable(void)
\r
2759 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
\r
2762 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
2764 /*@} end of CMSIS_Core_SAUFunctions */
\r
2769 /* ################################## SysTick function ############################################ */
\r
2771 \ingroup CMSIS_Core_FunctionInterface
\r
2772 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\r
2773 \brief Functions that configure the System.
\r
2777 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
\r
2780 \brief System Tick Configuration
\r
2781 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
\r
2782 Counter is in free running mode to generate periodic interrupts.
\r
2783 \param [in] ticks Number of ticks between two interrupts.
\r
2784 \return 0 Function succeeded.
\r
2785 \return 1 Function failed.
\r
2786 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
2787 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
2788 must contain a vendor-specific implementation of this function.
\r
2790 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
2792 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
\r
2794 return (1UL); /* Reload value impossible */
\r
2797 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
2798 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
\r
2799 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
\r
2800 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
2801 SysTick_CTRL_TICKINT_Msk |
\r
2802 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
2803 return (0UL); /* Function successful */
\r
2806 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
2808 \brief System Tick Configuration (non-secure)
\r
2809 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
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2810 Counter is in free running mode to generate periodic interrupts.
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2811 \param [in] ticks Number of ticks between two interrupts.
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2812 \return 0 Function succeeded.
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2813 \return 1 Function failed.
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2814 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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2815 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
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2816 must contain a vendor-specific implementation of this function.
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2819 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
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2821 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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2823 return (1UL); /* Reload value impossible */
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2826 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
2827 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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2828 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
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2829 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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2830 SysTick_CTRL_TICKINT_Msk |
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2831 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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2832 return (0UL); /* Function successful */
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2834 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
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2838 /*@} end of CMSIS_Core_SysTickFunctions */
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2842 /* ##################################### Debug In/Output function ########################################### */
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2844 \ingroup CMSIS_Core_FunctionInterface
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2845 \defgroup CMSIS_core_DebugFunctions ITM Functions
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2846 \brief Functions that access the ITM debug interface.
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2850 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
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2851 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
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2855 \brief ITM Send Character
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2856 \details Transmits a character via the ITM channel 0, and
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2857 \li Just returns when no debugger is connected that has booked the output.
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2858 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
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2859 \param [in] ch Character to transmit.
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2860 \returns Character to transmit.
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2862 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
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2864 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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2865 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
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2867 while (ITM->PORT[0U].u32 == 0UL)
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2871 ITM->PORT[0U].u8 = (uint8_t)ch;
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2878 \brief ITM Receive Character
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2879 \details Inputs a character via the external variable \ref ITM_RxBuffer.
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2880 \return Received character.
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2881 \return -1 No character pending.
\r
2883 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
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2885 int32_t ch = -1; /* no character available */
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2887 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
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2889 ch = ITM_RxBuffer;
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2890 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
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2898 \brief ITM Check Character
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2899 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
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2900 \return 0 No character available.
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2901 \return 1 Character available.
\r
2903 __STATIC_INLINE int32_t ITM_CheckChar (void)
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2906 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
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2908 return (0); /* no character available */
\r
2912 return (1); /* character available */
\r
2916 /*@} end of CMSIS_core_DebugFunctions */
\r
2921 #ifdef __cplusplus
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2925 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
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2927 #endif /* __CMSIS_GENERIC */
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projects / freertos / blob