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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32
  33 /*****************************************************************************/
  34 /**
  35 *
  36 * @file xcsudma.c
  37 * @addtogroup csudma_v1_0
  38 * @{
  39 *
  40 * This file contains the implementation of the interface functions for CSU_DMA
  41 * driver. Refer to the header file xcsudma.h for more detailed information.
  42 *
  43 * <pre>
  44 * MODIFICATION HISTORY:
  45 *
  46 * Ver   Who     Date     Changes
  47 * ----- ------  -------- ---------------------------------------------------
  48 * 1.0   vnsld   22/10/14 First release
  49 * </pre>
  50 *
  51 ******************************************************************************/
  52
  53 /***************************** Include Files *********************************/
  54
  55 #include "xcsudma.h"
  56
  57 /************************** Function Prototypes ******************************/
  58
  59
  60 /************************** Function Definitions *****************************/
  61
  62 /*****************************************************************************/
  63 /**
  64 *
  65 * This function initializes an CSU_DMA core. This function must be called
  66 * prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting
  67 * up the instance data and ensuring the hardware is in a quiescent state.
  68 *
  69 * @param        InstancePtr is a pointer to the XCsuDma instance.
  70 * @param        CfgPtr is a reference to a structure containing information
  71 *               about a specific XCsuDma instance.
  72 * @param        EffectiveAddr is the device base address in the virtual memory
  73 *               address space. The caller is responsible for keeping the
  74 *               address mapping from EffectiveAddr to the device physical
  75 *               base address unchanged once this function is invoked.
  76 *               Unexpected errors may occur if the address mapping changes
  77 *               after this function is called. If address translation is not
  78 *               used, pass in the physical address instead.
  79 *
  80 * @return
  81 *               - XST_SUCCESS if initialization was successful.
  82 *
  83 * @note         None.
  84 *
  85 ******************************************************************************/
  86 s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
  87                         u32 EffectiveAddr)
  88 {
  89
  90         /* Verify arguments. */
  91         Xil_AssertNonvoid(InstancePtr != NULL);
  92         Xil_AssertNonvoid(CfgPtr != NULL);
  93         Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
  94
  95         /* Setup the instance */
  96         (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
  97                                                 sizeof(XCsuDma_Config));
  98         InstancePtr->Config.BaseAddress = EffectiveAddr;
  99
 100         XCsuDma_Reset();
 101
 102         InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
 103
 104         return (XST_SUCCESS);
 105
 106 }
 107
 108 /*****************************************************************************/
 109 /**
 110 *
 111 * This function sets the starting address and amount(size) of the data to be
 112 * transfered from/to the memory through the AXI interface.
 113 *
 114 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 115 * @param        Channel represents the type of channel either it is Source or
 116 *               Destination.
 117 *               Source channel      - XCSUDMA_SRC_CHANNEL
 118 *               Destination Channel - XCSUDMA_DST_CHANNEL
 119 * @param        Addr is a 64 bit variable which holds the starting address of
 120 *               data which needs to write into the memory(DST) (or read from
 121 *               the memory(SRC)).
 122 * @param        Size is a 32 bit variable which represents the number of 4 byte
 123 *               words needs to be transfered from starting address.
 124 * @param        EnDataLast is to trigger an end of message. It will enable or
 125 *               disable data_inp_last signal to stream interface when current
 126 *               command is completed. It is applicable only to source channel
 127 *               and neglected for destination channel.
 128 *               -       1 - Asserts data_inp_last signal.
 129 *               -       0 - data_inp_last will not be asserted.
 130 *
 131 * @return       None.
 132 *
 133 * @note         Data_inp_last signal is asserted simultaneously with the
 134 *               data_inp_valid signal associated with the final 32-bit word
 135 *               transfer.
 136 *
 137 ******************************************************************************/
 138 void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 139                                         UINTPTR Addr, u32 Size, u8 EnDataLast)
 140 {
 141         /* Verify arguments */
 142         Xil_AssertVoid(InstancePtr != NULL);
 143         Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00);
 144         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 145                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 146         Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
 147         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 148
 149         /* Flushing cache memory */
 150         if (Channel == (XCSUDMA_SRC_CHANNEL)) {
 151                 Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
 152         }
 153         /* Invalidating cache memory */
 154         else {
 155                 Xil_DCacheInvalidateRange(Addr, Size <<
 156                                         (u32)(XCSUDMA_SIZE_SHIFT));
 157         }
 158
 159         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 160                 ((u32)(XCSUDMA_ADDR_OFFSET) +
 161                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 162                                 ((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK)));
 163
 164         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 165                 ((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
 166                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 167                 (((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) &
 168                                         (u32)(XCSUDMA_MSB_ADDR_MASK)));
 169
 170         if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
 171                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 172                         ((u32)(XCSUDMA_SIZE_OFFSET) +
 173                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 174                         ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
 175                                         (u32)(XCSUDMA_LAST_WORD_MASK)));
 176         }
 177         else {
 178                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 179                         ((u32)(XCSUDMA_SIZE_OFFSET) +
 180                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 181                                 (Size << (u32)(XCSUDMA_SIZE_SHIFT)));
 182         }
 183 }
 184
 185 /*****************************************************************************/
 186 /**
 187 *
 188 * This function returns the current address location of the memory, from where
 189 * it has to read the data(SRC) or the location where it has to write the data
 190 * (DST) based on the channel selection.
 191 *
 192 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 193 * @param        Channel represents the type of channel either it is Source or
 194 *               Destination.
 195 *               Source channel      - XCSUDMA_SRC_CHANNEL
 196 *               Destination Channel - XCSUDMA_DST_CHANNEL
 197 *
 198 * @return       Address is a 64 bit variable which holds the current address.
 199 *               - From this location data has to be read(SRC)
 200 *               - At this location data has to be written(DST)
 201 *
 202 * @note         None.
 203 *
 204 ******************************************************************************/
 205 u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 206 {
 207         u64 FullAddr;
 208
 209         /* Verify arguments */
 210         Xil_AssertNonvoid(InstancePtr != NULL);
 211         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 212                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 213
 214         FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 215                                 ((u32)(XCSUDMA_ADDR_OFFSET) +
 216                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 217
 218         FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 219                         ((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
 220                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) <<
 221                                 (u64)(XCSUDMA_MSB_ADDR_SHIFT));
 222
 223         return FullAddr;
 224 }
 225
 226 /*****************************************************************************/
 227 /**
 228 *
 229 * This function returns the size of the data yet to be transfered from memory
 230 * to CSU_DMA or CSU_DMA to memory based on the channel selection.
 231 *
 232 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 233 * @param        Channel represents the type of channel either it is Source or
 234 *               Destination.
 235 *               Source channel      - XCSUDMA_SRC_CHANNEL
 236 *               Destination Channel - XCSUDMA_DST_CHANNEL
 237 *
 238 * @return       Size is amount of data yet to be transfered.
 239 *
 240 * @note         None.
 241 *
 242 ******************************************************************************/
 243 u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 244 {
 245         u32 Size;
 246
 247         /* Verify arguments. */
 248         Xil_AssertNonvoid(InstancePtr != NULL);
 249         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 250                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 251
 252         Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 253                 ((u32)(XCSUDMA_SIZE_OFFSET) +
 254                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >>
 255                                         (u32)(XCSUDMA_SIZE_SHIFT);
 256
 257         return Size;
 258 }
 259
 260 /*****************************************************************************/
 261 /**
 262 *
 263 * This function pause the Channel data tranfer to/from memory or to/from stream
 264 * based on pause type.
 265 *
 266 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 267 * @param        Channel represents the type of channel either it is Source or
 268 *               Destination.
 269 *               Source channel      - XCSUDMA_SRC_CHANNEL
 270 *               Destination Channel - XCSUDMA_DST_CHANNEL
 271 * @param        Type is type of the pause to be enabled.
 272 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 273 *                       - SRC Stops issuing of new read commands to memory.
 274 *                       - DST Stops issuing of new write commands to memory.
 275 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 276 *                       - SRC Stops transfer of data from FIFO to Stream.
 277 *                       - DST Stops transfer of data from stream to FIFO.
 278 *
 279 * @return       None.
 280 *
 281 * @note         None.
 282 *
 283 ******************************************************************************/
 284 void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 285                                                 XCsuDma_PauseType Type)
 286 {
 287         /* Verify arguments. */
 288         Xil_AssertVoid(InstancePtr != NULL);
 289         Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 290                                 (Type == (XCSUDMA_PAUSE_STREAM)));
 291         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 292                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 293         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 294
 295         /* Pause Memory Read/Write/Stream operations */
 296         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 297                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 298                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 299                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 300                         (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 301                                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 302                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) |
 303                                         (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)));
 304         }
 305         if (Type == (XCSUDMA_PAUSE_STREAM)) {
 306                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 307                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 308                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 309                         (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 310                                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 311                                 (Channel * (u32)XCSUDMA_OFFSET_DIFF))) |
 312                                 (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)));
 313         }
 314 }
 315
 316 /*****************************************************************************/
 317 /**
 318 *
 319 * This functions checks whether Channel's memory or stream is paused or not
 320 * based on the given pause type.
 321 *
 322 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 323 * @param        Channel represents the type of channel either it is Source or
 324 *               Destination.
 325 *               Source channel      - XCSUDMA_SRC_CHANNEL
 326 *               Destination Channel - XCSUDMA_DST_CHANNEL
 327 * @param        Type is type of the pause which needs to be checked.
 328 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 329 *                       - SRC Stops issuing of new read commands to memory.
 330 *                       - DST Stops issuing of new write commands to memory.
 331 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 332 *                       - SRC Stops transfer of data from FIFO to Stream.
 333 *                       - DST Stops transfer of data from stream to FIFO.
 334 *
 335 * @return       Returns the pause status.
 336 *               - TRUE if it is in paused state.
 337 *               - FALSE if it is not in pause state.
 338 *
 339 * @note         None.
 340 *
 341 ******************************************************************************/
 342 s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 343                 XCsuDma_PauseType Type)
 344 {
 345
 346         u32 Data;
 347         s32 PauseState;
 348
 349         /* Verify arguments. */
 350         Xil_AssertNonvoid(InstancePtr != NULL);
 351         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 352                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 353         Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 354                                         (Type == (XCSUDMA_PAUSE_STREAM)));
 355
 356         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 357                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 358                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 359
 360         /* To know Pause condition of Memory Read/Write/Stream operations */
 361         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 362                 if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) ==
 363                                                                 (u32)0x00) {
 364                         PauseState = (s32)(FALSE);
 365                 }
 366                 else {
 367                         PauseState = (s32)(TRUE);
 368                 }
 369         }
 370         else {
 371                 if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) ==
 372                                                                 (u32)0x00) {
 373                                 PauseState = (s32)(FALSE);
 374                 }
 375                 else {
 376                         PauseState = (s32)(TRUE);
 377                 }
 378         }
 379
 380         return (s32)PauseState;
 381
 382 }
 383
 384 /*****************************************************************************/
 385 /**
 386 *
 387 * This function resumes the channel if it is in paused state and continues
 388 * where it has left or no effect if it is not in paused state, based on the
 389 * type of pause.
 390 *
 391 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 392 * @param        Channel represents the type of channel either it is Source or
 393 *               Destination.
 394 *               Source channel      - XCSUDMA_SRC_CHANNEL
 395 *               Destination Channel - XCSUDMA_DST_CHANNEL
 396 * @param        Type is type of the pause to be Resume if it is in pause
 397 *               state.
 398 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 399 *                       - SRC Stops issuing of new read commands to memory.
 400 *                       - DST Stops issuing of new write commands to memory.
 401 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 402 *                       - SRC Stops transfer of data from FIFO to Stream.
 403 *                       - DST Stops transfer of data from stream to FIFO.
 404 *
 405 * @return       None.
 406 *
 407 * @note         None.
 408 *
 409 ******************************************************************************/
 410 void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 411                 XCsuDma_PauseType Type)
 412 {
 413         u32 Data;
 414         /* Verify arguments. */
 415         Xil_AssertVoid(InstancePtr != NULL);
 416         Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 417                         (Type == (XCSUDMA_PAUSE_STREAM)));
 418         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 419                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 420         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 421
 422         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 423                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 424                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 425
 426         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 427                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 428                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 429                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 430                 (Data &
 431                                 (~(XCSUDMA_CTRL_PAUSE_MEM_MASK))));
 432         }
 433         if (Type == (XCSUDMA_PAUSE_STREAM)) {
 434                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 435                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 436                 (((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))),
 437                         ( Data &
 438                         (~(XCSUDMA_CTRL_PAUSE_STRM_MASK))));
 439         }
 440 }
 441
 442 /*****************************************************************************/
 443 /**
 444 *
 445 * This function returns the sum of all the data read from AXI memory. It is
 446 * valid only one we use CSU_DMA source channel.
 447 *
 448 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 449 *
 450 * @return       Returns the sum of all the data read from memory.
 451 *
 452 * @note         Before start of the transfer need to clear this register to get
 453 *               correct sum otherwise it adds to previous value which results
 454 *               to wrong output.
 455 *               Valid only for source channel
 456 *
 457 ******************************************************************************/
 458 u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr)
 459 {
 460         u32 ChkSum;
 461
 462         /* Verify arguments. */
 463         Xil_AssertNonvoid(InstancePtr != NULL);
 464         Xil_AssertNonvoid(InstancePtr->IsReady ==
 465                                 (u32)(XIL_COMPONENT_IS_READY));
 466
 467         ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 468                                                 (u32)(XCSUDMA_CRC_OFFSET));
 469
 470         return ChkSum;
 471
 472 }
 473 /*****************************************************************************/
 474 /**
 475 *
 476 * This function clears the check sum of the data read from AXI memory. It is
 477 * valid only for CSU_DMA source channel.
 478 *
 479 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 480 *
 481 * @return       Returns the sum of all the data read from memory.
 482 *
 483 * @note         Before start of the transfer need to clear this register to get
 484 *               correct sum otherwise it adds to previous value which results
 485 *               to wrong output.
 486 *
 487 ******************************************************************************/
 488 void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr)
 489 {
 490
 491         /* Verify arguments. */
 492         Xil_AssertVoid(InstancePtr != NULL);
 493
 494         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 495                 (u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK));
 496 }
 497
 498 /*****************************************************************************/
 499 /**
 500 * This function cofigures all the values of CSU_DMA's Channels with the values
 501 * of updated XCsuDma_Configure structure.
 502 *
 503 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 504 * @param        Channel represents the type of channel either it is Source or
 505 *               Destination.
 506 *               Source channel      - XCSUDMA_SRC_CHANNEL
 507 *               Destination Channel - XCSUDMA_DST_CHANNEL
 508 * @param        ConfigurValues is a pointer to the structure XCsuDma_Configure
 509 *               whose values are used to configure CSU_DMA core.
 510 *               - SssFifoThesh   When the DST FIFO level >= this value,
 511 *                 the SSS interface signal, "data_out_fifo_level_hit" will be
 512 *                 asserted. This mechanism can be used by the SSS to flow
 513 *                 control data that is being looped back from the SRC DMA.
 514 *                       - Range is (0x10 to 0x7A) threshold is 17 to 123
 515 *                       entries.
 516 *                       - It is valid only for DST CSU_DMA IP.
 517 *               - ApbErr          When accessed to invalid APB the resulting
 518 *                 pslerr will be
 519 *                       - 0 - 1'b0
 520 *                       - 1 - 1'b1
 521 *               - EndianType      Type of endianness
 522 *                       - 0 doesn't change order
 523 *                       - 1 will flip the order.
 524 *               - AxiBurstType....Type of the burst
 525 *                       - 0 will issue INCR type burst
 526 *                       - 1 will issue FIXED type burst
 527 *               - TimeoutValue    Time out value for timers
 528 *                       - 0x000 to 0xFFE are valid inputs
 529 *                       - 0xFFF clears both timers
 530 *               - FifoThresh......Programmed watermark value
 531 *                       - Range is 0x00 to 0x80 (0 to 128 entries).
 532 *               - Acache         Sets the AXI CACHE bits on the AXI Write/Read
 533 *               channel.
 534 *                       - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
 535 *                         for DST channel are always 1, we need to configure
 536 *                         remaining 3 signal support
 537 *                         (Bufferable, Read allocate and Write allocate).
 538 *                       Valid inputs are:
 539 *                       - 0x000 - Cacheable, but do not allocate
 540 *                       - 0x001 - Cacheable and bufferable, but do not allocate
 541 *                       - 0x010 - Cacheable write-through, allocate on reads
 542 *                                 only
 543 *                       - 0x011 - Cacheable write-back, allocate on reads only
 544 *                       - 0x100 - Cacheable write-through, allocate on writes
 545 *                                 only
 546 *                       - 0x101 - Cacheable write-back, allocate on writes only
 547 *                       - 0x110 - Cacheable write-through, allocate on both
 548 *                                 reads and writes
 549 *                       - 0x111 - Cacheable write-back, allocate on both reads
 550 *                                 and writes
 551 *               - RouteBit        To select route
 552 *                       - 0 : Command will be routed normally
 553 *                       - 1 : Command will be routed to APU's cache controller
 554 *               - TimeoutEn       To enable or disable time out counters
 555 *                       - 0 : The 2 Timeout counters are disabled
 556 *                       - 1 : The 2 Timeout counters are enabled
 557 *               - TimeoutPre      Set the prescaler value for the timeout in
 558 *               clk (~2.5ns) cycles
 559 *                       - Range is 0x000(Prescaler enables timer every cycles)
 560 *                         to 0xFFF(Prescaler enables timer every 4096 cycles)
 561 *               - MaxOutCmds      Controls the maximumum number of outstanding
 562 *               AXI read commands issued.
 563 *                       - Range is 0x0(Up to 1 Outstanding Read command
 564 *                         allowed) to 0x8 (Up to 9 Outstanding Read
 565 *                         command allowed)
 566 *
 567 * @return       None.
 568 *
 569 * @note         To use timers timeout value Timeout enable field should be
 570 *               enabled.
 571 *
 572 ******************************************************************************/
 573 void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 574                                         XCsuDma_Configure *ConfigurValues)
 575 {
 576         u32 Data;
 577
 578         /* Verify arguments. */
 579         Xil_AssertVoid(InstancePtr != NULL);
 580         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 581         Xil_AssertVoid(ConfigurValues != NULL);
 582         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 583                                 (Channel == (XCSUDMA_DST_CHANNEL)));
 584         Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE));
 585
 586         Data = (((ConfigurValues->EndianType <<
 587                         (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
 588                         (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) |
 589                 ((ConfigurValues->ApbErr <<
 590                         (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) &
 591                         (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) |
 592                 ((ConfigurValues->AxiBurstType <<
 593                         (u32)(XCSUDMA_CTRL_BURST_SHIFT)) &
 594                         (u32)(XCSUDMA_CTRL_BURST_MASK)) |
 595                 ((ConfigurValues->TimeoutValue <<
 596                         (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) &
 597                         (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) |
 598                 ((ConfigurValues->FifoThresh <<
 599                         (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) &
 600                         (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)));
 601         if(Channel == XCSUDMA_DST_CHANNEL) {
 602                 Data = Data | (u32)((ConfigurValues->SssFifoThesh <<
 603                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) &
 604                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK));
 605         }
 606
 607         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 608                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 609                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
 610
 611         Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 612                         ((u32)(XCSUDMA_CTRL2_OFFSET) +
 613                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) &
 614                                 (u32)(XCSUDMA_CTRL2_RESERVED_MASK));
 615         Data |= (((ConfigurValues->Acache <<
 616                         (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) &
 617                         (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) |
 618                 ((ConfigurValues->RouteBit <<
 619                         (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) &
 620                         (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) |
 621                 ((ConfigurValues->TimeoutEn <<
 622                         (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) &
 623                         (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) |
 624                 ((ConfigurValues->TimeoutPre <<
 625                         (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) &
 626                         (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) |
 627                 ((ConfigurValues->MaxOutCmds) &
 628                         (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
 629
 630         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 631                 ((u32)(XCSUDMA_CTRL2_OFFSET) +
 632                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
 633 }
 634
 635 /*****************************************************************************/
 636 /**
 637 *
 638 * This function updates XCsuDma_Configure structure members with the cofigured
 639 * values of CSU_DMA's Channel.
 640 *
 641 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 642 * @param        Channel represents the type of channel either it is Source or
 643 *               Destination.
 644 *               Source channel      - XCSUDMA_SRC_CHANNEL
 645 *               Destination Channel - XCSUDMA_DST_CHANNEL
 646 * @param        ConfigurValues is a pointer to the structure XCsuDma_Configure
 647 *               whose members are updated with configurations of CSU_DMA core.
 648 *               - SssFifoThesh   When the DST FIFO level >= this value,
 649 *                 the SSS interface signal, "data_out_fifo_level_hit" will be
 650 *                 asserted. This mechanism can be used by the SSS to flow
 651 *                 control data that is being looped back from the SRC DMA.
 652 *                       - Range is (0x10 to 0x7A) threshold is 17 to 123
 653 *                       entries.
 654 *                       - It is valid only for DST CSU_DMA IP.
 655 *               - ApbErr          When accessed to invalid APB the resulting
 656 *                 pslerr will be
 657 *                       - 0 - 1'b0
 658 *                       - 1 - 1'b1
 659 *               - EndianType      Type of endianness
 660 *                       - 0 doesn't change order
 661 *                       - 1 will flip the order.
 662 *               - AxiBurstType....Type of the burst
 663 *                       - 0 will issue INCR type burst
 664 *                       - 1 will issue FIXED type burst
 665 *               - TimeoutValue    Time out value for timers
 666 *                       - 0x000 to 0xFFE are valid inputs
 667 *                       - 0xFFF clears both timers
 668 *               - FifoThresh......Programmed watermark value
 669 *                       - Range is 0x00 to 0x80 (0 to 128 entries).
 670 *               - Acache         Sets the AXI CACHE bits on the AXI Write/Read
 671 *               channel.
 672 *                       - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
 673 *                         for DST channel are always 1, we need to configure
 674 *                         remaining 3 signal support
 675 *                         (Bufferable, Read allocate and Write allocate).
 676 *                       Valid inputs are:
 677 *                       - 0x000 - Cacheable, but do not allocate
 678 *                       - 0x001 - Cacheable and bufferable, but do not allocate
 679 *                       - 0x010 - Cacheable write-through, allocate on reads
 680 *                                 only
 681 *                       - 0x011 - Cacheable write-back, allocate on reads only
 682 *                       - 0x100 - Cacheable write-through, allocate on writes
 683 *                                 only
 684 *                       - 0x101 - Cacheable write-back, allocate on writes only
 685 *                       - 0x110 - Cacheable write-through, allocate on both
 686 *                                 reads and writes
 687 *                       - 0x111 - Cacheable write-back, allocate on both reads
 688 *                                 and writes
 689 *               - RouteBit        To select route
 690 *                       - 0 : Command will be routed based normally
 691 *                       - 1 : Command will be routed to APU's cache controller
 692 *               - TimeoutEn       To enable or disable time out counters
 693 *                       - 0 : The 2 Timeout counters are disabled
 694 *                       - 1 : The 2 Timeout counters are enabled
 695 *               - TimeoutPre      Set the prescaler value for the timeout in
 696 *               clk (~2.5ns) cycles
 697 *                       - Range is 0x000(Prescaler enables timer every cycles)
 698 *                        to 0xFFF(Prescaler enables timer every 4096 cycles)
 699 *               - MaxOutCmds      Controls the maximumum number of outstanding
 700 *               AXI read commands issued.
 701 *                       - Range is 0x0(Up to 1 Outstanding Read command
 702 *                       allowed) to 0x8 (Up to 9 Outstanding Read command
 703 *                       allowed)
 704 *
 705 * @return       None.
 706 *
 707 * @note         None.
 708 *
 709 ******************************************************************************/
 710 void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 711                                 XCsuDma_Configure *ConfigurValues)
 712 {
 713         u32 Data;
 714
 715         /* Verify arguments. */
 716         Xil_AssertVoid(InstancePtr != NULL);
 717         Xil_AssertVoid(ConfigurValues != NULL);
 718         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 719                                 (Channel == (XCSUDMA_DST_CHANNEL)));
 720
 721         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 722                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 723                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 724
 725         if (Channel == (XCSUDMA_DST_CHANNEL)) {
 726                 ConfigurValues->SssFifoThesh =
 727                         (u8)((Data &
 728                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >>
 729                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT));
 730         }
 731         ConfigurValues->ApbErr =
 732                 (u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >>
 733                                 (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT));
 734         ConfigurValues->EndianType =
 735                 (u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >>
 736                                 (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT));
 737         ConfigurValues->AxiBurstType =
 738                 (u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >>
 739                                 (u32)(XCSUDMA_CTRL_BURST_SHIFT));
 740         ConfigurValues->TimeoutValue =
 741                 ((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >>
 742                                 (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT));
 743         ConfigurValues->FifoThresh =
 744                 (u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >>
 745                                 (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT));
 746
 747         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 748                         ((u32)(XCSUDMA_CTRL2_OFFSET) +
 749                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 750
 751         ConfigurValues->Acache =
 752                         (u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >>
 753                                         (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT));
 754         ConfigurValues->RouteBit =
 755                         (u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >>
 756                                         (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT));
 757         ConfigurValues->TimeoutEn =
 758                         (u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >>
 759                                 (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT));
 760         ConfigurValues->TimeoutPre =
 761                         (u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >>
 762                                 (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT));
 763         ConfigurValues->MaxOutCmds =
 764                         (u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
 765
 766 }
 767 /** @} */