1 /**************************************************************************//**
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2 * @file efm32pg1b_devinfo.h
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3 * @brief EFM32PG1B_DEVINFO register and bit field definitions
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5 ******************************************************************************
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7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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35 ******************************************************************************/
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36 /**************************************************************************//**
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37 * @defgroup EFM32PG1B_DEVINFO
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39 *****************************************************************************/
\r
43 __I uint32_t CAL; /**< CRC of DI-page and calibration temperature */
\r
44 uint32_t RESERVED0[9]; /**< Reserved for future use **/
\r
45 __I uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
\r
46 __I uint32_t EUI48H; /**< OUI */
\r
47 __I uint32_t CUSTOMINFO; /**< Custom information */
\r
48 __I uint32_t MEMINFO; /**< Flash page size and misc. chip information */
\r
49 uint32_t RESERVED1[2]; /**< Reserved for future use **/
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50 __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
\r
51 __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
\r
52 __I uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
\r
53 __I uint32_t PART; /**< Part description */
\r
54 __I uint32_t DEVINFOREV; /**< Device information page revision */
\r
55 __I uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
\r
56 uint32_t RESERVED2[2]; /**< Reserved for future use **/
\r
57 __I uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
\r
58 __I uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
\r
59 __I uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
\r
60 __I uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
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61 uint32_t RESERVED3[4]; /**< Reserved for future use **/
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62 __I uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
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63 uint32_t RESERVED4[2]; /**< Reserved for future use **/
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64 __I uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
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65 uint32_t RESERVED5[2]; /**< Reserved for future use **/
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66 __I uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
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67 __I uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
\r
68 __I uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
\r
69 uint32_t RESERVED6[1]; /**< Reserved for future use **/
\r
70 __I uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
\r
71 __I uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
\r
72 __I uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
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73 uint32_t RESERVED7[11]; /**< Reserved for future use **/
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74 __I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
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75 uint32_t RESERVED8[2]; /**< Reserved for future use **/
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76 __I uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
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77 uint32_t RESERVED9[2]; /**< Reserved for future use **/
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78 __I uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
\r
79 __I uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
\r
80 __I uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
\r
81 uint32_t RESERVED10[1]; /**< Reserved for future use **/
\r
82 __I uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
\r
83 __I uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
\r
84 __I uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
\r
85 uint32_t RESERVED11[11]; /**< Reserved for future use **/
\r
86 __I uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
\r
87 __I uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
\r
88 __I uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
\r
89 uint32_t RESERVED12[3]; /**< Reserved for future use **/
\r
90 __I uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
\r
91 __I uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
\r
92 uint32_t RESERVED13[2]; /**< Reserved for future use **/
\r
93 __I uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
\r
94 __I uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
\r
95 __I uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
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96 __I uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */
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97 __I uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */
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98 __I uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */
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99 __I uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
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100 } DEVINFO_TypeDef; /** @} */
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102 /**************************************************************************//**
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103 * @defgroup EFM32PG1B_DEVINFO_BitFields
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105 *****************************************************************************/
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107 /* Bit fields for DEVINFO CAL */
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108 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
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109 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */
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110 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */
\r
111 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
\r
112 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
\r
114 /* Bit fields for DEVINFO EUI48L */
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115 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
\r
116 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */
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117 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */
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118 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */
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119 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */
\r
121 /* Bit fields for DEVINFO EUI48H */
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122 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
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123 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */
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124 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */
\r
126 /* Bit fields for DEVINFO CUSTOMINFO */
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127 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
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128 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */
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129 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */
\r
131 /* Bit fields for DEVINFO MEMINFO */
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132 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
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133 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */
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134 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */
\r
135 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */
\r
136 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */
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137 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */
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138 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */
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139 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
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140 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
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141 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
\r
142 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
\r
143 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */
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144 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */
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145 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */
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146 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */
\r
147 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */
\r
148 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
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149 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */
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150 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */
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151 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */
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152 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */
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153 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */
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154 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */
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156 /* Bit fields for DEVINFO UNIQUEL */
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157 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
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158 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */
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159 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
\r
161 /* Bit fields for DEVINFO UNIQUEH */
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162 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
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163 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */
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164 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
\r
166 /* Bit fields for DEVINFO MSIZE */
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167 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
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168 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */
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169 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */
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170 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */
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171 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */
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173 /* Bit fields for DEVINFO PART */
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174 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */
\r
175 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */
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176 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */
\r
177 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */
\r
178 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */
\r
179 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */
\r
180 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */
\r
181 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */
\r
182 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */
\r
183 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */
\r
184 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */
\r
185 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P 0x00000016UL /**< Mode EFR32ZG1P for DEVINFO_PART */
\r
186 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B 0x00000017UL /**< Mode EFR32ZG1B for DEVINFO_PART */
\r
187 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V 0x00000018UL /**< Mode EFR32ZG1V for DEVINFO_PART */
\r
188 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */
\r
189 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
\r
190 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
\r
191 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
\r
192 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
\r
193 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
\r
194 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
\r
195 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
\r
196 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
\r
197 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
\r
198 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
\r
199 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
\r
200 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
\r
201 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
\r
202 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
\r
203 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
\r
204 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
\r
205 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
\r
206 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
\r
207 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
\r
208 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
\r
209 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
\r
210 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
\r
211 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
\r
212 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
\r
213 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
\r
214 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
\r
215 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
\r
216 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P << 16) /**< Shifted mode EFR32ZG1P for DEVINFO_PART */
\r
217 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B << 16) /**< Shifted mode EFR32ZG1B for DEVINFO_PART */
\r
218 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V << 16) /**< Shifted mode EFR32ZG1V for DEVINFO_PART */
\r
219 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
\r
220 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
\r
221 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
\r
222 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
\r
223 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
\r
224 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
\r
225 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
\r
226 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
\r
227 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
\r
228 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
\r
229 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
\r
230 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
\r
231 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
\r
232 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
\r
233 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
\r
234 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
\r
235 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
\r
236 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
\r
237 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
\r
238 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
\r
239 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
\r
240 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
\r
241 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */
\r
242 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */
\r
244 /* Bit fields for DEVINFO DEVINFOREV */
\r
245 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
\r
246 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */
\r
247 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */
\r
249 /* Bit fields for DEVINFO EMUTEMP */
\r
250 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
\r
251 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */
\r
252 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */
\r
254 /* Bit fields for DEVINFO ADC0CAL0 */
\r
255 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
\r
256 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */
\r
257 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */
\r
258 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */
\r
259 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */
\r
260 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */
\r
261 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */
\r
262 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */
\r
263 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */
\r
264 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */
\r
265 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */
\r
266 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */
\r
267 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */
\r
269 /* Bit fields for DEVINFO ADC0CAL1 */
\r
270 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
\r
271 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */
\r
272 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */
\r
273 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */
\r
274 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */
\r
275 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */
\r
276 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */
\r
277 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */
\r
278 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */
\r
279 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */
\r
280 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */
\r
281 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */
\r
282 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */
\r
284 /* Bit fields for DEVINFO ADC0CAL2 */
\r
285 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
\r
286 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */
\r
287 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */
\r
288 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */
\r
289 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */
\r
291 /* Bit fields for DEVINFO ADC0CAL3 */
\r
292 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
\r
293 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */
\r
294 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */
\r
296 /* Bit fields for DEVINFO HFRCOCAL0 */
\r
297 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
\r
298 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
299 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
300 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
301 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
302 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
303 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
304 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
305 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
306 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
307 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
308 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
309 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
310 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
311 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
312 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
313 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
315 /* Bit fields for DEVINFO HFRCOCAL3 */
\r
316 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
\r
317 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
318 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
319 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
320 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
321 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
322 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
323 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
324 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
325 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
326 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
327 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
328 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
329 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
330 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
331 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
332 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
334 /* Bit fields for DEVINFO HFRCOCAL6 */
\r
335 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
\r
336 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
337 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
338 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
339 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
340 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
341 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
342 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
343 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
344 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
345 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
346 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
347 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
348 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
349 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
350 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
351 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
353 /* Bit fields for DEVINFO HFRCOCAL7 */
\r
354 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
\r
355 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
356 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
357 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
358 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
359 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
360 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
361 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
362 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
363 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
364 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
365 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
366 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
367 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
368 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
369 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
370 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
372 /* Bit fields for DEVINFO HFRCOCAL8 */
\r
373 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
\r
374 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
375 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
376 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
377 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
378 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
379 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
380 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
381 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
382 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
383 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
384 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
385 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
386 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
387 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
388 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
389 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
391 /* Bit fields for DEVINFO HFRCOCAL10 */
\r
392 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
\r
393 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
394 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
395 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
396 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
397 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
398 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
399 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
400 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
401 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
402 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
403 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
404 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
405 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
406 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
407 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
408 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
410 /* Bit fields for DEVINFO HFRCOCAL11 */
\r
411 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
\r
412 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
413 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
414 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
415 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
416 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
417 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
418 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
419 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
420 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
421 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
422 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
423 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
424 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
425 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
426 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
427 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
429 /* Bit fields for DEVINFO HFRCOCAL12 */
\r
430 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
\r
431 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
432 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
433 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
434 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
435 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
436 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
437 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
438 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
439 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
440 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
441 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
442 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
443 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
444 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
445 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
446 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
448 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
\r
449 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
\r
450 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
451 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
452 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
453 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
454 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
455 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
456 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
457 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
458 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
459 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
460 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
461 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
462 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
463 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
464 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
465 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
467 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
\r
468 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
\r
469 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
470 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
471 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
472 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
473 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
474 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
475 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
476 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
477 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
478 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
479 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
480 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
481 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
482 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
483 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
484 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
486 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
\r
487 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
\r
488 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
489 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
490 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
491 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
492 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
493 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
494 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
495 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
496 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
497 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
498 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
499 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
500 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
501 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
502 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
503 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
505 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
\r
506 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
\r
507 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
508 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
509 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
510 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
511 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
512 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
513 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
514 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
515 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
516 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
517 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
518 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
519 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
520 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
521 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
522 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
524 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
\r
525 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
\r
526 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
527 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
528 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
529 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
530 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
531 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
532 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
533 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
534 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
535 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
536 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
537 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
538 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
539 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
540 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
541 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
543 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
\r
544 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
\r
545 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
546 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
547 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
548 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
549 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
550 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
551 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
552 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
553 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
554 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
555 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
556 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
557 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
558 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
559 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
560 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
562 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
\r
563 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
\r
564 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
565 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
566 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
567 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
568 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
569 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
570 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
571 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
572 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
573 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
574 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
575 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
576 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
577 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
578 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
579 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
581 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
\r
582 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
\r
583 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
\r
584 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
\r
585 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
\r
586 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
\r
587 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
\r
588 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
\r
589 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
\r
590 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
\r
591 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
\r
592 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
\r
593 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
\r
594 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
\r
595 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
\r
596 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
\r
597 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
\r
598 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
\r
600 /* Bit fields for DEVINFO VMONCAL0 */
\r
601 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
\r
602 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */
\r
603 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */
\r
604 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */
\r
605 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */
\r
606 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */
\r
607 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */
\r
608 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */
\r
609 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */
\r
610 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */
\r
611 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */
\r
612 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */
\r
613 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */
\r
614 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */
\r
615 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */
\r
616 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */
\r
617 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
\r
619 /* Bit fields for DEVINFO VMONCAL1 */
\r
620 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
\r
621 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */
\r
622 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */
\r
623 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */
\r
624 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */
\r
625 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */
\r
626 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */
\r
627 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */
\r
628 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */
\r
629 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */
\r
630 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */
\r
631 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */
\r
632 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */
\r
633 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */
\r
634 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */
\r
635 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */
\r
636 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
\r
638 /* Bit fields for DEVINFO VMONCAL2 */
\r
639 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
\r
640 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */
\r
641 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */
\r
642 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */
\r
643 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */
\r
644 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */
\r
645 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */
\r
646 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */
\r
647 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */
\r
648 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */
\r
649 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */
\r
650 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */
\r
651 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */
\r
652 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */
\r
653 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */
\r
654 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */
\r
655 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
\r
657 /* Bit fields for DEVINFO IDAC0CAL0 */
\r
658 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
\r
659 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */
\r
660 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */
\r
661 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */
\r
662 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */
\r
663 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */
\r
664 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */
\r
665 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */
\r
666 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
\r
668 /* Bit fields for DEVINFO IDAC0CAL1 */
\r
669 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
\r
670 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */
\r
671 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */
\r
672 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */
\r
673 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */
\r
674 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */
\r
675 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */
\r
676 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */
\r
677 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
\r
679 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
\r
680 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
\r
681 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */
\r
682 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */
\r
683 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */
\r
684 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */
\r
685 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */
\r
686 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */
\r
687 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */
\r
688 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */
\r
690 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
\r
691 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
\r
692 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
\r
693 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
\r
694 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
\r
695 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
\r
696 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
\r
697 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
\r
698 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
\r
699 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
\r
701 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
\r
702 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
\r
703 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
\r
704 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
\r
705 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
\r
706 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
\r
707 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
\r
708 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
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709 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
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710 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
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712 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
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713 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
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714 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
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715 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
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716 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
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717 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
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718 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
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719 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
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720 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
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721 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
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723 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
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724 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
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725 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
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726 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
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727 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
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728 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
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729 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
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730 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
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731 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
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732 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
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734 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
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735 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
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736 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */
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737 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */
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738 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */
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739 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */
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741 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
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742 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
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743 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
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744 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
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745 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
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746 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
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747 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
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748 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
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749 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
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750 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
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752 /** @} End of group EFM32PG1B_DEVINFO */
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753 /** @} End of group Parts */
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