1 /* Copyright 2019 SiFive, Inc */
2 /* SPDX-License-Identifier: Apache-2.0 */
4 #include <metal/machine/platform.h>
6 #ifdef METAL_SIFIVE_FE310_G000_LFROSC
8 #include <metal/drivers/sifive_fe310-g000_lfrosc.h>
9 #include <metal/machine.h>
12 #define METAL_LFROSCCFG_DIV_MASK 0x3F
13 #define METAL_LFROSCCFG_TRIM_SHIFT 16
14 #define METAL_LFROSCCFG_TRIM_MASK (0x1F << METAL_LFROSCCFG_TRIM_SHIFT)
15 #define METAL_LFROSCCFG_EN (1 << 30)
16 #define METAL_LFROSCCFG_RDY (1 << 31)
19 #define METAL_LFCLKMUX_SEL 1
20 #define METAL_LFCLKMUX_EXT_MUX_STATUS (1 << 31)
22 #define LFROSC_REGW(addr) (__METAL_ACCESS_ONCE((__metal_io_u32 *)addr))
24 long __metal_driver_sifive_fe310_g000_lfrosc_get_rate_hz(const struct metal_clock *clock)
26 struct metal_clock *internal_ref = __metal_driver_sifive_fe310_g000_lfrosc_lfrosc(clock);
27 struct metal_clock *external_ref = __metal_driver_sifive_fe310_g000_lfrosc_psdlfaltclk(clock);
29 unsigned long int cfg_reg = __metal_driver_sifive_fe310_g000_lfrosc_config_reg(clock);
30 unsigned long int mux_reg = __metal_driver_sifive_fe310_g000_lfrosc_mux_reg(clock);
32 if(LFROSC_REGW(mux_reg) & METAL_LFCLKMUX_EXT_MUX_STATUS) {
33 return metal_clock_get_rate_hz(external_ref);
36 const unsigned long int div = (LFROSC_REGW(cfg_reg) & METAL_LFROSCCFG_DIV_MASK) + 1;
38 return metal_clock_get_rate_hz(internal_ref) / div;
41 long __metal_driver_sifive_fe310_g000_lfrosc_set_rate_hz(struct metal_clock *clock, long rate)
43 return __metal_driver_sifive_fe310_g000_lfrosc_get_rate_hz(clock);
46 __METAL_DEFINE_VTABLE(__metal_driver_vtable_sifive_fe310_g000_lfrosc) = {
47 .clock.get_rate_hz = &__metal_driver_sifive_fe310_g000_lfrosc_get_rate_hz,
48 .clock.set_rate_hz = &__metal_driver_sifive_fe310_g000_lfrosc_set_rate_hz,
50 #endif /* METAL_SIFIVE_FE310_G000_LFROSC */
52 typedef int no_empty_translation_units;