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31 ******************************************************************************/
33 #ifndef _MICROBLAZE_INTERFACE_H_
34 #define _MICROBLAZE_INTERFACE_H_
36 #include "xil_types.h"
37 #include "xil_assert.h"
38 #include "xil_exception.h"
43 extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
44 extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
45 extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
46 extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
47 extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
48 extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
49 extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
50 extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
51 extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
52 extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
54 extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
55 extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
56 extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
57 extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
58 extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
59 extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
60 extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
61 extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
62 extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
63 extern void microblaze_flush_cache_ext_range(unsigned int cacheaddr,
64 unsigned int len); /* Flush cache ext range */
65 extern void microblaze_invalidate_cache_ext_range(unsigned int cacheaddr,
66 unsigned int len); /* Invalidate cache ext range */
69 extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
70 extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
71 extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
72 extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
74 /* necessary for pre-processor */
75 #define stringify(s) tostring(s)
76 #define tostring(s) #s
78 /* FSL Access Macros */
80 /* Blocking Data Read and Write to FSL no. id */
81 #define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
82 #define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
84 /* Non-blocking Data Read and Write to FSL no. id */
85 #define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
86 #define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
88 /* Blocking Control Read and Write to FSL no. id */
89 #define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
90 #define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
92 /* Non-blocking Control Read and Write to FSL no. id */
93 #define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
94 #define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
96 /* Polling versions of FSL access macros. This makes the FSL access interruptible */
97 #define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
98 "addic\tr18,r0,0\n\t" \
100 : "=d" (val) :: "r18")
102 #define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
103 "addic\tr18,r0,0\n\t" \
105 :: "d" (val) : "r18")
107 #define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
108 "addic\tr18,r0,0\n\t" \
110 : "=d" (val) :: "r18")
112 #define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
113 "addic\tr18,r0,0\n\t" \
115 :: "d" (val) : "r18")
116 /* FSL valid and error check macros. */
117 #define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
118 #define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
119 "andi\t%0,%0,0x10" : "=d" (error))
121 /* Pseudo assembler instructions */
122 #define clz(v) ({ unsigned int _rval; \
123 __asm__ __volatile__ ( \
124 "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
129 #define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
130 #define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
132 #define mb_swapb(v) ({ unsigned int _rval; \
133 __asm__ __volatile__ ( \
134 "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
139 #define mb_swaph(v) ({ unsigned int _rval; \
140 __asm__ __volatile__ ( \
141 "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
146 #define mfgpr(rn) ({ unsigned int _rval; \
147 __asm__ __volatile__ ( \
148 "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
153 #define mfmsr() ({ unsigned int _rval; \
154 __asm__ __volatile__ ( \
155 "mfs\t%0,rmsr\n" : "=d"(_rval) \
160 #define mfear() ({ unsigned int _rval; \
161 __asm__ __volatile__ ( \
162 "mfs\t%0,rear\n" : "=d"(_rval) \
167 #define mfesr() ({ unsigned int _rval; \
168 __asm__ __volatile__ ( \
169 "mfs\t%0,resr\n" : "=d"(_rval) \
174 #define mffsr() ({ unsigned int _rval; \
175 __asm__ __volatile__ ( \
176 "mfs\t%0,rfsr\n" : "=d"(_rval) \
181 #define mfpvr(rn) ({ unsigned int _rval; \
182 __asm__ __volatile__ ( \
183 "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
188 #define mfbtr() ({ unsigned int _rval; \
189 __asm__ __volatile__ ( \
190 "mfs\t%0,rbtr\n" : "=d"(_rval) \
195 #define mfedr() ({ unsigned int _rval; \
196 __asm__ __volatile__ ( \
197 "mfs\t%0,redr\n" : "=d"(_rval) \
202 #define mfpid() ({ unsigned int _rval; \
203 __asm__ __volatile__ ( \
204 "mfs\t%0,rpid\n" : "=d"(_rval)\
209 #define mfzpr() ({ unsigned int _rval; \
210 __asm__ __volatile__ ( \
211 "mfs\t%0,rzpr\n" : "=d"(_rval) \
216 #define mftlbx() ({ unsigned int _rval; \
217 __asm__ __volatile__ ( \
218 "mfs\t%0,rtlbx\n" : "=d"(_rval) \
223 #define mftlblo() ({ unsigned int _rval; \
224 __asm__ __volatile__ ( \
225 "mfs\t%0,rtlblo\n" : "=d"(_rval) \
230 #define mftlbhi() ({ unsigned int _rval; \
231 __asm__ __volatile__ ( \
232 "mfs\t%0,rtlbhi\n" : "=d"(_rval) \
237 #define mfslr() ({ unsigned int _rval; \
238 __asm__ __volatile__ ( \
239 "mfs\t%0,rslr\n" : "=d"(_rval) \
244 #define mfshr() ({ unsigned int _rval; \
245 __asm__ __volatile__ ( \
246 "mfs\t%0,rshr\n" : "=d"(_rval) \
251 #define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
252 "or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
256 #define mtmsr(v) ({ __asm__ __volatile__ ( \
257 "mts\trmsr,%0\n\tnop\n" :: "d" (v) \
262 #define mtfsr(v) ({ __asm__ __volatile__ ( \
263 "mts\trfsr,%0\n\tnop\n" :: "d" (v) \
267 #define mtpid(v) ({ __asm__ __volatile__ ( \
268 "mts\trpid,%0\n\tnop\n" :: "d" (v) \
272 #define mtzpr(v) ({ __asm__ __volatile__ ( \
273 "mts\trzpr,%0\n\tnop\n" :: "d" (v) \
277 #define mttlbx(v) ({ __asm__ __volatile__ ( \
278 "mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
282 #define mttlblo(v) ({ __asm__ __volatile__ ( \
283 "mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
287 #define mttlbhi(v) ({ __asm__ __volatile__ ( \
288 "mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
292 #define mttlbsx(v) ({ __asm__ __volatile__ ( \
293 "mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
297 #define mtslr(v) ({ __asm__ __volatile__ ( \
298 "mts\trslr,%0\n\tnop\n" :: "d" (v) \
302 #define mtshr(v) ({ __asm__ __volatile__ ( \
303 "mts\trshr,%0\n\tnop\n" :: "d" (v) \
307 #define lwx(address) ({ unsigned int _rval; \
308 __asm__ __volatile__ ( \
309 "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
314 #define lwr(address) ({ unsigned int _rval; \
315 __asm__ __volatile__ ( \
316 "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
321 #define lhur(address) ({ unsigned int _rval; \
322 __asm__ __volatile__ ( \
323 "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
328 #define lbur(address) ({ unsigned int _rval; \
329 __asm__ __volatile__ ( \
330 "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
335 #define swx(address, data) ({ __asm__ __volatile__ ( \
336 "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
340 #define swr(address, data) ({ __asm__ __volatile__ ( \
341 "swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
345 #define shr(address, data) ({ __asm__ __volatile__ ( \
346 "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
350 #define sbr(address, data) ({ __asm__ __volatile__ ( \
351 "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
355 #define microblaze_getfpex_operand_a() ({ \
356 extern unsigned int mb_fpex_op_a; \
360 #define microblaze_getfpex_operand_b() ({ \
361 extern unsigned int mb_fpex_op_b; \
365 /* Deprecated MicroBlaze FSL macros */
366 #define microblaze_bread_datafsl(val, id) getfsl(val,id)
367 #define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
368 #define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
369 #define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
370 #define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
371 #define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
372 #define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
373 #define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
378 #endif // _MICROBLAZE_INTERFACE_H_