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   1 /*\r
   2     FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
   7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
   8      *    Complete, revised, and edited pdf reference manuals are also       *\r
   9      *    available.                                                         *\r
  10      *                                                                       *\r
  11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  12      *    ensuring you get running as quickly as possible and with an        *\r
  13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  14      *    the FreeRTOS project to continue with its mission of providing     *\r
  15      *    professional grade, cross platform, de facto standard solutions    *\r
  16      *    for microcontrollers - completely free of charge!                  *\r
  17      *                                                                       *\r
  18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  19      *                                                                       *\r
  20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  21      *                                                                       *\r
  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43     \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
  48      *                                                                       *\r
  49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  50      *                                                                       *\r
  51     ***************************************************************************\r
  52 \r
  53     \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information, \r
  55     license and contact details.\r
  56     \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  58     including FreeRTOS+Trace - an indispensable productivity tool.\r
  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
  61     the code with commercial support, indemnification, and middleware, under \r
  62     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
  63     provide a safety engineered and independently SIL3 certified version under \r
  64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  65 */\r
  66 \r
  67 /*-----------------------------------------------------------\r
  68  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  69  *----------------------------------------------------------*/\r
  70 \r
  71 /* Scheduler includes. */\r
  72 #include "FreeRTOS.h"\r
  73 #include "task.h"\r
  74 \r
  75 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  76 defined.  The value should also ensure backward compatibility.\r
  77 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  78 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  79         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  80 #endif\r
  81 \r
  82 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
  83         #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
  84 #endif\r
  85 \r
  86 /* Constants required to manipulate the NVIC. */\r
  87 #define portNVIC_SYSTICK_CTRL           ( ( volatile unsigned long *) 0xe000e010 )\r
  88 #define portNVIC_SYSTICK_LOAD           ( ( volatile unsigned long *) 0xe000e014 )\r
  89 #define portNVIC_INT_CTRL                       ( ( volatile unsigned long *) 0xe000ed04 )\r
  90 #define portNVIC_SYSPRI2                        ( ( volatile unsigned long *) 0xe000ed20 )\r
  91 #define portNVIC_SYSTICK_CLK            0x00000004\r
  92 #define portNVIC_SYSTICK_INT            0x00000002\r
  93 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  94 #define portNVIC_PENDSVSET                      0x10000000\r
  95 #define portNVIC_PENDSV_PRI                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
  96 #define portNVIC_SYSTICK_PRI            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
  97 \r
  98 /* Constants required to set up the initial stack. */\r
  99 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 100 \r
 101 /* The priority used by the kernel is assigned to a variable to make access\r
 102 from inline assembler easier. */\r
 103 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
 104 \r
 105 /* Each task maintains its own interrupt status in the critical nesting\r
 106 variable. */\r
 107 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 108 \r
 109 /*\r
 110  * Setup the timer to generate the tick interrupts.\r
 111  */\r
 112 static void prvSetupTimerInterrupt( void );\r
 113 \r
 114 /*\r
 115  * Exception handlers.\r
 116  */\r
 117 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 118 void xPortSysTickHandler( void );\r
 119 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 120 \r
 121 /*\r
 122  * Start first task is a separate function so it can be tested in isolation.\r
 123  */\r
 124 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 125 \r
 126 /*-----------------------------------------------------------*/\r
 127 \r
 128 /*\r
 129  * See header file for description.\r
 130  */\r
 131 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 132 {\r
 133         /* Simulate the stack frame as it would be created by a context switch\r
 134         interrupt. */\r
 135         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 136         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 137         pxTopOfStack--;\r
 138         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 139         pxTopOfStack--;\r
 140         *pxTopOfStack = 0;      /* LR */\r
 141         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 142         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 143         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 144 \r
 145         return pxTopOfStack;\r
 146 }\r
 147 /*-----------------------------------------------------------*/\r
 148 \r
 149 void vPortSVCHandler( void )\r
 150 {\r
 151         __asm volatile (\r
 152                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 153                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 154                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 155                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 156                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 157                                         "       mov r0, #0                                              \n"\r
 158                                         "       msr     basepri, r0                                     \n"\r
 159                                         "       orr r14, #0xd                                   \n"\r
 160                                         "       bx r14                                                  \n"\r
 161                                         "                                                                       \n"\r
 162                                         "       .align 2                                                \n"\r
 163                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 164                                 );\r
 165 }\r
 166 /*-----------------------------------------------------------*/\r
 167 \r
 168 static void prvPortStartFirstTask( void )\r
 169 {\r
 170         __asm volatile(\r
 171                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 172                                         " ldr r0, [r0]                  \n"\r
 173                                         " ldr r0, [r0]                  \n"\r
 174                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 175                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 176                                         " svc 0                                 \n" /* System call to start first task. */\r
 177                                         " nop                                   \n"\r
 178                                 );\r
 179 }\r
 180 /*-----------------------------------------------------------*/\r
 181 \r
 182 /*\r
 183  * See header file for description.\r
 184  */\r
 185 portBASE_TYPE xPortStartScheduler( void )\r
 186 {\r
 187         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 188         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 189         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 190 \r
 191         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 192         here already. */\r
 193         prvSetupTimerInterrupt();\r
 194 \r
 195         /* Initialise the critical nesting count ready for the first task. */\r
 196         uxCriticalNesting = 0;\r
 197 \r
 198         /* Start the first task. */\r
 199         prvPortStartFirstTask();\r
 200 \r
 201         /* Should not get here! */\r
 202         return 0;\r
 203 }\r
 204 /*-----------------------------------------------------------*/\r
 205 \r
 206 void vPortEndScheduler( void )\r
 207 {\r
 208         /* It is unlikely that the CM3 port will require this function as there\r
 209         is nothing to return to.  */\r
 210 }\r
 211 /*-----------------------------------------------------------*/\r
 212 \r
 213 void vPortYieldFromISR( void )\r
 214 {\r
 215         /* Set a PendSV to request a context switch. */\r
 216         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 217 }\r
 218 /*-----------------------------------------------------------*/\r
 219 \r
 220 void vPortEnterCritical( void )\r
 221 {\r
 222         portDISABLE_INTERRUPTS();\r
 223         uxCriticalNesting++;\r
 224 }\r
 225 /*-----------------------------------------------------------*/\r
 226 \r
 227 void vPortExitCritical( void )\r
 228 {\r
 229         uxCriticalNesting--;\r
 230         if( uxCriticalNesting == 0 )\r
 231         {\r
 232                 portENABLE_INTERRUPTS();\r
 233         }\r
 234 }\r
 235 /*-----------------------------------------------------------*/\r
 236 \r
 237 void xPortPendSVHandler( void )\r
 238 {\r
 239         /* This is a naked function. */\r
 240 \r
 241         __asm volatile\r
 242         (\r
 243         "       mrs r0, psp                                                     \n"\r
 244         "                                                                               \n"\r
 245         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 246         "       ldr     r2, [r3]                                                \n"\r
 247         "                                                                               \n"\r
 248         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 249         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 250         "                                                                               \n"\r
 251         "       stmdb sp!, {r3, r14}                            \n"\r
 252         "       mov r0, %0                                                      \n"\r
 253         "       msr basepri, r0                                         \n"\r
 254         "       bl vTaskSwitchContext                           \n"\r
 255         "       mov r0, #0                                                      \n"\r
 256         "       msr basepri, r0                                         \n"\r
 257         "       ldmia sp!, {r3, r14}                            \n"\r
 258         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 259         "       ldr r1, [r3]                                            \n"\r
 260         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 261         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 262         "       msr psp, r0                                                     \n"\r
 263         "       bx r14                                                          \n"\r
 264         "                                                                               \n"\r
 265         "       .align 2                                                        \n"\r
 266         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 267         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 268         );\r
 269 }\r
 270 /*-----------------------------------------------------------*/\r
 271 \r
 272 void xPortSysTickHandler( void )\r
 273 {\r
 274 unsigned long ulDummy;\r
 275 \r
 276         /* If using preemption, also force a context switch. */\r
 277         #if configUSE_PREEMPTION == 1\r
 278                 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 279         #endif\r
 280 \r
 281         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 282         {\r
 283                 vTaskIncrementTick();\r
 284         }\r
 285         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 286 }\r
 287 /*-----------------------------------------------------------*/\r
 288 \r
 289 /*\r
 290  * Setup the systick timer to generate the tick interrupts at the required\r
 291  * frequency.\r
 292  */\r
 293 void prvSetupTimerInterrupt( void )\r
 294 {\r
 295         /* Configure SysTick to interrupt at the requested rate. */\r
 296         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 297         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 298 }\r
 299 /*-----------------------------------------------------------*/\r
 300 \r