1 /**************************************************************************//**
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2 * @file efm32wg_dmactrl.h
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3 * @brief EFM32WG_DMACTRL register and bit field definitions
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5 ******************************************************************************
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7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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35 ******************************************************************************/
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37 /**************************************************************************//**
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38 * @defgroup EFM32WG_DMACTRL_BitFields
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40 *****************************************************************************/
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41 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
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42 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
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43 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
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44 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
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45 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
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46 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
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47 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
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48 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
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49 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
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50 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
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51 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
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52 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
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53 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
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54 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
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55 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
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56 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
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57 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
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58 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
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59 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
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60 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
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61 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
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62 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
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63 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
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64 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
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65 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
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66 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
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67 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
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68 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
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69 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
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70 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
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71 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
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72 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
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73 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
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74 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
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75 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
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76 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
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77 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
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78 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
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79 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
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80 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
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81 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
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82 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
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83 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
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84 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
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85 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
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86 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
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87 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
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88 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
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89 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
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90 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
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91 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
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92 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
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93 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
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94 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
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95 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
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96 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
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97 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
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98 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
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99 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
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100 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
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101 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
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102 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
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103 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
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104 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
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105 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
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106 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
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107 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
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108 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
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109 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
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110 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
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111 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
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112 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
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113 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
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114 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
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115 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
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116 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
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117 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
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118 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
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119 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
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120 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
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121 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
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122 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
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123 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
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124 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
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125 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
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126 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
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127 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
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128 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
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129 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
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130 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
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131 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
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132 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
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133 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
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134 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
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135 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
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136 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
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138 /** @} End of group EFM32WG_DMA */
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139 /** @} End of group Parts */
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