2 * Copyright (c) 2014, Texas Instruments Incorporated
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3 * All rights reserved.
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5 * Redistribution and use in source and binary forms, with or without
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6 * modification, are permitted provided that the following conditions
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9 * * Redistributions of source code must retain the above copyright
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10 * notice, this list of conditions and the following disclaimer.
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12 * * Redistributions in binary form must reproduce the above copyright
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13 * notice, this list of conditions and the following disclaimer in the
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14 * documentation and/or other materials provided with the distribution.
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16 * * Neither the name of Texas Instruments Incorporated nor the names of
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17 * its contributors may be used to endorse or promote products derived
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18 * from this software without specific prior written permission.
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 /********************************************************************
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34 * Standard register and bit definitions for the Texas Instruments
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35 * MSP430 microcontroller.
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37 * This file supports assembler and C development for
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38 * MSP430FR5XX_FR6XXGENERIC device.
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40 * Texas Instruments, Version 1.0
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45 ********************************************************************/
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47 #ifndef __msp430FR5XX_FR6XXGENERIC
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48 #define __msp430FR5XX_FR6XXGENERIC
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50 //#define __MSP430_HEADER_VERSION__ 1125
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52 #ifdef __IAR_SYSTEMS_ICC__
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53 #ifndef _SYSTEM_BUILD
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54 #pragma system_include
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58 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
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59 #error msp430fr5xx_6xxgeneric.h file for use with ICC430/A430 only
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63 #ifdef __IAR_SYSTEMS_ICC__
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65 #pragma language=extended
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67 #define DEFC(name, address) __no_init volatile unsigned char name @ address;
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68 #define DEFW(name, address) __no_init volatile unsigned short name @ address;
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70 #define DEFCW(name, address) __no_init union \
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74 volatile unsigned char name##_L; \
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75 volatile unsigned char name##_H; \
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77 volatile unsigned short name; \
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80 #define READ_ONLY_DEFCW(name, address) __no_init union \
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84 volatile READ_ONLY unsigned char name##_L; \
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85 volatile READ_ONLY unsigned char name##_H; \
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87 volatile READ_ONLY unsigned short name; \
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91 #if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__
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92 #define __ACCESS_20BIT_REG__ void __data20 * volatile
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94 #define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */
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97 #define DEFA(name, address) __no_init union \
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101 volatile unsigned char name##_L; \
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102 volatile unsigned char name##_H; \
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106 volatile unsigned short name##L; \
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107 volatile unsigned short name##H; \
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109 __ACCESS_20BIT_REG__ name; \
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112 #endif /* __IAR_SYSTEMS_ICC__ */
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115 #ifdef __IAR_SYSTEMS_ASM__
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116 #define DEFC(name, address) sfrb name = address;
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117 #define DEFW(name, address) sfrw name = address;
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119 #define DEFCW(name, address) sfrbw name, name##_L, name##_H, address;
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120 sfrbw macro name, name_L, name_H, address;
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121 sfrb name_L = address;
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122 sfrb name_H = address+1;
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123 sfrw name = address;
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126 #define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address;
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127 const_sfrbw macro name, name_L, name_H, address;
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128 const sfrb name_L = address;
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129 const sfrb name_H = address+1;
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130 const sfrw name = address;
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133 #define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address;
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134 sfrba macro name, nameL, nameH, name_L, name_H, address;
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135 sfrb name_L = address;
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136 sfrb name_H = address+1;
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137 sfrw nameL = address;
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138 sfrw nameH = address+2;
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139 sfrl name = address;
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142 #endif /* __IAR_SYSTEMS_ASM__*/
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147 #define READ_ONLY const
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150 /************************************************************
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152 ************************************************************/
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154 #define BIT0 (0x0001u)
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155 #define BIT1 (0x0002u)
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156 #define BIT2 (0x0004u)
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157 #define BIT3 (0x0008u)
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158 #define BIT4 (0x0010u)
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159 #define BIT5 (0x0020u)
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160 #define BIT6 (0x0040u)
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161 #define BIT7 (0x0080u)
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162 #define BIT8 (0x0100u)
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163 #define BIT9 (0x0200u)
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164 #define BITA (0x0400u)
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165 #define BITB (0x0800u)
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166 #define BITC (0x1000u)
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167 #define BITD (0x2000u)
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168 #define BITE (0x4000u)
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169 #define BITF (0x8000u)
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171 /************************************************************
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172 * STATUS REGISTER BITS
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173 ************************************************************/
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175 #define C (0x0001u)
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176 #define Z (0x0002u)
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177 #define N (0x0004u)
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178 #define V (0x0100u)
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179 #define GIE (0x0008u)
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180 #define CPUOFF (0x0010u)
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181 #define OSCOFF (0x0020u)
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182 #define SCG0 (0x0040u)
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183 #define SCG1 (0x0080u)
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185 /* Low Power Modes coded with Bits 4-7 in SR */
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187 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */
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188 #define LPM0 (CPUOFF)
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189 #define LPM1 (SCG0+CPUOFF)
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190 #define LPM2 (SCG1+CPUOFF)
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191 #define LPM3 (SCG1+SCG0+CPUOFF)
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192 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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193 /* End #defines for assembler */
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195 #else /* Begin #defines for C */
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196 #define LPM0_bits (CPUOFF)
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197 #define LPM1_bits (SCG0+CPUOFF)
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198 #define LPM2_bits (SCG1+CPUOFF)
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199 #define LPM3_bits (SCG1+SCG0+CPUOFF)
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200 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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204 #if __MSP430_HEADER_VERSION__ < 1107
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205 #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
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206 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
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207 #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
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208 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
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209 #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
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210 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
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211 #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
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212 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
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213 #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
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214 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
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216 #define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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217 #define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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218 #define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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219 #define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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220 #define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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221 #define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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222 #define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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223 #define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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224 #define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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225 #define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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227 #endif /* End #defines for C */
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229 /************************************************************
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231 ************************************************************/
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232 #define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
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234 #if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \
\r
235 || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \
\r
236 || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \
\r
237 || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)
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238 #define __MSP430_HAS_TxA7__
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240 #if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \
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241 || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)
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242 #define __MSP430_HAS_TxB7__
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244 #if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \
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245 || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)
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246 #define __MSP430_HAS_TxD7__
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248 #if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)
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249 #define __MSP430_HAS_USCI_Ax__
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251 #if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)
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252 #define __MSP430_HAS_USCI_Bx__
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254 #if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)
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255 #define __MSP430_HAS_EUSCI_Ax__
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257 #if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)
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258 #define __MSP430_HAS_EUSCI_Bx__
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260 #ifdef __MSP430_HAS_EUSCI_B0__
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261 #define __MSP430_HAS_EUSCI_Bx__
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264 /************************************************************
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266 ************************************************************/
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267 #ifdef __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */
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269 #define OFS_ADC12CTL0 (0x0000u) /* ADC12 B Control 0 */
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270 #define OFS_ADC12CTL0_L OFS_ADC12CTL0
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271 #define OFS_ADC12CTL0_H OFS_ADC12CTL0+1
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272 #define OFS_ADC12CTL1 (0x0002u) /* ADC12 B Control 1 */
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273 #define OFS_ADC12CTL1_L OFS_ADC12CTL1
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274 #define OFS_ADC12CTL1_H OFS_ADC12CTL1+1
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275 #define OFS_ADC12CTL2 (0x0004u) /* ADC12 B Control 2 */
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276 #define OFS_ADC12CTL2_L OFS_ADC12CTL2
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277 #define OFS_ADC12CTL2_H OFS_ADC12CTL2+1
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278 #define OFS_ADC12CTL3 (0x0006u) /* ADC12 B Control 3 */
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279 #define OFS_ADC12CTL3_L OFS_ADC12CTL3
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280 #define OFS_ADC12CTL3_H OFS_ADC12CTL3+1
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281 #define OFS_ADC12LO (0x0008u) /* ADC12 B Window Comparator High Threshold */
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282 #define OFS_ADC12LO_L OFS_ADC12LO
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283 #define OFS_ADC12LO_H OFS_ADC12LO+1
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284 #define OFS_ADC12HI (0x000Au) /* ADC12 B Window Comparator High Threshold */
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285 #define OFS_ADC12HI_L OFS_ADC12HI
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286 #define OFS_ADC12HI_H OFS_ADC12HI+1
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287 #define OFS_ADC12IFGR0 (0x000Cu) /* ADC12 B Interrupt Flag 0 */
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288 #define OFS_ADC12IFGR0_L OFS_ADC12IFGR0
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289 #define OFS_ADC12IFGR0_H OFS_ADC12IFGR0+1
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290 #define OFS_ADC12IFGR1 (0x000Eu) /* ADC12 B Interrupt Flag 1 */
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291 #define OFS_ADC12IFGR1_L OFS_ADC12IFGR1
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292 #define OFS_ADC12IFGR1_H OFS_ADC12IFGR1+1
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293 #define OFS_ADC12IFGR2 (0x0010u) /* ADC12 B Interrupt Flag 2 */
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294 #define OFS_ADC12IFGR2_L OFS_ADC12IFGR2
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295 #define OFS_ADC12IFGR2_H OFS_ADC12IFGR2+1
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296 #define OFS_ADC12IER0 (0x0012u) /* ADC12 B Interrupt Enable 0 */
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297 #define OFS_ADC12IER0_L OFS_ADC12IER0
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298 #define OFS_ADC12IER0_H OFS_ADC12IER0+1
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299 #define OFS_ADC12IER1 (0x0014u) /* ADC12 B Interrupt Enable 1 */
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300 #define OFS_ADC12IER1_L OFS_ADC12IER1
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301 #define OFS_ADC12IER1_H OFS_ADC12IER1+1
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302 #define OFS_ADC12IER2 (0x0016u) /* ADC12 B Interrupt Enable 2 */
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303 #define OFS_ADC12IER2_L OFS_ADC12IER2
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304 #define OFS_ADC12IER2_H OFS_ADC12IER2+1
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305 #define OFS_ADC12IV (0x0018u) /* ADC12 B Interrupt Vector Word */
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306 #define OFS_ADC12IV_L OFS_ADC12IV
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307 #define OFS_ADC12IV_H OFS_ADC12IV+1
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309 #define OFS_ADC12MCTL0 (0x0020u) /* ADC12 Memory Control 0 */
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310 #define OFS_ADC12MCTL0_L OFS_ADC12MCTL0
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311 #define OFS_ADC12MCTL0_H OFS_ADC12MCTL0+1
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312 #define OFS_ADC12MCTL1 (0x0022u) /* ADC12 Memory Control 1 */
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313 #define OFS_ADC12MCTL1_L OFS_ADC12MCTL1
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314 #define OFS_ADC12MCTL1_H OFS_ADC12MCTL1+1
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315 #define OFS_ADC12MCTL2 (0x0024u) /* ADC12 Memory Control 2 */
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316 #define OFS_ADC12MCTL2_L OFS_ADC12MCTL2
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317 #define OFS_ADC12MCTL2_H OFS_ADC12MCTL2+1
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318 #define OFS_ADC12MCTL3 (0x0026u) /* ADC12 Memory Control 3 */
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319 #define OFS_ADC12MCTL3_L OFS_ADC12MCTL3
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320 #define OFS_ADC12MCTL3_H OFS_ADC12MCTL3+1
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321 #define OFS_ADC12MCTL4 (0x0028u) /* ADC12 Memory Control 4 */
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322 #define OFS_ADC12MCTL4_L OFS_ADC12MCTL4
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323 #define OFS_ADC12MCTL4_H OFS_ADC12MCTL4+1
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324 #define OFS_ADC12MCTL5 (0x002Au) /* ADC12 Memory Control 5 */
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325 #define OFS_ADC12MCTL5_L OFS_ADC12MCTL5
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326 #define OFS_ADC12MCTL5_H OFS_ADC12MCTL5+1
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327 #define OFS_ADC12MCTL6 (0x002Cu) /* ADC12 Memory Control 6 */
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328 #define OFS_ADC12MCTL6_L OFS_ADC12MCTL6
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329 #define OFS_ADC12MCTL6_H OFS_ADC12MCTL6+1
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330 #define OFS_ADC12MCTL7 (0x002Eu) /* ADC12 Memory Control 7 */
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331 #define OFS_ADC12MCTL7_L OFS_ADC12MCTL7
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332 #define OFS_ADC12MCTL7_H OFS_ADC12MCTL7+1
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333 #define OFS_ADC12MCTL8 (0x0030u) /* ADC12 Memory Control 8 */
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334 #define OFS_ADC12MCTL8_L OFS_ADC12MCTL8
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335 #define OFS_ADC12MCTL8_H OFS_ADC12MCTL8+1
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336 #define OFS_ADC12MCTL9 (0x0032u) /* ADC12 Memory Control 9 */
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337 #define OFS_ADC12MCTL9_L OFS_ADC12MCTL9
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338 #define OFS_ADC12MCTL9_H OFS_ADC12MCTL9+1
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339 #define OFS_ADC12MCTL10 (0x0034u) /* ADC12 Memory Control 10 */
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340 #define OFS_ADC12MCTL10_L OFS_ADC12MCTL10
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341 #define OFS_ADC12MCTL10_H OFS_ADC12MCTL10+1
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342 #define OFS_ADC12MCTL11 (0x0036u) /* ADC12 Memory Control 11 */
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343 #define OFS_ADC12MCTL11_L OFS_ADC12MCTL11
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344 #define OFS_ADC12MCTL11_H OFS_ADC12MCTL11+1
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345 #define OFS_ADC12MCTL12 (0x0038u) /* ADC12 Memory Control 12 */
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346 #define OFS_ADC12MCTL12_L OFS_ADC12MCTL12
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347 #define OFS_ADC12MCTL12_H OFS_ADC12MCTL12+1
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348 #define OFS_ADC12MCTL13 (0x003Au) /* ADC12 Memory Control 13 */
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349 #define OFS_ADC12MCTL13_L OFS_ADC12MCTL13
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350 #define OFS_ADC12MCTL13_H OFS_ADC12MCTL13+1
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351 #define OFS_ADC12MCTL14 (0x003Cu) /* ADC12 Memory Control 14 */
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352 #define OFS_ADC12MCTL14_L OFS_ADC12MCTL14
\r
353 #define OFS_ADC12MCTL14_H OFS_ADC12MCTL14+1
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354 #define OFS_ADC12MCTL15 (0x003Eu) /* ADC12 Memory Control 15 */
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355 #define OFS_ADC12MCTL15_L OFS_ADC12MCTL15
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356 #define OFS_ADC12MCTL15_H OFS_ADC12MCTL15+1
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357 #define OFS_ADC12MCTL16 (0x0040u) /* ADC12 Memory Control 16 */
\r
358 #define OFS_ADC12MCTL16_L OFS_ADC12MCTL16
\r
359 #define OFS_ADC12MCTL16_H OFS_ADC12MCTL16+1
\r
360 #define OFS_ADC12MCTL17 (0x0042u) /* ADC12 Memory Control 17 */
\r
361 #define OFS_ADC12MCTL17_L OFS_ADC12MCTL17
\r
362 #define OFS_ADC12MCTL17_H OFS_ADC12MCTL17+1
\r
363 #define OFS_ADC12MCTL18 (0x0044u) /* ADC12 Memory Control 18 */
\r
364 #define OFS_ADC12MCTL18_L OFS_ADC12MCTL18
\r
365 #define OFS_ADC12MCTL18_H OFS_ADC12MCTL18+1
\r
366 #define OFS_ADC12MCTL19 (0x0046u) /* ADC12 Memory Control 19 */
\r
367 #define OFS_ADC12MCTL19_L OFS_ADC12MCTL19
\r
368 #define OFS_ADC12MCTL19_H OFS_ADC12MCTL19+1
\r
369 #define OFS_ADC12MCTL20 (0x0048u) /* ADC12 Memory Control 20 */
\r
370 #define OFS_ADC12MCTL20_L OFS_ADC12MCTL20
\r
371 #define OFS_ADC12MCTL20_H OFS_ADC12MCTL20+1
\r
372 #define OFS_ADC12MCTL21 (0x004Au) /* ADC12 Memory Control 21 */
\r
373 #define OFS_ADC12MCTL21_L OFS_ADC12MCTL21
\r
374 #define OFS_ADC12MCTL21_H OFS_ADC12MCTL21+1
\r
375 #define OFS_ADC12MCTL22 (0x004Cu) /* ADC12 Memory Control 22 */
\r
376 #define OFS_ADC12MCTL22_L OFS_ADC12MCTL22
\r
377 #define OFS_ADC12MCTL22_H OFS_ADC12MCTL22+1
\r
378 #define OFS_ADC12MCTL23 (0x004Eu) /* ADC12 Memory Control 23 */
\r
379 #define OFS_ADC12MCTL23_L OFS_ADC12MCTL23
\r
380 #define OFS_ADC12MCTL23_H OFS_ADC12MCTL23+1
\r
381 #define OFS_ADC12MCTL24 (0x0050u) /* ADC12 Memory Control 24 */
\r
382 #define OFS_ADC12MCTL24_L OFS_ADC12MCTL24
\r
383 #define OFS_ADC12MCTL24_H OFS_ADC12MCTL24+1
\r
384 #define OFS_ADC12MCTL25 (0x0052u) /* ADC12 Memory Control 25 */
\r
385 #define OFS_ADC12MCTL25_L OFS_ADC12MCTL25
\r
386 #define OFS_ADC12MCTL25_H OFS_ADC12MCTL25+1
\r
387 #define OFS_ADC12MCTL26 (0x0054u) /* ADC12 Memory Control 26 */
\r
388 #define OFS_ADC12MCTL26_L OFS_ADC12MCTL26
\r
389 #define OFS_ADC12MCTL26_H OFS_ADC12MCTL26+1
\r
390 #define OFS_ADC12MCTL27 (0x0056u) /* ADC12 Memory Control 27 */
\r
391 #define OFS_ADC12MCTL27_L OFS_ADC12MCTL27
\r
392 #define OFS_ADC12MCTL27_H OFS_ADC12MCTL27+1
\r
393 #define OFS_ADC12MCTL28 (0x0058u) /* ADC12 Memory Control 28 */
\r
394 #define OFS_ADC12MCTL28_L OFS_ADC12MCTL28
\r
395 #define OFS_ADC12MCTL28_H OFS_ADC12MCTL28+1
\r
396 #define OFS_ADC12MCTL29 (0x005Au) /* ADC12 Memory Control 29 */
\r
397 #define OFS_ADC12MCTL29_L OFS_ADC12MCTL29
\r
398 #define OFS_ADC12MCTL29_H OFS_ADC12MCTL29+1
\r
399 #define OFS_ADC12MCTL30 (0x005Cu) /* ADC12 Memory Control 30 */
\r
400 #define OFS_ADC12MCTL30_L OFS_ADC12MCTL30
\r
401 #define OFS_ADC12MCTL30_H OFS_ADC12MCTL30+1
\r
402 #define OFS_ADC12MCTL31 (0x005Eu) /* ADC12 Memory Control 31 */
\r
403 #define OFS_ADC12MCTL31_L OFS_ADC12MCTL31
\r
404 #define OFS_ADC12MCTL31_H OFS_ADC12MCTL31+1
\r
405 #define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
\r
406 #ifndef __IAR_SYSTEMS_ICC__
\r
407 #define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
\r
409 #define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */
\r
412 #define OFS_ADC12MEM0 (0x0060u) /* ADC12 Conversion Memory 0 */
\r
413 #define OFS_ADC12MEM0_L OFS_ADC12MEM0
\r
414 #define OFS_ADC12MEM0_H OFS_ADC12MEM0+1
\r
415 #define OFS_ADC12MEM1 (0x0062u) /* ADC12 Conversion Memory 1 */
\r
416 #define OFS_ADC12MEM1_L OFS_ADC12MEM1
\r
417 #define OFS_ADC12MEM1_H OFS_ADC12MEM1+1
\r
418 #define OFS_ADC12MEM2 (0x0064u) /* ADC12 Conversion Memory 2 */
\r
419 #define OFS_ADC12MEM2_L OFS_ADC12MEM2
\r
420 #define OFS_ADC12MEM2_H OFS_ADC12MEM2+1
\r
421 #define OFS_ADC12MEM3 (0x0066u) /* ADC12 Conversion Memory 3 */
\r
422 #define OFS_ADC12MEM3_L OFS_ADC12MEM3
\r
423 #define OFS_ADC12MEM3_H OFS_ADC12MEM3+1
\r
424 #define OFS_ADC12MEM4 (0x0068u) /* ADC12 Conversion Memory 4 */
\r
425 #define OFS_ADC12MEM4_L OFS_ADC12MEM4
\r
426 #define OFS_ADC12MEM4_H OFS_ADC12MEM4+1
\r
427 #define OFS_ADC12MEM5 (0x006Au) /* ADC12 Conversion Memory 5 */
\r
428 #define OFS_ADC12MEM5_L OFS_ADC12MEM5
\r
429 #define OFS_ADC12MEM5_H OFS_ADC12MEM5+1
\r
430 #define OFS_ADC12MEM6 (0x006Cu) /* ADC12 Conversion Memory 6 */
\r
431 #define OFS_ADC12MEM6_L OFS_ADC12MEM6
\r
432 #define OFS_ADC12MEM6_H OFS_ADC12MEM6+1
\r
433 #define OFS_ADC12MEM7 (0x006Eu) /* ADC12 Conversion Memory 7 */
\r
434 #define OFS_ADC12MEM7_L OFS_ADC12MEM7
\r
435 #define OFS_ADC12MEM7_H OFS_ADC12MEM7+1
\r
436 #define OFS_ADC12MEM8 (0x0070u) /* ADC12 Conversion Memory 8 */
\r
437 #define OFS_ADC12MEM8_L OFS_ADC12MEM8
\r
438 #define OFS_ADC12MEM8_H OFS_ADC12MEM8+1
\r
439 #define OFS_ADC12MEM9 (0x0072u) /* ADC12 Conversion Memory 9 */
\r
440 #define OFS_ADC12MEM9_L OFS_ADC12MEM9
\r
441 #define OFS_ADC12MEM9_H OFS_ADC12MEM9+1
\r
442 #define OFS_ADC12MEM10 (0x0074u) /* ADC12 Conversion Memory 10 */
\r
443 #define OFS_ADC12MEM10_L OFS_ADC12MEM10
\r
444 #define OFS_ADC12MEM10_H OFS_ADC12MEM10+1
\r
445 #define OFS_ADC12MEM11 (0x0076u) /* ADC12 Conversion Memory 11 */
\r
446 #define OFS_ADC12MEM11_L OFS_ADC12MEM11
\r
447 #define OFS_ADC12MEM11_H OFS_ADC12MEM11+1
\r
448 #define OFS_ADC12MEM12 (0x0078u) /* ADC12 Conversion Memory 12 */
\r
449 #define OFS_ADC12MEM12_L OFS_ADC12MEM12
\r
450 #define OFS_ADC12MEM12_H OFS_ADC12MEM12+1
\r
451 #define OFS_ADC12MEM13 (0x007Au) /* ADC12 Conversion Memory 13 */
\r
452 #define OFS_ADC12MEM13_L OFS_ADC12MEM13
\r
453 #define OFS_ADC12MEM13_H OFS_ADC12MEM13+1
\r
454 #define OFS_ADC12MEM14 (0x007Cu) /* ADC12 Conversion Memory 14 */
\r
455 #define OFS_ADC12MEM14_L OFS_ADC12MEM14
\r
456 #define OFS_ADC12MEM14_H OFS_ADC12MEM14+1
\r
457 #define OFS_ADC12MEM15 (0x007Eu) /* ADC12 Conversion Memory 15 */
\r
458 #define OFS_ADC12MEM15_L OFS_ADC12MEM15
\r
459 #define OFS_ADC12MEM15_H OFS_ADC12MEM15+1
\r
460 #define OFS_ADC12MEM16 (0x0080u) /* ADC12 Conversion Memory 16 */
\r
461 #define OFS_ADC12MEM16_L OFS_ADC12MEM16
\r
462 #define OFS_ADC12MEM16_H OFS_ADC12MEM16+1
\r
463 #define OFS_ADC12MEM17 (0x0082u) /* ADC12 Conversion Memory 17 */
\r
464 #define OFS_ADC12MEM17_L OFS_ADC12MEM17
\r
465 #define OFS_ADC12MEM17_H OFS_ADC12MEM17+1
\r
466 #define OFS_ADC12MEM18 (0x0084u) /* ADC12 Conversion Memory 18 */
\r
467 #define OFS_ADC12MEM18_L OFS_ADC12MEM18
\r
468 #define OFS_ADC12MEM18_H OFS_ADC12MEM18+1
\r
469 #define OFS_ADC12MEM19 (0x0086u) /* ADC12 Conversion Memory 19 */
\r
470 #define OFS_ADC12MEM19_L OFS_ADC12MEM19
\r
471 #define OFS_ADC12MEM19_H OFS_ADC12MEM19+1
\r
472 #define OFS_ADC12MEM20 (0x0088u) /* ADC12 Conversion Memory 20 */
\r
473 #define OFS_ADC12MEM20_L OFS_ADC12MEM20
\r
474 #define OFS_ADC12MEM20_H OFS_ADC12MEM20+1
\r
475 #define OFS_ADC12MEM21 (0x008Au) /* ADC12 Conversion Memory 21 */
\r
476 #define OFS_ADC12MEM21_L OFS_ADC12MEM21
\r
477 #define OFS_ADC12MEM21_H OFS_ADC12MEM21+1
\r
478 #define OFS_ADC12MEM22 (0x008Cu) /* ADC12 Conversion Memory 22 */
\r
479 #define OFS_ADC12MEM22_L OFS_ADC12MEM22
\r
480 #define OFS_ADC12MEM22_H OFS_ADC12MEM22+1
\r
481 #define OFS_ADC12MEM23 (0x008Eu) /* ADC12 Conversion Memory 23 */
\r
482 #define OFS_ADC12MEM23_L OFS_ADC12MEM23
\r
483 #define OFS_ADC12MEM23_H OFS_ADC12MEM23+1
\r
484 #define OFS_ADC12MEM24 (0x0090u) /* ADC12 Conversion Memory 24 */
\r
485 #define OFS_ADC12MEM24_L OFS_ADC12MEM24
\r
486 #define OFS_ADC12MEM24_H OFS_ADC12MEM24+1
\r
487 #define OFS_ADC12MEM25 (0x0092u) /* ADC12 Conversion Memory 25 */
\r
488 #define OFS_ADC12MEM25_L OFS_ADC12MEM25
\r
489 #define OFS_ADC12MEM25_H OFS_ADC12MEM25+1
\r
490 #define OFS_ADC12MEM26 (0x0094u) /* ADC12 Conversion Memory 26 */
\r
491 #define OFS_ADC12MEM26_L OFS_ADC12MEM26
\r
492 #define OFS_ADC12MEM26_H OFS_ADC12MEM26+1
\r
493 #define OFS_ADC12MEM27 (0x0096u) /* ADC12 Conversion Memory 27 */
\r
494 #define OFS_ADC12MEM27_L OFS_ADC12MEM27
\r
495 #define OFS_ADC12MEM27_H OFS_ADC12MEM27+1
\r
496 #define OFS_ADC12MEM28 (0x0098u) /* ADC12 Conversion Memory 28 */
\r
497 #define OFS_ADC12MEM28_L OFS_ADC12MEM28
\r
498 #define OFS_ADC12MEM28_H OFS_ADC12MEM28+1
\r
499 #define OFS_ADC12MEM29 (0x009Au) /* ADC12 Conversion Memory 29 */
\r
500 #define OFS_ADC12MEM29_L OFS_ADC12MEM29
\r
501 #define OFS_ADC12MEM29_H OFS_ADC12MEM29+1
\r
502 #define OFS_ADC12MEM30 (0x009Cu) /* ADC12 Conversion Memory 30 */
\r
503 #define OFS_ADC12MEM30_L OFS_ADC12MEM30
\r
504 #define OFS_ADC12MEM30_H OFS_ADC12MEM30+1
\r
505 #define OFS_ADC12MEM31 (0x009Eu) /* ADC12 Conversion Memory 31 */
\r
506 #define OFS_ADC12MEM31_L OFS_ADC12MEM31
\r
507 #define OFS_ADC12MEM31_H OFS_ADC12MEM31+1
\r
508 #define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
\r
509 #ifndef __IAR_SYSTEMS_ICC__
\r
510 #define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
\r
512 #define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
\r
515 /* ADC12CTL0 Control Bits */
\r
516 #define ADC12SC (0x0001u) /* ADC12 Start Conversion */
\r
517 #define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */
\r
518 #define ADC12ON (0x0010u) /* ADC12 On/enable */
\r
519 #define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */
\r
520 #define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
\r
521 #define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */
\r
522 #define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */
\r
523 #define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */
\r
524 #define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
\r
525 #define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
\r
526 #define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
\r
527 #define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
\r
529 /* ADC12CTL0 Control Bits */
\r
530 #define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */
\r
531 #define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */
\r
532 #define ADC12ON_L (0x0010u) /* ADC12 On/enable */
\r
533 #define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */
\r
535 /* ADC12CTL0 Control Bits */
\r
536 #define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */
\r
537 #define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */
\r
538 #define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */
\r
539 #define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */
\r
540 #define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */
\r
541 #define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */
\r
542 #define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */
\r
543 #define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */
\r
545 #define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
\r
546 #define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
\r
547 #define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
\r
548 #define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
\r
549 #define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
\r
550 #define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
\r
551 #define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
\r
552 #define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
\r
553 #define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
\r
554 #define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
\r
555 #define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
\r
556 #define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
\r
557 #define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
\r
558 #define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
\r
559 #define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
\r
560 #define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
\r
562 #define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
\r
563 #define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
\r
564 #define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
\r
565 #define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
\r
566 #define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
\r
567 #define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
\r
568 #define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
\r
569 #define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
\r
570 #define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
\r
571 #define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
\r
572 #define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
\r
573 #define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
\r
574 #define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
\r
575 #define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
\r
576 #define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
\r
577 #define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
\r
579 /* ADC12CTL1 Control Bits */
\r
580 #define ADC12BUSY (0x0001u) /* ADC12 Busy */
\r
581 #define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */
\r
582 #define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */
\r
583 #define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */
\r
584 #define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */
\r
585 #define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */
\r
586 #define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */
\r
587 #define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */
\r
588 #define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */
\r
589 #define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */
\r
590 #define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */
\r
591 #define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */
\r
592 #define ADC12SHS2 (0x1000u) /* ADC12 Sample/Hold Source Bit: 2 */
\r
593 #define ADC12PDIV0 (0x2000u) /* ADC12 Predivider Bit: 0 */
\r
594 #define ADC12PDIV1 (0x4000u) /* ADC12 Predivider Bit: 1 */
\r
596 /* ADC12CTL1 Control Bits */
\r
597 #define ADC12BUSY_L (0x0001u) /* ADC12 Busy */
\r
598 #define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */
\r
599 #define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */
\r
600 #define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */
\r
601 #define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */
\r
602 #define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */
\r
603 #define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */
\r
604 #define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */
\r
606 /* ADC12CTL1 Control Bits */
\r
607 #define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */
\r
608 #define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */
\r
609 #define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */
\r
610 #define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */
\r
611 #define ADC12SHS2_H (0x0010u) /* ADC12 Sample/Hold Source Bit: 2 */
\r
612 #define ADC12PDIV0_H (0x0020u) /* ADC12 Predivider Bit: 0 */
\r
613 #define ADC12PDIV1_H (0x0040u) /* ADC12 Predivider Bit: 1 */
\r
615 #define ADC12CONSEQ_0 (0*0x0002u) /* ADC12 Conversion Sequence Select: 0 */
\r
616 #define ADC12CONSEQ_1 (1*0x0002u) /* ADC12 Conversion Sequence Select: 1 */
\r
617 #define ADC12CONSEQ_2 (2*0x0002u) /* ADC12 Conversion Sequence Select: 2 */
\r
618 #define ADC12CONSEQ_3 (3*0x0002u) /* ADC12 Conversion Sequence Select: 3 */
\r
620 #define ADC12SSEL_0 (0*0x0008u) /* ADC12 Clock Source Select: 0 */
\r
621 #define ADC12SSEL_1 (1*0x0008u) /* ADC12 Clock Source Select: 1 */
\r
622 #define ADC12SSEL_2 (2*0x0008u) /* ADC12 Clock Source Select: 2 */
\r
623 #define ADC12SSEL_3 (3*0x0008u) /* ADC12 Clock Source Select: 3 */
\r
625 #define ADC12DIV_0 (0*0x0020u) /* ADC12 Clock Divider Select: 0 */
\r
626 #define ADC12DIV_1 (1*0x0020u) /* ADC12 Clock Divider Select: 1 */
\r
627 #define ADC12DIV_2 (2*0x0020u) /* ADC12 Clock Divider Select: 2 */
\r
628 #define ADC12DIV_3 (3*0x0020u) /* ADC12 Clock Divider Select: 3 */
\r
629 #define ADC12DIV_4 (4*0x0020u) /* ADC12 Clock Divider Select: 4 */
\r
630 #define ADC12DIV_5 (5*0x0020u) /* ADC12 Clock Divider Select: 5 */
\r
631 #define ADC12DIV_6 (6*0x0020u) /* ADC12 Clock Divider Select: 6 */
\r
632 #define ADC12DIV_7 (7*0x0020u) /* ADC12 Clock Divider Select: 7 */
\r
634 #define ADC12SHS_0 (0*0x0400u) /* ADC12 Sample/Hold Source: 0 */
\r
635 #define ADC12SHS_1 (1*0x0400u) /* ADC12 Sample/Hold Source: 1 */
\r
636 #define ADC12SHS_2 (2*0x0400u) /* ADC12 Sample/Hold Source: 2 */
\r
637 #define ADC12SHS_3 (3*0x0400u) /* ADC12 Sample/Hold Source: 3 */
\r
638 #define ADC12SHS_4 (4*0x0400u) /* ADC12 Sample/Hold Source: 4 */
\r
639 #define ADC12SHS_5 (5*0x0400u) /* ADC12 Sample/Hold Source: 5 */
\r
640 #define ADC12SHS_6 (6*0x0400u) /* ADC12 Sample/Hold Source: 6 */
\r
641 #define ADC12SHS_7 (7*0x0400u) /* ADC12 Sample/Hold Source: 7 */
\r
643 #define ADC12PDIV_0 (0*0x2000u) /* ADC12 Clock predivider Select 0 */
\r
644 #define ADC12PDIV_1 (1*0x2000u) /* ADC12 Clock predivider Select 1 */
\r
645 #define ADC12PDIV_2 (2*0x2000u) /* ADC12 Clock predivider Select 2 */
\r
646 #define ADC12PDIV_3 (3*0x2000u) /* ADC12 Clock predivider Select 3 */
\r
647 #define ADC12PDIV__1 (0*0x2000u) /* ADC12 Clock predivider Select: /1 */
\r
648 #define ADC12PDIV__4 (1*0x2000u) /* ADC12 Clock predivider Select: /4 */
\r
649 #define ADC12PDIV__32 (2*0x2000u) /* ADC12 Clock predivider Select: /32 */
\r
650 #define ADC12PDIV__64 (3*0x2000u) /* ADC12 Clock predivider Select: /64 */
\r
652 /* ADC12CTL2 Control Bits */
\r
653 #define ADC12PWRMD (0x0001u) /* ADC12 Power Mode */
\r
654 #define ADC12DF (0x0008u) /* ADC12 Data Format */
\r
655 #define ADC12RES0 (0x0010u) /* ADC12 Resolution Bit: 0 */
\r
656 #define ADC12RES1 (0x0020u) /* ADC12 Resolution Bit: 1 */
\r
658 /* ADC12CTL2 Control Bits */
\r
659 #define ADC12PWRMD_L (0x0001u) /* ADC12 Power Mode */
\r
660 #define ADC12DF_L (0x0008u) /* ADC12 Data Format */
\r
661 #define ADC12RES0_L (0x0010u) /* ADC12 Resolution Bit: 0 */
\r
662 #define ADC12RES1_L (0x0020u) /* ADC12 Resolution Bit: 1 */
\r
664 #define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */
\r
665 #define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */
\r
666 #define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */
\r
667 #define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */
\r
669 #define ADC12RES__8BIT (0x0000u) /* ADC12+ Resolution : 8 Bit */
\r
670 #define ADC12RES__10BIT (0x0010u) /* ADC12+ Resolution : 10 Bit */
\r
671 #define ADC12RES__12BIT (0x0020u) /* ADC12+ Resolution : 12 Bit */
\r
673 /* ADC12CTL3 Control Bits */
\r
674 #define ADC12CSTARTADD0 (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */
\r
675 #define ADC12CSTARTADD1 (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */
\r
676 #define ADC12CSTARTADD2 (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */
\r
677 #define ADC12CSTARTADD3 (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */
\r
678 #define ADC12CSTARTADD4 (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */
\r
679 #define ADC12BATMAP (0x0040u) /* ADC12 Internal AVCC/2 select */
\r
680 #define ADC12TCMAP (0x0080u) /* ADC12 Internal TempSensor select */
\r
681 #define ADC12ICH0MAP (0x0100u) /* ADC12 Internal Channel 0 select */
\r
682 #define ADC12ICH1MAP (0x0200u) /* ADC12 Internal Channel 1 select */
\r
683 #define ADC12ICH2MAP (0x0400u) /* ADC12 Internal Channel 2 select */
\r
684 #define ADC12ICH3MAP (0x0800u) /* ADC12 Internal Channel 3 select */
\r
686 /* ADC12CTL3 Control Bits */
\r
687 #define ADC12CSTARTADD0_L (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */
\r
688 #define ADC12CSTARTADD1_L (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */
\r
689 #define ADC12CSTARTADD2_L (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */
\r
690 #define ADC12CSTARTADD3_L (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */
\r
691 #define ADC12CSTARTADD4_L (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */
\r
692 #define ADC12BATMAP_L (0x0040u) /* ADC12 Internal AVCC/2 select */
\r
693 #define ADC12TCMAP_L (0x0080u) /* ADC12 Internal TempSensor select */
\r
695 /* ADC12CTL3 Control Bits */
\r
696 #define ADC12ICH0MAP_H (0x0001u) /* ADC12 Internal Channel 0 select */
\r
697 #define ADC12ICH1MAP_H (0x0002u) /* ADC12 Internal Channel 1 select */
\r
698 #define ADC12ICH2MAP_H (0x0004u) /* ADC12 Internal Channel 2 select */
\r
699 #define ADC12ICH3MAP_H (0x0008u) /* ADC12 Internal Channel 3 select */
\r
701 #define ADC12CSTARTADD_0 ( 0*0x0001u) /* ADC12 Conversion Start Address: 0 */
\r
702 #define ADC12CSTARTADD_1 ( 1*0x0001u) /* ADC12 Conversion Start Address: 1 */
\r
703 #define ADC12CSTARTADD_2 ( 2*0x0001u) /* ADC12 Conversion Start Address: 2 */
\r
704 #define ADC12CSTARTADD_3 ( 3*0x0001u) /* ADC12 Conversion Start Address: 3 */
\r
705 #define ADC12CSTARTADD_4 ( 4*0x0001u) /* ADC12 Conversion Start Address: 4 */
\r
706 #define ADC12CSTARTADD_5 ( 5*0x0001u) /* ADC12 Conversion Start Address: 5 */
\r
707 #define ADC12CSTARTADD_6 ( 6*0x0001u) /* ADC12 Conversion Start Address: 6 */
\r
708 #define ADC12CSTARTADD_7 ( 7*0x0001u) /* ADC12 Conversion Start Address: 7 */
\r
709 #define ADC12CSTARTADD_8 ( 8*0x0001u) /* ADC12 Conversion Start Address: 8 */
\r
710 #define ADC12CSTARTADD_9 ( 9*0x0001u) /* ADC12 Conversion Start Address: 9 */
\r
711 #define ADC12CSTARTADD_10 (10*0x0001u) /* ADC12 Conversion Start Address: 10 */
\r
712 #define ADC12CSTARTADD_11 (11*0x0001u) /* ADC12 Conversion Start Address: 11 */
\r
713 #define ADC12CSTARTADD_12 (12*0x0001u) /* ADC12 Conversion Start Address: 12 */
\r
714 #define ADC12CSTARTADD_13 (13*0x0001u) /* ADC12 Conversion Start Address: 13 */
\r
715 #define ADC12CSTARTADD_14 (14*0x0001u) /* ADC12 Conversion Start Address: 14 */
\r
716 #define ADC12CSTARTADD_15 (15*0x0001u) /* ADC12 Conversion Start Address: 15 */
\r
717 #define ADC12CSTARTADD_16 (16*0x0001u) /* ADC12 Conversion Start Address: 16 */
\r
718 #define ADC12CSTARTADD_17 (17*0x0001u) /* ADC12 Conversion Start Address: 17 */
\r
719 #define ADC12CSTARTADD_18 (18*0x0001u) /* ADC12 Conversion Start Address: 18 */
\r
720 #define ADC12CSTARTADD_19 (19*0x0001u) /* ADC12 Conversion Start Address: 19 */
\r
721 #define ADC12CSTARTADD_20 (20*0x0001u) /* ADC12 Conversion Start Address: 20 */
\r
722 #define ADC12CSTARTADD_21 (21*0x0001u) /* ADC12 Conversion Start Address: 21 */
\r
723 #define ADC12CSTARTADD_22 (22*0x0001u) /* ADC12 Conversion Start Address: 22 */
\r
724 #define ADC12CSTARTADD_23 (23*0x0001u) /* ADC12 Conversion Start Address: 23 */
\r
725 #define ADC12CSTARTADD_24 (24*0x0001u) /* ADC12 Conversion Start Address: 24 */
\r
726 #define ADC12CSTARTADD_25 (25*0x0001u) /* ADC12 Conversion Start Address: 25 */
\r
727 #define ADC12CSTARTADD_26 (26*0x0001u) /* ADC12 Conversion Start Address: 26 */
\r
728 #define ADC12CSTARTADD_27 (27*0x0001u) /* ADC12 Conversion Start Address: 27 */
\r
729 #define ADC12CSTARTADD_28 (28*0x0001u) /* ADC12 Conversion Start Address: 28 */
\r
730 #define ADC12CSTARTADD_29 (29*0x0001u) /* ADC12 Conversion Start Address: 29 */
\r
731 #define ADC12CSTARTADD_30 (30*0x0001u) /* ADC12 Conversion Start Address: 30 */
\r
732 #define ADC12CSTARTADD_31 (31*0x0001u) /* ADC12 Conversion Start Address: 31 */
\r
734 /* ADC12MCTLx Control Bits */
\r
735 #define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */
\r
736 #define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */
\r
737 #define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */
\r
738 #define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */
\r
739 #define ADC12INCH4 (0x0010u) /* ADC12 Input Channel Select Bit 4 */
\r
740 #define ADC12EOS (0x0080u) /* ADC12 End of Sequence */
\r
741 #define ADC12VRSEL0 (0x0100u) /* ADC12 VR Select Bit 0 */
\r
742 #define ADC12VRSEL1 (0x0200u) /* ADC12 VR Select Bit 1 */
\r
743 #define ADC12VRSEL2 (0x0400u) /* ADC12 VR Select Bit 2 */
\r
744 #define ADC12VRSEL3 (0x0800u) /* ADC12 VR Select Bit 3 */
\r
745 #define ADC12DIF (0x2000u) /* ADC12 Differential mode (only for even Registers) */
\r
746 #define ADC12WINC (0x4000u) /* ADC12 Comparator window enable */
\r
748 /* ADC12MCTLx Control Bits */
\r
749 #define ADC12INCH0_L (0x0001u) /* ADC12 Input Channel Select Bit 0 */
\r
750 #define ADC12INCH1_L (0x0002u) /* ADC12 Input Channel Select Bit 1 */
\r
751 #define ADC12INCH2_L (0x0004u) /* ADC12 Input Channel Select Bit 2 */
\r
752 #define ADC12INCH3_L (0x0008u) /* ADC12 Input Channel Select Bit 3 */
\r
753 #define ADC12INCH4_L (0x0010u) /* ADC12 Input Channel Select Bit 4 */
\r
754 #define ADC12EOS_L (0x0080u) /* ADC12 End of Sequence */
\r
756 /* ADC12MCTLx Control Bits */
\r
757 #define ADC12VRSEL0_H (0x0001u) /* ADC12 VR Select Bit 0 */
\r
758 #define ADC12VRSEL1_H (0x0002u) /* ADC12 VR Select Bit 1 */
\r
759 #define ADC12VRSEL2_H (0x0004u) /* ADC12 VR Select Bit 2 */
\r
760 #define ADC12VRSEL3_H (0x0008u) /* ADC12 VR Select Bit 3 */
\r
761 #define ADC12DIF_H (0x0020u) /* ADC12 Differential mode (only for even Registers) */
\r
762 #define ADC12WINC_H (0x0040u) /* ADC12 Comparator window enable */
\r
764 #define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */
\r
765 #define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */
\r
766 #define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */
\r
767 #define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */
\r
768 #define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */
\r
769 #define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */
\r
770 #define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */
\r
771 #define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */
\r
772 #define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */
\r
773 #define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */
\r
774 #define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */
\r
775 #define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */
\r
776 #define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */
\r
777 #define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */
\r
778 #define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */
\r
779 #define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */
\r
780 #define ADC12INCH_16 (0x0010u) /* ADC12 Input Channel 16 */
\r
781 #define ADC12INCH_17 (0x0011u) /* ADC12 Input Channel 17 */
\r
782 #define ADC12INCH_18 (0x0012u) /* ADC12 Input Channel 18 */
\r
783 #define ADC12INCH_19 (0x0013u) /* ADC12 Input Channel 19 */
\r
784 #define ADC12INCH_20 (0x0014u) /* ADC12 Input Channel 20 */
\r
785 #define ADC12INCH_21 (0x0015u) /* ADC12 Input Channel 21 */
\r
786 #define ADC12INCH_22 (0x0016u) /* ADC12 Input Channel 22 */
\r
787 #define ADC12INCH_23 (0x0017u) /* ADC12 Input Channel 23 */
\r
788 #define ADC12INCH_24 (0x0018u) /* ADC12 Input Channel 24 */
\r
789 #define ADC12INCH_25 (0x0019u) /* ADC12 Input Channel 25 */
\r
790 #define ADC12INCH_26 (0x001Au) /* ADC12 Input Channel 26 */
\r
791 #define ADC12INCH_27 (0x001Bu) /* ADC12 Input Channel 27 */
\r
792 #define ADC12INCH_28 (0x001Cu) /* ADC12 Input Channel 28 */
\r
793 #define ADC12INCH_29 (0x001Du) /* ADC12 Input Channel 29 */
\r
794 #define ADC12INCH_30 (0x001Eu) /* ADC12 Input Channel 30 */
\r
795 #define ADC12INCH_31 (0x001Fu) /* ADC12 Input Channel 31 */
\r
797 #define ADC12VRSEL_0 (0*0x100u) /* ADC12 Select Reference 0 */
\r
798 #define ADC12VRSEL_1 (1*0x100u) /* ADC12 Select Reference 1 */
\r
799 #define ADC12VRSEL_2 (2*0x100u) /* ADC12 Select Reference 2 */
\r
800 #define ADC12VRSEL_3 (3*0x100u) /* ADC12 Select Reference 3 */
\r
801 #define ADC12VRSEL_4 (4*0x100u) /* ADC12 Select Reference 4 */
\r
802 #define ADC12VRSEL_5 (5*0x100u) /* ADC12 Select Reference 5 */
\r
803 #define ADC12VRSEL_6 (6*0x100u) /* ADC12 Select Reference 6 */
\r
804 #define ADC12VRSEL_7 (7*0x100u) /* ADC12 Select Reference 7 */
\r
805 #define ADC12VRSEL_8 (8*0x100u) /* ADC12 Select Reference 8 */
\r
806 #define ADC12VRSEL_9 (9*0x100u) /* ADC12 Select Reference 9 */
\r
807 #define ADC12VRSEL_10 (10*0x100u) /* ADC12 Select Reference 10 */
\r
808 #define ADC12VRSEL_11 (11*0x100u) /* ADC12 Select Reference 11 */
\r
809 #define ADC12VRSEL_12 (12*0x100u) /* ADC12 Select Reference 12 */
\r
810 #define ADC12VRSEL_13 (13*0x100u) /* ADC12 Select Reference 13 */
\r
811 #define ADC12VRSEL_14 (14*0x100u) /* ADC12 Select Reference 14 */
\r
812 #define ADC12VRSEL_15 (15*0x100u) /* ADC12 Select Reference 15 */
\r
814 /* ADC12HI Control Bits */
\r
816 /* ADC12LO Control Bits */
\r
818 /* ADC12IER0 Control Bits */
\r
819 #define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */
\r
820 #define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */
\r
821 #define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */
\r
822 #define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */
\r
823 #define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */
\r
824 #define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */
\r
825 #define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */
\r
826 #define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */
\r
827 #define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */
\r
828 #define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */
\r
829 #define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */
\r
830 #define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */
\r
831 #define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */
\r
832 #define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */
\r
833 #define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */
\r
834 #define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */
\r
836 /* ADC12IER0 Control Bits */
\r
837 #define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */
\r
838 #define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */
\r
839 #define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */
\r
840 #define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */
\r
841 #define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */
\r
842 #define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */
\r
843 #define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */
\r
844 #define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */
\r
846 /* ADC12IER0 Control Bits */
\r
847 #define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */
\r
848 #define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */
\r
849 #define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */
\r
850 #define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */
\r
851 #define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */
\r
852 #define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */
\r
853 #define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */
\r
854 #define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */
\r
856 /* ADC12IER1 Control Bits */
\r
857 #define ADC12IE16 (0x0001u) /* ADC12 Memory 16 Interrupt Enable */
\r
858 #define ADC12IE17 (0x0002u) /* ADC12 Memory 17 Interrupt Enable */
\r
859 #define ADC12IE18 (0x0004u) /* ADC12 Memory 18 Interrupt Enable */
\r
860 #define ADC12IE19 (0x0008u) /* ADC12 Memory 19 Interrupt Enable */
\r
861 #define ADC12IE20 (0x0010u) /* ADC12 Memory 20 Interrupt Enable */
\r
862 #define ADC12IE21 (0x0020u) /* ADC12 Memory 21 Interrupt Enable */
\r
863 #define ADC12IE22 (0x0040u) /* ADC12 Memory 22 Interrupt Enable */
\r
864 #define ADC12IE23 (0x0080u) /* ADC12 Memory 23 Interrupt Enable */
\r
865 #define ADC12IE24 (0x0100u) /* ADC12 Memory 24 Interrupt Enable */
\r
866 #define ADC12IE25 (0x0200u) /* ADC12 Memory 25 Interrupt Enable */
\r
867 #define ADC12IE26 (0x0400u) /* ADC12 Memory 26 Interrupt Enable */
\r
868 #define ADC12IE27 (0x0800u) /* ADC12 Memory 27 Interrupt Enable */
\r
869 #define ADC12IE28 (0x1000u) /* ADC12 Memory 28 Interrupt Enable */
\r
870 #define ADC12IE29 (0x2000u) /* ADC12 Memory 29 Interrupt Enable */
\r
871 #define ADC12IE30 (0x4000u) /* ADC12 Memory 30 Interrupt Enable */
\r
872 #define ADC12IE31 (0x8000u) /* ADC12 Memory 31 Interrupt Enable */
\r
874 /* ADC12IER1 Control Bits */
\r
875 #define ADC12IE16_L (0x0001u) /* ADC12 Memory 16 Interrupt Enable */
\r
876 #define ADC12IE17_L (0x0002u) /* ADC12 Memory 17 Interrupt Enable */
\r
877 #define ADC12IE18_L (0x0004u) /* ADC12 Memory 18 Interrupt Enable */
\r
878 #define ADC12IE19_L (0x0008u) /* ADC12 Memory 19 Interrupt Enable */
\r
879 #define ADC12IE20_L (0x0010u) /* ADC12 Memory 20 Interrupt Enable */
\r
880 #define ADC12IE21_L (0x0020u) /* ADC12 Memory 21 Interrupt Enable */
\r
881 #define ADC12IE22_L (0x0040u) /* ADC12 Memory 22 Interrupt Enable */
\r
882 #define ADC12IE23_L (0x0080u) /* ADC12 Memory 23 Interrupt Enable */
\r
884 /* ADC12IER1 Control Bits */
\r
885 #define ADC12IE24_H (0x0001u) /* ADC12 Memory 24 Interrupt Enable */
\r
886 #define ADC12IE25_H (0x0002u) /* ADC12 Memory 25 Interrupt Enable */
\r
887 #define ADC12IE26_H (0x0004u) /* ADC12 Memory 26 Interrupt Enable */
\r
888 #define ADC12IE27_H (0x0008u) /* ADC12 Memory 27 Interrupt Enable */
\r
889 #define ADC12IE28_H (0x0010u) /* ADC12 Memory 28 Interrupt Enable */
\r
890 #define ADC12IE29_H (0x0020u) /* ADC12 Memory 29 Interrupt Enable */
\r
891 #define ADC12IE30_H (0x0040u) /* ADC12 Memory 30 Interrupt Enable */
\r
892 #define ADC12IE31_H (0x0080u) /* ADC12 Memory 31 Interrupt Enable */
\r
894 /* ADC12IER2 Control Bits */
\r
895 #define ADC12INIE (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
\r
896 #define ADC12LOIE (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
\r
897 #define ADC12HIIE (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
\r
898 #define ADC12OVIE (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */
\r
899 #define ADC12TOVIE (0x0020u) /* ADC12 Timer Overflow interrupt enable */
\r
900 #define ADC12RDYIE (0x0040u) /* ADC12 local buffered reference ready interrupt enable */
\r
902 /* ADC12IER2 Control Bits */
\r
903 #define ADC12INIE_L (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
\r
904 #define ADC12LOIE_L (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
\r
905 #define ADC12HIIE_L (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
\r
906 #define ADC12OVIE_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */
\r
907 #define ADC12TOVIE_L (0x0020u) /* ADC12 Timer Overflow interrupt enable */
\r
908 #define ADC12RDYIE_L (0x0040u) /* ADC12 local buffered reference ready interrupt enable */
\r
910 /* ADC12IFGR0 Control Bits */
\r
911 #define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */
\r
912 #define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */
\r
913 #define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */
\r
914 #define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */
\r
915 #define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */
\r
916 #define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */
\r
917 #define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */
\r
918 #define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */
\r
919 #define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */
\r
920 #define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */
\r
921 #define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */
\r
922 #define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */
\r
923 #define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */
\r
924 #define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */
\r
925 #define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */
\r
926 #define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */
\r
928 /* ADC12IFGR0 Control Bits */
\r
929 #define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */
\r
930 #define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */
\r
931 #define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */
\r
932 #define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */
\r
933 #define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */
\r
934 #define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */
\r
935 #define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */
\r
936 #define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */
\r
938 /* ADC12IFGR0 Control Bits */
\r
939 #define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */
\r
940 #define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */
\r
941 #define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */
\r
942 #define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */
\r
943 #define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */
\r
944 #define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */
\r
945 #define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */
\r
946 #define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */
\r
948 /* ADC12IFGR1 Control Bits */
\r
949 #define ADC12IFG16 (0x0001u) /* ADC12 Memory 16 Interrupt Flag */
\r
950 #define ADC12IFG17 (0x0002u) /* ADC12 Memory 17 Interrupt Flag */
\r
951 #define ADC12IFG18 (0x0004u) /* ADC12 Memory 18 Interrupt Flag */
\r
952 #define ADC12IFG19 (0x0008u) /* ADC12 Memory 19 Interrupt Flag */
\r
953 #define ADC12IFG20 (0x0010u) /* ADC12 Memory 20 Interrupt Flag */
\r
954 #define ADC12IFG21 (0x0020u) /* ADC12 Memory 21 Interrupt Flag */
\r
955 #define ADC12IFG22 (0x0040u) /* ADC12 Memory 22 Interrupt Flag */
\r
956 #define ADC12IFG23 (0x0080u) /* ADC12 Memory 23 Interrupt Flag */
\r
957 #define ADC12IFG24 (0x0100u) /* ADC12 Memory 24 Interrupt Flag */
\r
958 #define ADC12IFG25 (0x0200u) /* ADC12 Memory 25 Interrupt Flag */
\r
959 #define ADC12IFG26 (0x0400u) /* ADC12 Memory 26 Interrupt Flag */
\r
960 #define ADC12IFG27 (0x0800u) /* ADC12 Memory 27 Interrupt Flag */
\r
961 #define ADC12IFG28 (0x1000u) /* ADC12 Memory 28 Interrupt Flag */
\r
962 #define ADC12IFG29 (0x2000u) /* ADC12 Memory 29 Interrupt Flag */
\r
963 #define ADC12IFG30 (0x4000u) /* ADC12 Memory 30 Interrupt Flag */
\r
964 #define ADC12IFG31 (0x8000u) /* ADC12 Memory 31 Interrupt Flag */
\r
966 /* ADC12IFGR1 Control Bits */
\r
967 #define ADC12IFG16_L (0x0001u) /* ADC12 Memory 16 Interrupt Flag */
\r
968 #define ADC12IFG17_L (0x0002u) /* ADC12 Memory 17 Interrupt Flag */
\r
969 #define ADC12IFG18_L (0x0004u) /* ADC12 Memory 18 Interrupt Flag */
\r
970 #define ADC12IFG19_L (0x0008u) /* ADC12 Memory 19 Interrupt Flag */
\r
971 #define ADC12IFG20_L (0x0010u) /* ADC12 Memory 20 Interrupt Flag */
\r
972 #define ADC12IFG21_L (0x0020u) /* ADC12 Memory 21 Interrupt Flag */
\r
973 #define ADC12IFG22_L (0x0040u) /* ADC12 Memory 22 Interrupt Flag */
\r
974 #define ADC12IFG23_L (0x0080u) /* ADC12 Memory 23 Interrupt Flag */
\r
976 /* ADC12IFGR1 Control Bits */
\r
977 #define ADC12IFG24_H (0x0001u) /* ADC12 Memory 24 Interrupt Flag */
\r
978 #define ADC12IFG25_H (0x0002u) /* ADC12 Memory 25 Interrupt Flag */
\r
979 #define ADC12IFG26_H (0x0004u) /* ADC12 Memory 26 Interrupt Flag */
\r
980 #define ADC12IFG27_H (0x0008u) /* ADC12 Memory 27 Interrupt Flag */
\r
981 #define ADC12IFG28_H (0x0010u) /* ADC12 Memory 28 Interrupt Flag */
\r
982 #define ADC12IFG29_H (0x0020u) /* ADC12 Memory 29 Interrupt Flag */
\r
983 #define ADC12IFG30_H (0x0040u) /* ADC12 Memory 30 Interrupt Flag */
\r
984 #define ADC12IFG31_H (0x0080u) /* ADC12 Memory 31 Interrupt Flag */
\r
986 /* ADC12IFGR2 Control Bits */
\r
987 #define ADC12INIFG (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
\r
988 #define ADC12LOIFG (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
\r
989 #define ADC12HIIFG (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
\r
990 #define ADC12OVIFG (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */
\r
991 #define ADC12TOVIFG (0x0020u) /* ADC12 Timer Overflow interrupt Flag */
\r
992 #define ADC12RDYIFG (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */
\r
994 /* ADC12IFGR2 Control Bits */
\r
995 #define ADC12INIFG_L (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
\r
996 #define ADC12LOIFG_L (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
\r
997 #define ADC12HIIFG_L (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
\r
998 #define ADC12OVIFG_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */
\r
999 #define ADC12TOVIFG_L (0x0020u) /* ADC12 Timer Overflow interrupt Flag */
\r
1000 #define ADC12RDYIFG_L (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */
\r
1002 /* ADC12IV Definitions */
\r
1003 #define ADC12IV_NONE (0x0000u) /* No Interrupt pending */
\r
1004 #define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */
\r
1005 #define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */
\r
1006 #define ADC12IV_ADC12HIIFG (0x0006u) /* ADC12HIIFG */
\r
1007 #define ADC12IV_ADC12LOIFG (0x0008u) /* ADC12LOIFG */
\r
1008 #define ADC12IV_ADC12INIFG (0x000Au) /* ADC12INIFG */
\r
1009 #define ADC12IV_ADC12IFG0 (0x000Cu) /* ADC12IFG0 */
\r
1010 #define ADC12IV_ADC12IFG1 (0x000Eu) /* ADC12IFG1 */
\r
1011 #define ADC12IV_ADC12IFG2 (0x0010u) /* ADC12IFG2 */
\r
1012 #define ADC12IV_ADC12IFG3 (0x0012u) /* ADC12IFG3 */
\r
1013 #define ADC12IV_ADC12IFG4 (0x0014u) /* ADC12IFG4 */
\r
1014 #define ADC12IV_ADC12IFG5 (0x0016u) /* ADC12IFG5 */
\r
1015 #define ADC12IV_ADC12IFG6 (0x0018u) /* ADC12IFG6 */
\r
1016 #define ADC12IV_ADC12IFG7 (0x001Au) /* ADC12IFG7 */
\r
1017 #define ADC12IV_ADC12IFG8 (0x001Cu) /* ADC12IFG8 */
\r
1018 #define ADC12IV_ADC12IFG9 (0x001Eu) /* ADC12IFG9 */
\r
1019 #define ADC12IV_ADC12IFG10 (0x0020u) /* ADC12IFG10 */
\r
1020 #define ADC12IV_ADC12IFG11 (0x0022u) /* ADC12IFG11 */
\r
1021 #define ADC12IV_ADC12IFG12 (0x0024u) /* ADC12IFG12 */
\r
1022 #define ADC12IV_ADC12IFG13 (0x0026u) /* ADC12IFG13 */
\r
1023 #define ADC12IV_ADC12IFG14 (0x0028u) /* ADC12IFG14 */
\r
1024 #define ADC12IV_ADC12IFG15 (0x002Au) /* ADC12IFG15 */
\r
1025 #define ADC12IV_ADC12IFG16 (0x002Cu) /* ADC12IFG16 */
\r
1026 #define ADC12IV_ADC12IFG17 (0x002Eu) /* ADC12IFG17 */
\r
1027 #define ADC12IV_ADC12IFG18 (0x0030u) /* ADC12IFG18 */
\r
1028 #define ADC12IV_ADC12IFG19 (0x0032u) /* ADC12IFG19 */
\r
1029 #define ADC12IV_ADC12IFG20 (0x0034u) /* ADC12IFG20 */
\r
1030 #define ADC12IV_ADC12IFG21 (0x0036u) /* ADC12IFG21 */
\r
1031 #define ADC12IV_ADC12IFG22 (0x0038u) /* ADC12IFG22 */
\r
1032 #define ADC12IV_ADC12IFG23 (0x003Au) /* ADC12IFG23 */
\r
1033 #define ADC12IV_ADC12IFG24 (0x003Cu) /* ADC12IFG24 */
\r
1034 #define ADC12IV_ADC12IFG25 (0x003Eu) /* ADC12IFG25 */
\r
1035 #define ADC12IV_ADC12IFG26 (0x0040u) /* ADC12IFG26 */
\r
1036 #define ADC12IV_ADC12IFG27 (0x0042u) /* ADC12IFG27 */
\r
1037 #define ADC12IV_ADC12IFG28 (0x0044u) /* ADC12IFG28 */
\r
1038 #define ADC12IV_ADC12IFG29 (0x0046u) /* ADC12IFG29 */
\r
1039 #define ADC12IV_ADC12IFG30 (0x0048u) /* ADC12IFG30 */
\r
1040 #define ADC12IV_ADC12IFG31 (0x004Au) /* ADC12IFG31 */
\r
1041 #define ADC12IV_ADC12RDYIFG (0x004Cu) /* ADC12RDYIFG */
\r
1045 /************************************************************
\r
1046 * AES256 Accelerator
\r
1047 ************************************************************/
\r
1048 #ifdef __MSP430_HAS_AES256__ /* Definition to show that Module is available */
\r
1050 #define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */
\r
1051 #define OFS_AESACTL0_L OFS_AESACTL0
\r
1052 #define OFS_AESACTL0_H OFS_AESACTL0+1
\r
1053 #define OFS_AESACTL1 (0x0002u) /* AES accelerator control register 1 */
\r
1054 #define OFS_AESACTL1_L OFS_AESACTL1
\r
1055 #define OFS_AESACTL1_H OFS_AESACTL1+1
\r
1056 #define OFS_AESASTAT (0x0004u) /* AES accelerator status register */
\r
1057 #define OFS_AESASTAT_L OFS_AESASTAT
\r
1058 #define OFS_AESASTAT_H OFS_AESASTAT+1
\r
1059 #define OFS_AESAKEY (0x0006u) /* AES accelerator key register */
\r
1060 #define OFS_AESAKEY_L OFS_AESAKEY
\r
1061 #define OFS_AESAKEY_H OFS_AESAKEY+1
\r
1062 #define OFS_AESADIN (0x0008u) /* AES accelerator data in register */
\r
1063 #define OFS_AESADIN_L OFS_AESADIN
\r
1064 #define OFS_AESADIN_H OFS_AESADIN+1
\r
1065 #define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */
\r
1066 #define OFS_AESADOUT_L OFS_AESADOUT
\r
1067 #define OFS_AESADOUT_H OFS_AESADOUT+1
\r
1068 #define OFS_AESAXDIN (0x000Cu) /* AES accelerator XORed data in register */
\r
1069 #define OFS_AESAXDIN_L OFS_AESAXDIN
\r
1070 #define OFS_AESAXDIN_H OFS_AESAXDIN+1
\r
1071 #define OFS_AESAXIN (0x000Eu) /* AES accelerator XORed data in register (no trigger) */
\r
1072 #define OFS_AESAXIN_L OFS_AESAXIN
\r
1073 #define OFS_AESAXIN_H OFS_AESAXIN+1
\r
1075 /* AESACTL0 Control Bits */
\r
1076 #define AESOP0 (0x0001u) /* AES Operation Bit: 0 */
\r
1077 #define AESOP1 (0x0002u) /* AES Operation Bit: 1 */
\r
1078 #define AESKL0 (0x0004u) /* AES Key length Bit: 0 */
\r
1079 #define AESKL1 (0x0008u) /* AES Key length Bit: 1 */
\r
1080 #define AESTRIG (0x0010u) /* AES Trigger Select */
\r
1081 #define AESCM0 (0x0020u) /* AES Cipher mode select Bit: 0 */
\r
1082 #define AESCM1 (0x0040u) /* AES Cipher mode select Bit: 1 */
\r
1083 #define AESSWRST (0x0080u) /* AES Software Reset */
\r
1084 #define AESRDYIFG (0x0100u) /* AES ready interrupt flag */
\r
1085 #define AESERRFG (0x0800u) /* AES Error Flag */
\r
1086 #define AESRDYIE (0x1000u) /* AES ready interrupt enable*/
\r
1087 #define AESCMEN (0x8000u) /* AES DMA cipher mode enable*/
\r
1089 /* AESACTL0 Control Bits */
\r
1090 #define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */
\r
1091 #define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */
\r
1092 #define AESKL0_L (0x0004u) /* AES Key length Bit: 0 */
\r
1093 #define AESKL1_L (0x0008u) /* AES Key length Bit: 1 */
\r
1094 #define AESTRIG_L (0x0010u) /* AES Trigger Select */
\r
1095 #define AESCM0_L (0x0020u) /* AES Cipher mode select Bit: 0 */
\r
1096 #define AESCM1_L (0x0040u) /* AES Cipher mode select Bit: 1 */
\r
1097 #define AESSWRST_L (0x0080u) /* AES Software Reset */
\r
1099 /* AESACTL0 Control Bits */
\r
1100 #define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */
\r
1101 #define AESERRFG_H (0x0008u) /* AES Error Flag */
\r
1102 #define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/
\r
1103 #define AESCMEN_H (0x0080u) /* AES DMA cipher mode enable*/
\r
1105 #define AESOP_0 (0x0000u) /* AES Operation: Encrypt */
\r
1106 #define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */
\r
1107 #define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */
\r
1108 #define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */
\r
1110 #define AESKL_0 (0x0000u) /* AES Key length: AES128 */
\r
1111 #define AESKL_1 (0x0004u) /* AES Key length: AES192 */
\r
1112 #define AESKL_2 (0x0008u) /* AES Key length: AES256 */
\r
1113 #define AESKL__128 (0x0000u) /* AES Key length: AES128 */
\r
1114 #define AESKL__192 (0x0004u) /* AES Key length: AES192 */
\r
1115 #define AESKL__256 (0x0008u) /* AES Key length: AES256 */
\r
1117 #define AESCM_0 (0x0000u) /* AES Cipher mode select: ECB */
\r
1118 #define AESCM_1 (0x0020u) /* AES Cipher mode select: CBC */
\r
1119 #define AESCM_2 (0x0040u) /* AES Cipher mode select: OFB */
\r
1120 #define AESCM_3 (0x0060u) /* AES Cipher mode select: CFB */
\r
1121 #define AESCM__ECB (0x0000u) /* AES Cipher mode select: ECB */
\r
1122 #define AESCM__CBC (0x0020u) /* AES Cipher mode select: CBC */
\r
1123 #define AESCM__OFB (0x0040u) /* AES Cipher mode select: OFB */
\r
1124 #define AESCM__CFB (0x0060u) /* AES Cipher mode select: CFB */
\r
1126 /* AESACTL1 Control Bits */
\r
1127 #define AESBLKCNT0 (0x0001u) /* AES Cipher Block Counter Bit: 0 */
\r
1128 #define AESBLKCNT1 (0x0002u) /* AES Cipher Block Counter Bit: 1 */
\r
1129 #define AESBLKCNT2 (0x0004u) /* AES Cipher Block Counter Bit: 2 */
\r
1130 #define AESBLKCNT3 (0x0008u) /* AES Cipher Block Counter Bit: 3 */
\r
1131 #define AESBLKCNT4 (0x0010u) /* AES Cipher Block Counter Bit: 4 */
\r
1132 #define AESBLKCNT5 (0x0020u) /* AES Cipher Block Counter Bit: 5 */
\r
1133 #define AESBLKCNT6 (0x0040u) /* AES Cipher Block Counter Bit: 6 */
\r
1134 #define AESBLKCNT7 (0x0080u) /* AES Cipher Block Counter Bit: 7 */
\r
1136 /* AESACTL1 Control Bits */
\r
1137 #define AESBLKCNT0_L (0x0001u) /* AES Cipher Block Counter Bit: 0 */
\r
1138 #define AESBLKCNT1_L (0x0002u) /* AES Cipher Block Counter Bit: 1 */
\r
1139 #define AESBLKCNT2_L (0x0004u) /* AES Cipher Block Counter Bit: 2 */
\r
1140 #define AESBLKCNT3_L (0x0008u) /* AES Cipher Block Counter Bit: 3 */
\r
1141 #define AESBLKCNT4_L (0x0010u) /* AES Cipher Block Counter Bit: 4 */
\r
1142 #define AESBLKCNT5_L (0x0020u) /* AES Cipher Block Counter Bit: 5 */
\r
1143 #define AESBLKCNT6_L (0x0040u) /* AES Cipher Block Counter Bit: 6 */
\r
1144 #define AESBLKCNT7_L (0x0080u) /* AES Cipher Block Counter Bit: 7 */
\r
1146 /* AESASTAT Control Bits */
\r
1147 #define AESBUSY (0x0001u) /* AES Busy */
\r
1148 #define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */
\r
1149 #define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */
\r
1150 #define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */
\r
1151 #define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */
\r
1152 #define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */
\r
1153 #define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */
\r
1154 #define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */
\r
1155 #define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */
\r
1156 #define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */
\r
1157 #define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */
\r
1158 #define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */
\r
1159 #define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */
\r
1160 #define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */
\r
1161 #define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */
\r
1162 #define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */
\r
1164 /* AESASTAT Control Bits */
\r
1165 #define AESBUSY_L (0x0001u) /* AES Busy */
\r
1166 #define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */
\r
1167 #define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */
\r
1168 #define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */
\r
1169 #define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */
\r
1170 #define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */
\r
1171 #define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */
\r
1172 #define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */
\r
1174 /* AESASTAT Control Bits */
\r
1175 #define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */
\r
1176 #define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */
\r
1177 #define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */
\r
1178 #define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */
\r
1179 #define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */
\r
1180 #define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */
\r
1181 #define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */
\r
1182 #define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */
\r
1185 /************************************************************
\r
1186 * Capacitive_Touch_IO 0
\r
1187 ************************************************************/
\r
1188 #ifdef __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */
\r
1190 #define OFS_CAPTIO0CTL (0x000Eu) /* Capacitive_Touch_IO 0 control register */
\r
1191 #define OFS_CAPTIO0CTL_L OFS_CAPTIO0CTL
\r
1192 #define OFS_CAPTIO0CTL_H OFS_CAPTIO0CTL+1
\r
1194 #define CAPSIO0CTL CAPTIO0CTL /* legacy define */
\r
1196 /* CAPTIOxCTL Control Bits */
\r
1197 #define CAPTIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */
\r
1198 #define CAPTIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */
\r
1199 #define CAPTIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */
\r
1200 #define CAPTIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */
\r
1201 #define CAPTIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */
\r
1202 #define CAPTIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */
\r
1203 #define CAPTIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */
\r
1204 #define CAPTIOEN (0x0100u) /* CapTouchIO Enable */
\r
1205 #define CAPTIO (0x0200u) /* CapTouchIO state */
\r
1207 /* CAPTIOxCTL Control Bits */
\r
1208 #define CAPTIOPISEL0_L (0x0002u) /* CapTouchIO Pin Select Bit: 0 */
\r
1209 #define CAPTIOPISEL1_L (0x0004u) /* CapTouchIO Pin Select Bit: 1 */
\r
1210 #define CAPTIOPISEL2_L (0x0008u) /* CapTouchIO Pin Select Bit: 2 */
\r
1211 #define CAPTIOPOSEL0_L (0x0010u) /* CapTouchIO Port Select Bit: 0 */
\r
1212 #define CAPTIOPOSEL1_L (0x0020u) /* CapTouchIO Port Select Bit: 1 */
\r
1213 #define CAPTIOPOSEL2_L (0x0040u) /* CapTouchIO Port Select Bit: 2 */
\r
1214 #define CAPTIOPOSEL3_L (0x0080u) /* CapTouchIO Port Select Bit: 3 */
\r
1216 /* CAPTIOxCTL Control Bits */
\r
1217 #define CAPTIOEN_H (0x0001u) /* CapTouchIO Enable */
\r
1218 #define CAPTIO_H (0x0002u) /* CapTouchIO state */
\r
1220 /* Legacy defines */
\r
1221 #define CAPSIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */
\r
1222 #define CAPSIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */
\r
1223 #define CAPSIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */
\r
1224 #define CAPSIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */
\r
1225 #define CAPSIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */
\r
1226 #define CAPSIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */
\r
1227 #define CAPSIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */
\r
1228 #define CAPSIOEN (0x0100u) /* CapTouchIO Enable */
\r
1229 #define CAPSIO (0x0200u) /* CapTouchIO state */
\r
1232 /************************************************************
\r
1233 * Capacitive_Touch_IO 1
\r
1234 ************************************************************/
\r
1235 #ifdef __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */
\r
1237 #define OFS_CAPTIO1CTL (0x000Eu) /* Capacitive_Touch_IO 1 control register */
\r
1238 #define OFS_CAPTIO1CTL_L OFS_CAPTIO1CTL
\r
1239 #define OFS_CAPTIO1CTL_H OFS_CAPTIO1CTL+1
\r
1241 #define CAPSIO1CTL CAPTIO1CTL /* legacy define */
\r
1244 /************************************************************
\r
1246 ************************************************************/
\r
1247 #ifdef __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */
\r
1249 #define OFS_CECTL0 (0x0000u) /* Comparator E Control Register 0 */
\r
1250 #define OFS_CECTL0_L OFS_CECTL0
\r
1251 #define OFS_CECTL0_H OFS_CECTL0+1
\r
1252 #define OFS_CECTL1 (0x0002u) /* Comparator E Control Register 1 */
\r
1253 #define OFS_CECTL1_L OFS_CECTL1
\r
1254 #define OFS_CECTL1_H OFS_CECTL1+1
\r
1255 #define OFS_CECTL2 (0x0004u) /* Comparator E Control Register 2 */
\r
1256 #define OFS_CECTL2_L OFS_CECTL2
\r
1257 #define OFS_CECTL2_H OFS_CECTL2+1
\r
1258 #define OFS_CECTL3 (0x0006u) /* Comparator E Control Register 3 */
\r
1259 #define OFS_CECTL3_L OFS_CECTL3
\r
1260 #define OFS_CECTL3_H OFS_CECTL3+1
\r
1261 #define OFS_CEINT (0x000Cu) /* Comparator E Interrupt Register */
\r
1262 #define OFS_CEINT_L OFS_CEINT
\r
1263 #define OFS_CEINT_H OFS_CEINT+1
\r
1264 #define OFS_CEIV (0x000Eu) /* Comparator E Interrupt Vector Word */
\r
1265 #define OFS_CEIV_L OFS_CEIV
\r
1266 #define OFS_CEIV_H OFS_CEIV+1
\r
1268 /* CECTL0 Control Bits */
\r
1269 #define CEIPSEL0 (0x0001u) /* Comp. E Pos. Channel Input Select 0 */
\r
1270 #define CEIPSEL1 (0x0002u) /* Comp. E Pos. Channel Input Select 1 */
\r
1271 #define CEIPSEL2 (0x0004u) /* Comp. E Pos. Channel Input Select 2 */
\r
1272 #define CEIPSEL3 (0x0008u) /* Comp. E Pos. Channel Input Select 3 */
\r
1273 //#define RESERVED (0x0010u) /* Comp. E */
\r
1274 //#define RESERVED (0x0020u) /* Comp. E */
\r
1275 //#define RESERVED (0x0040u) /* Comp. E */
\r
1276 #define CEIPEN (0x0080u) /* Comp. E Pos. Channel Input Enable */
\r
1277 #define CEIMSEL0 (0x0100u) /* Comp. E Neg. Channel Input Select 0 */
\r
1278 #define CEIMSEL1 (0x0200u) /* Comp. E Neg. Channel Input Select 1 */
\r
1279 #define CEIMSEL2 (0x0400u) /* Comp. E Neg. Channel Input Select 2 */
\r
1280 #define CEIMSEL3 (0x0800u) /* Comp. E Neg. Channel Input Select 3 */
\r
1281 //#define RESERVED (0x1000u) /* Comp. E */
\r
1282 //#define RESERVED (0x2000u) /* Comp. E */
\r
1283 //#define RESERVED (0x4000u) /* Comp. E */
\r
1284 #define CEIMEN (0x8000u) /* Comp. E Neg. Channel Input Enable */
\r
1286 /* CECTL0 Control Bits */
\r
1287 #define CEIPSEL0_L (0x0001u) /* Comp. E Pos. Channel Input Select 0 */
\r
1288 #define CEIPSEL1_L (0x0002u) /* Comp. E Pos. Channel Input Select 1 */
\r
1289 #define CEIPSEL2_L (0x0004u) /* Comp. E Pos. Channel Input Select 2 */
\r
1290 #define CEIPSEL3_L (0x0008u) /* Comp. E Pos. Channel Input Select 3 */
\r
1291 //#define RESERVED (0x0010u) /* Comp. E */
\r
1292 //#define RESERVED (0x0020u) /* Comp. E */
\r
1293 //#define RESERVED (0x0040u) /* Comp. E */
\r
1294 #define CEIPEN_L (0x0080u) /* Comp. E Pos. Channel Input Enable */
\r
1295 //#define RESERVED (0x1000u) /* Comp. E */
\r
1296 //#define RESERVED (0x2000u) /* Comp. E */
\r
1297 //#define RESERVED (0x4000u) /* Comp. E */
\r
1299 /* CECTL0 Control Bits */
\r
1300 //#define RESERVED (0x0010u) /* Comp. E */
\r
1301 //#define RESERVED (0x0020u) /* Comp. E */
\r
1302 //#define RESERVED (0x0040u) /* Comp. E */
\r
1303 #define CEIMSEL0_H (0x0001u) /* Comp. E Neg. Channel Input Select 0 */
\r
1304 #define CEIMSEL1_H (0x0002u) /* Comp. E Neg. Channel Input Select 1 */
\r
1305 #define CEIMSEL2_H (0x0004u) /* Comp. E Neg. Channel Input Select 2 */
\r
1306 #define CEIMSEL3_H (0x0008u) /* Comp. E Neg. Channel Input Select 3 */
\r
1307 //#define RESERVED (0x1000u) /* Comp. E */
\r
1308 //#define RESERVED (0x2000u) /* Comp. E */
\r
1309 //#define RESERVED (0x4000u) /* Comp. E */
\r
1310 #define CEIMEN_H (0x0080u) /* Comp. E Neg. Channel Input Enable */
\r
1312 #define CEIPSEL_0 (0x0000u) /* Comp. E V+ terminal Input Select: Channel 0 */
\r
1313 #define CEIPSEL_1 (0x0001u) /* Comp. E V+ terminal Input Select: Channel 1 */
\r
1314 #define CEIPSEL_2 (0x0002u) /* Comp. E V+ terminal Input Select: Channel 2 */
\r
1315 #define CEIPSEL_3 (0x0003u) /* Comp. E V+ terminal Input Select: Channel 3 */
\r
1316 #define CEIPSEL_4 (0x0004u) /* Comp. E V+ terminal Input Select: Channel 4 */
\r
1317 #define CEIPSEL_5 (0x0005u) /* Comp. E V+ terminal Input Select: Channel 5 */
\r
1318 #define CEIPSEL_6 (0x0006u) /* Comp. E V+ terminal Input Select: Channel 6 */
\r
1319 #define CEIPSEL_7 (0x0007u) /* Comp. E V+ terminal Input Select: Channel 7 */
\r
1320 #define CEIPSEL_8 (0x0008u) /* Comp. E V+ terminal Input Select: Channel 8 */
\r
1321 #define CEIPSEL_9 (0x0009u) /* Comp. E V+ terminal Input Select: Channel 9 */
\r
1322 #define CEIPSEL_10 (0x000Au) /* Comp. E V+ terminal Input Select: Channel 10 */
\r
1323 #define CEIPSEL_11 (0x000Bu) /* Comp. E V+ terminal Input Select: Channel 11 */
\r
1324 #define CEIPSEL_12 (0x000Cu) /* Comp. E V+ terminal Input Select: Channel 12 */
\r
1325 #define CEIPSEL_13 (0x000Du) /* Comp. E V+ terminal Input Select: Channel 13 */
\r
1326 #define CEIPSEL_14 (0x000Eu) /* Comp. E V+ terminal Input Select: Channel 14 */
\r
1327 #define CEIPSEL_15 (0x000Fu) /* Comp. E V+ terminal Input Select: Channel 15 */
\r
1329 #define CEIMSEL_0 (0x0000u) /* Comp. E V- Terminal Input Select: Channel 0 */
\r
1330 #define CEIMSEL_1 (0x0100u) /* Comp. E V- Terminal Input Select: Channel 1 */
\r
1331 #define CEIMSEL_2 (0x0200u) /* Comp. E V- Terminal Input Select: Channel 2 */
\r
1332 #define CEIMSEL_3 (0x0300u) /* Comp. E V- Terminal Input Select: Channel 3 */
\r
1333 #define CEIMSEL_4 (0x0400u) /* Comp. E V- Terminal Input Select: Channel 4 */
\r
1334 #define CEIMSEL_5 (0x0500u) /* Comp. E V- Terminal Input Select: Channel 5 */
\r
1335 #define CEIMSEL_6 (0x0600u) /* Comp. E V- Terminal Input Select: Channel 6 */
\r
1336 #define CEIMSEL_7 (0x0700u) /* Comp. E V- Terminal Input Select: Channel 7 */
\r
1337 #define CEIMSEL_8 (0x0800u) /* Comp. E V- terminal Input Select: Channel 8 */
\r
1338 #define CEIMSEL_9 (0x0900u) /* Comp. E V- terminal Input Select: Channel 9 */
\r
1339 #define CEIMSEL_10 (0x0A00u) /* Comp. E V- terminal Input Select: Channel 10 */
\r
1340 #define CEIMSEL_11 (0x0B00u) /* Comp. E V- terminal Input Select: Channel 11 */
\r
1341 #define CEIMSEL_12 (0x0C00u) /* Comp. E V- terminal Input Select: Channel 12 */
\r
1342 #define CEIMSEL_13 (0x0D00u) /* Comp. E V- terminal Input Select: Channel 13 */
\r
1343 #define CEIMSEL_14 (0x0E00u) /* Comp. E V- terminal Input Select: Channel 14 */
\r
1344 #define CEIMSEL_15 (0x0F00u) /* Comp. E V- terminal Input Select: Channel 15 */
\r
1346 /* CECTL1 Control Bits */
\r
1347 #define CEOUT (0x0001u) /* Comp. E Output */
\r
1348 #define CEOUTPOL (0x0002u) /* Comp. E Output Polarity */
\r
1349 #define CEF (0x0004u) /* Comp. E Enable Output Filter */
\r
1350 #define CEIES (0x0008u) /* Comp. E Interrupt Edge Select */
\r
1351 #define CESHORT (0x0010u) /* Comp. E Input Short */
\r
1352 #define CEEX (0x0020u) /* Comp. E Exchange Inputs */
\r
1353 #define CEFDLY0 (0x0040u) /* Comp. E Filter delay Bit 0 */
\r
1354 #define CEFDLY1 (0x0080u) /* Comp. E Filter delay Bit 1 */
\r
1355 #define CEPWRMD0 (0x0100u) /* Comp. E Power mode Bit 0 */
\r
1356 #define CEPWRMD1 (0x0200u) /* Comp. E Power mode Bit 1 */
\r
1357 #define CEON (0x0400u) /* Comp. E enable */
\r
1358 #define CEMRVL (0x0800u) /* Comp. E CEMRV Level */
\r
1359 #define CEMRVS (0x1000u) /* Comp. E Output selects between VREF0 or VREF1*/
\r
1360 //#define RESERVED (0x2000u) /* Comp. E */
\r
1361 //#define RESERVED (0x4000u) /* Comp. E */
\r
1362 //#define RESERVED (0x8000u) /* Comp. E */
\r
1364 /* CECTL1 Control Bits */
\r
1365 #define CEOUT_L (0x0001u) /* Comp. E Output */
\r
1366 #define CEOUTPOL_L (0x0002u) /* Comp. E Output Polarity */
\r
1367 #define CEF_L (0x0004u) /* Comp. E Enable Output Filter */
\r
1368 #define CEIES_L (0x0008u) /* Comp. E Interrupt Edge Select */
\r
1369 #define CESHORT_L (0x0010u) /* Comp. E Input Short */
\r
1370 #define CEEX_L (0x0020u) /* Comp. E Exchange Inputs */
\r
1371 #define CEFDLY0_L (0x0040u) /* Comp. E Filter delay Bit 0 */
\r
1372 #define CEFDLY1_L (0x0080u) /* Comp. E Filter delay Bit 1 */
\r
1373 //#define RESERVED (0x2000u) /* Comp. E */
\r
1374 //#define RESERVED (0x4000u) /* Comp. E */
\r
1375 //#define RESERVED (0x8000u) /* Comp. E */
\r
1377 /* CECTL1 Control Bits */
\r
1378 #define CEPWRMD0_H (0x0001u) /* Comp. E Power mode Bit 0 */
\r
1379 #define CEPWRMD1_H (0x0002u) /* Comp. E Power mode Bit 1 */
\r
1380 #define CEON_H (0x0004u) /* Comp. E enable */
\r
1381 #define CEMRVL_H (0x0008u) /* Comp. E CEMRV Level */
\r
1382 #define CEMRVS_H (0x0010u) /* Comp. E Output selects between VREF0 or VREF1*/
\r
1383 //#define RESERVED (0x2000u) /* Comp. E */
\r
1384 //#define RESERVED (0x4000u) /* Comp. E */
\r
1385 //#define RESERVED (0x8000u) /* Comp. E */
\r
1387 #define CEPWRMD_0 (0x0000u) /* Comp. E Power mode 0 */
\r
1388 #define CEPWRMD_1 (0x0100u) /* Comp. E Power mode 1 */
\r
1389 #define CEPWRMD_2 (0x0200u) /* Comp. E Power mode 2 */
\r
1390 #define CEPWRMD_3 (0x0300u) /* Comp. E Power mode 3*/
\r
1392 #define CEFDLY_0 (0x0000u) /* Comp. E Filter delay 0 : 450ns */
\r
1393 #define CEFDLY_1 (0x0040u) /* Comp. E Filter delay 1 : 900ns */
\r
1394 #define CEFDLY_2 (0x0080u) /* Comp. E Filter delay 2 : 1800ns */
\r
1395 #define CEFDLY_3 (0x00C0u) /* Comp. E Filter delay 3 : 3600ns */
\r
1397 /* CECTL2 Control Bits */
\r
1398 #define CEREF00 (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */
\r
1399 #define CEREF01 (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */
\r
1400 #define CEREF02 (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */
\r
1401 #define CEREF03 (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */
\r
1402 #define CEREF04 (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */
\r
1403 #define CERSEL (0x0020u) /* Comp. E Reference select */
\r
1404 #define CERS0 (0x0040u) /* Comp. E Reference Source Bit : 0 */
\r
1405 #define CERS1 (0x0080u) /* Comp. E Reference Source Bit : 1 */
\r
1406 #define CEREF10 (0x0100u) /* Comp. E Reference 1 Resistor Select Bit : 0 */
\r
1407 #define CEREF11 (0x0200u) /* Comp. E Reference 1 Resistor Select Bit : 1 */
\r
1408 #define CEREF12 (0x0400u) /* Comp. E Reference 1 Resistor Select Bit : 2 */
\r
1409 #define CEREF13 (0x0800u) /* Comp. E Reference 1 Resistor Select Bit : 3 */
\r
1410 #define CEREF14 (0x1000u) /* Comp. E Reference 1 Resistor Select Bit : 4 */
\r
1411 #define CEREFL0 (0x2000u) /* Comp. E Reference voltage level Bit : 0 */
\r
1412 #define CEREFL1 (0x4000u) /* Comp. E Reference voltage level Bit : 1 */
\r
1413 #define CEREFACC (0x8000u) /* Comp. E Reference Accuracy */
\r
1415 /* CECTL2 Control Bits */
\r
1416 #define CEREF00_L (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */
\r
1417 #define CEREF01_L (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */
\r
1418 #define CEREF02_L (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */
\r
1419 #define CEREF03_L (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */
\r
1420 #define CEREF04_L (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */
\r
1421 #define CERSEL_L (0x0020u) /* Comp. E Reference select */
\r
1422 #define CERS0_L (0x0040u) /* Comp. E Reference Source Bit : 0 */
\r
1423 #define CERS1_L (0x0080u) /* Comp. E Reference Source Bit : 1 */
\r
1425 /* CECTL2 Control Bits */
\r
1426 #define CEREF10_H (0x0001u) /* Comp. E Reference 1 Resistor Select Bit : 0 */
\r
1427 #define CEREF11_H (0x0002u) /* Comp. E Reference 1 Resistor Select Bit : 1 */
\r
1428 #define CEREF12_H (0x0004u) /* Comp. E Reference 1 Resistor Select Bit : 2 */
\r
1429 #define CEREF13_H (0x0008u) /* Comp. E Reference 1 Resistor Select Bit : 3 */
\r
1430 #define CEREF14_H (0x0010u) /* Comp. E Reference 1 Resistor Select Bit : 4 */
\r
1431 #define CEREFL0_H (0x0020u) /* Comp. E Reference voltage level Bit : 0 */
\r
1432 #define CEREFL1_H (0x0040u) /* Comp. E Reference voltage level Bit : 1 */
\r
1433 #define CEREFACC_H (0x0080u) /* Comp. E Reference Accuracy */
\r
1435 #define CEREF0_0 (0x0000u) /* Comp. E Int. Ref.0 Select 0 : 1/32 */
\r
1436 #define CEREF0_1 (0x0001u) /* Comp. E Int. Ref.0 Select 1 : 2/32 */
\r
1437 #define CEREF0_2 (0x0002u) /* Comp. E Int. Ref.0 Select 2 : 3/32 */
\r
1438 #define CEREF0_3 (0x0003u) /* Comp. E Int. Ref.0 Select 3 : 4/32 */
\r
1439 #define CEREF0_4 (0x0004u) /* Comp. E Int. Ref.0 Select 4 : 5/32 */
\r
1440 #define CEREF0_5 (0x0005u) /* Comp. E Int. Ref.0 Select 5 : 6/32 */
\r
1441 #define CEREF0_6 (0x0006u) /* Comp. E Int. Ref.0 Select 6 : 7/32 */
\r
1442 #define CEREF0_7 (0x0007u) /* Comp. E Int. Ref.0 Select 7 : 8/32 */
\r
1443 #define CEREF0_8 (0x0008u) /* Comp. E Int. Ref.0 Select 0 : 9/32 */
\r
1444 #define CEREF0_9 (0x0009u) /* Comp. E Int. Ref.0 Select 1 : 10/32 */
\r
1445 #define CEREF0_10 (0x000Au) /* Comp. E Int. Ref.0 Select 2 : 11/32 */
\r
1446 #define CEREF0_11 (0x000Bu) /* Comp. E Int. Ref.0 Select 3 : 12/32 */
\r
1447 #define CEREF0_12 (0x000Cu) /* Comp. E Int. Ref.0 Select 4 : 13/32 */
\r
1448 #define CEREF0_13 (0x000Du) /* Comp. E Int. Ref.0 Select 5 : 14/32 */
\r
1449 #define CEREF0_14 (0x000Eu) /* Comp. E Int. Ref.0 Select 6 : 15/32 */
\r
1450 #define CEREF0_15 (0x000Fu) /* Comp. E Int. Ref.0 Select 7 : 16/32 */
\r
1451 #define CEREF0_16 (0x0010u) /* Comp. E Int. Ref.0 Select 0 : 17/32 */
\r
1452 #define CEREF0_17 (0x0011u) /* Comp. E Int. Ref.0 Select 1 : 18/32 */
\r
1453 #define CEREF0_18 (0x0012u) /* Comp. E Int. Ref.0 Select 2 : 19/32 */
\r
1454 #define CEREF0_19 (0x0013u) /* Comp. E Int. Ref.0 Select 3 : 20/32 */
\r
1455 #define CEREF0_20 (0x0014u) /* Comp. E Int. Ref.0 Select 4 : 21/32 */
\r
1456 #define CEREF0_21 (0x0015u) /* Comp. E Int. Ref.0 Select 5 : 22/32 */
\r
1457 #define CEREF0_22 (0x0016u) /* Comp. E Int. Ref.0 Select 6 : 23/32 */
\r
1458 #define CEREF0_23 (0x0017u) /* Comp. E Int. Ref.0 Select 7 : 24/32 */
\r
1459 #define CEREF0_24 (0x0018u) /* Comp. E Int. Ref.0 Select 0 : 25/32 */
\r
1460 #define CEREF0_25 (0x0019u) /* Comp. E Int. Ref.0 Select 1 : 26/32 */
\r
1461 #define CEREF0_26 (0x001Au) /* Comp. E Int. Ref.0 Select 2 : 27/32 */
\r
1462 #define CEREF0_27 (0x001Bu) /* Comp. E Int. Ref.0 Select 3 : 28/32 */
\r
1463 #define CEREF0_28 (0x001Cu) /* Comp. E Int. Ref.0 Select 4 : 29/32 */
\r
1464 #define CEREF0_29 (0x001Du) /* Comp. E Int. Ref.0 Select 5 : 30/32 */
\r
1465 #define CEREF0_30 (0x001Eu) /* Comp. E Int. Ref.0 Select 6 : 31/32 */
\r
1466 #define CEREF0_31 (0x001Fu) /* Comp. E Int. Ref.0 Select 7 : 32/32 */
\r
1468 #define CERS_0 (0x0000u) /* Comp. E Reference Source 0 : Off */
\r
1469 #define CERS_1 (0x0040u) /* Comp. E Reference Source 1 : Vcc */
\r
1470 #define CERS_2 (0x0080u) /* Comp. E Reference Source 2 : Shared Ref. */
\r
1471 #define CERS_3 (0x00C0u) /* Comp. E Reference Source 3 : Shared Ref. / Off */
\r
1473 #define CEREF1_0 (0x0000u) /* Comp. E Int. Ref.1 Select 0 : 1/32 */
\r
1474 #define CEREF1_1 (0x0100u) /* Comp. E Int. Ref.1 Select 1 : 2/32 */
\r
1475 #define CEREF1_2 (0x0200u) /* Comp. E Int. Ref.1 Select 2 : 3/32 */
\r
1476 #define CEREF1_3 (0x0300u) /* Comp. E Int. Ref.1 Select 3 : 4/32 */
\r
1477 #define CEREF1_4 (0x0400u) /* Comp. E Int. Ref.1 Select 4 : 5/32 */
\r
1478 #define CEREF1_5 (0x0500u) /* Comp. E Int. Ref.1 Select 5 : 6/32 */
\r
1479 #define CEREF1_6 (0x0600u) /* Comp. E Int. Ref.1 Select 6 : 7/32 */
\r
1480 #define CEREF1_7 (0x0700u) /* Comp. E Int. Ref.1 Select 7 : 8/32 */
\r
1481 #define CEREF1_8 (0x0800u) /* Comp. E Int. Ref.1 Select 0 : 9/32 */
\r
1482 #define CEREF1_9 (0x0900u) /* Comp. E Int. Ref.1 Select 1 : 10/32 */
\r
1483 #define CEREF1_10 (0x0A00u) /* Comp. E Int. Ref.1 Select 2 : 11/32 */
\r
1484 #define CEREF1_11 (0x0B00u) /* Comp. E Int. Ref.1 Select 3 : 12/32 */
\r
1485 #define CEREF1_12 (0x0C00u) /* Comp. E Int. Ref.1 Select 4 : 13/32 */
\r
1486 #define CEREF1_13 (0x0D00u) /* Comp. E Int. Ref.1 Select 5 : 14/32 */
\r
1487 #define CEREF1_14 (0x0E00u) /* Comp. E Int. Ref.1 Select 6 : 15/32 */
\r
1488 #define CEREF1_15 (0x0F00u) /* Comp. E Int. Ref.1 Select 7 : 16/32 */
\r
1489 #define CEREF1_16 (0x1000u) /* Comp. E Int. Ref.1 Select 0 : 17/32 */
\r
1490 #define CEREF1_17 (0x1100u) /* Comp. E Int. Ref.1 Select 1 : 18/32 */
\r
1491 #define CEREF1_18 (0x1200u) /* Comp. E Int. Ref.1 Select 2 : 19/32 */
\r
1492 #define CEREF1_19 (0x1300u) /* Comp. E Int. Ref.1 Select 3 : 20/32 */
\r
1493 #define CEREF1_20 (0x1400u) /* Comp. E Int. Ref.1 Select 4 : 21/32 */
\r
1494 #define CEREF1_21 (0x1500u) /* Comp. E Int. Ref.1 Select 5 : 22/32 */
\r
1495 #define CEREF1_22 (0x1600u) /* Comp. E Int. Ref.1 Select 6 : 23/32 */
\r
1496 #define CEREF1_23 (0x1700u) /* Comp. E Int. Ref.1 Select 7 : 24/32 */
\r
1497 #define CEREF1_24 (0x1800u) /* Comp. E Int. Ref.1 Select 0 : 25/32 */
\r
1498 #define CEREF1_25 (0x1900u) /* Comp. E Int. Ref.1 Select 1 : 26/32 */
\r
1499 #define CEREF1_26 (0x1A00u) /* Comp. E Int. Ref.1 Select 2 : 27/32 */
\r
1500 #define CEREF1_27 (0x1B00u) /* Comp. E Int. Ref.1 Select 3 : 28/32 */
\r
1501 #define CEREF1_28 (0x1C00u) /* Comp. E Int. Ref.1 Select 4 : 29/32 */
\r
1502 #define CEREF1_29 (0x1D00u) /* Comp. E Int. Ref.1 Select 5 : 30/32 */
\r
1503 #define CEREF1_30 (0x1E00u) /* Comp. E Int. Ref.1 Select 6 : 31/32 */
\r
1504 #define CEREF1_31 (0x1F00u) /* Comp. E Int. Ref.1 Select 7 : 32/32 */
\r
1506 #define CEREFL_0 (0x0000u) /* Comp. E Reference voltage level 0 : None */
\r
1507 #define CEREFL_1 (0x2000u) /* Comp. E Reference voltage level 1 : 1.2V */
\r
1508 #define CEREFL_2 (0x4000u) /* Comp. E Reference voltage level 2 : 2.0V */
\r
1509 #define CEREFL_3 (0x6000u) /* Comp. E Reference voltage level 3 : 2.5V */
\r
1511 #define CEPD0 (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */
\r
1512 #define CEPD1 (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */
\r
1513 #define CEPD2 (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */
\r
1514 #define CEPD3 (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */
\r
1515 #define CEPD4 (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */
\r
1516 #define CEPD5 (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */
\r
1517 #define CEPD6 (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */
\r
1518 #define CEPD7 (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */
\r
1519 #define CEPD8 (0x0100u) /* Comp. E Disable Input Buffer of Port Register .8 */
\r
1520 #define CEPD9 (0x0200u) /* Comp. E Disable Input Buffer of Port Register .9 */
\r
1521 #define CEPD10 (0x0400u) /* Comp. E Disable Input Buffer of Port Register .10 */
\r
1522 #define CEPD11 (0x0800u) /* Comp. E Disable Input Buffer of Port Register .11 */
\r
1523 #define CEPD12 (0x1000u) /* Comp. E Disable Input Buffer of Port Register .12 */
\r
1524 #define CEPD13 (0x2000u) /* Comp. E Disable Input Buffer of Port Register .13 */
\r
1525 #define CEPD14 (0x4000u) /* Comp. E Disable Input Buffer of Port Register .14 */
\r
1526 #define CEPD15 (0x8000u) /* Comp. E Disable Input Buffer of Port Register .15 */
\r
1528 #define CEPD0_L (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */
\r
1529 #define CEPD1_L (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */
\r
1530 #define CEPD2_L (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */
\r
1531 #define CEPD3_L (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */
\r
1532 #define CEPD4_L (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */
\r
1533 #define CEPD5_L (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */
\r
1534 #define CEPD6_L (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */
\r
1535 #define CEPD7_L (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */
\r
1537 #define CEPD8_H (0x0001u) /* Comp. E Disable Input Buffer of Port Register .8 */
\r
1538 #define CEPD9_H (0x0002u) /* Comp. E Disable Input Buffer of Port Register .9 */
\r
1539 #define CEPD10_H (0x0004u) /* Comp. E Disable Input Buffer of Port Register .10 */
\r
1540 #define CEPD11_H (0x0008u) /* Comp. E Disable Input Buffer of Port Register .11 */
\r
1541 #define CEPD12_H (0x0010u) /* Comp. E Disable Input Buffer of Port Register .12 */
\r
1542 #define CEPD13_H (0x0020u) /* Comp. E Disable Input Buffer of Port Register .13 */
\r
1543 #define CEPD14_H (0x0040u) /* Comp. E Disable Input Buffer of Port Register .14 */
\r
1544 #define CEPD15_H (0x0080u) /* Comp. E Disable Input Buffer of Port Register .15 */
\r
1546 /* CEINT Control Bits */
\r
1547 #define CEIFG (0x0001u) /* Comp. E Interrupt Flag */
\r
1548 #define CEIIFG (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */
\r
1549 //#define RESERVED (0x0004u) /* Comp. E */
\r
1550 //#define RESERVED (0x0008u) /* Comp. E */
\r
1551 #define CERDYIFG (0x0010u) /* Comp. E Comparator_E ready interrupt flag */
\r
1552 //#define RESERVED (0x0020u) /* Comp. E */
\r
1553 //#define RESERVED (0x0040u) /* Comp. E */
\r
1554 //#define RESERVED (0x0080u) /* Comp. E */
\r
1555 #define CEIE (0x0100u) /* Comp. E Interrupt Enable */
\r
1556 #define CEIIE (0x0200u) /* Comp. E Interrupt Enable Inverted Polarity */
\r
1557 //#define RESERVED (0x0400u) /* Comp. E */
\r
1558 //#define RESERVED (0x0800u) /* Comp. E */
\r
1559 #define CERDYIE (0x1000u) /* Comp. E Comparator_E ready interrupt enable */
\r
1560 //#define RESERVED (0x2000u) /* Comp. E */
\r
1561 //#define RESERVED (0x4000u) /* Comp. E */
\r
1562 //#define RESERVED (0x8000u) /* Comp. E */
\r
1564 /* CEINT Control Bits */
\r
1565 #define CEIFG_L (0x0001u) /* Comp. E Interrupt Flag */
\r
1566 #define CEIIFG_L (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */
\r
1567 //#define RESERVED (0x0004u) /* Comp. E */
\r
1568 //#define RESERVED (0x0008u) /* Comp. E */
\r
1569 #define CERDYIFG_L (0x0010u) /* Comp. E Comparator_E ready interrupt flag */
\r
1570 //#define RESERVED (0x0020u) /* Comp. E */
\r
1571 //#define RESERVED (0x0040u) /* Comp. E */
\r
1572 //#define RESERVED (0x0080u) /* Comp. E */
\r
1573 //#define RESERVED (0x0400u) /* Comp. E */
\r
1574 //#define RESERVED (0x0800u) /* Comp. E */
\r
1575 //#define RESERVED (0x2000u) /* Comp. E */
\r
1576 //#define RESERVED (0x4000u) /* Comp. E */
\r
1577 //#define RESERVED (0x8000u) /* Comp. E */
\r
1579 /* CEINT Control Bits */
\r
1580 //#define RESERVED (0x0004u) /* Comp. E */
\r
1581 //#define RESERVED (0x0008u) /* Comp. E */
\r
1582 //#define RESERVED (0x0020u) /* Comp. E */
\r
1583 //#define RESERVED (0x0040u) /* Comp. E */
\r
1584 //#define RESERVED (0x0080u) /* Comp. E */
\r
1585 #define CEIE_H (0x0001u) /* Comp. E Interrupt Enable */
\r
1586 #define CEIIE_H (0x0002u) /* Comp. E Interrupt Enable Inverted Polarity */
\r
1587 //#define RESERVED (0x0400u) /* Comp. E */
\r
1588 //#define RESERVED (0x0800u) /* Comp. E */
\r
1589 #define CERDYIE_H (0x0010u) /* Comp. E Comparator_E ready interrupt enable */
\r
1590 //#define RESERVED (0x2000u) /* Comp. E */
\r
1591 //#define RESERVED (0x4000u) /* Comp. E */
\r
1592 //#define RESERVED (0x8000u) /* Comp. E */
\r
1594 /* CEIV Definitions */
\r
1595 #define CEIV_NONE (0x0000u) /* No Interrupt pending */
\r
1596 #define CEIV_CEIFG (0x0002u) /* CEIFG */
\r
1597 #define CEIV_CEIIFG (0x0004u) /* CEIIFG */
\r
1598 #define CEIV_CERDYIFG (0x000Au) /* CERDYIFG */
\r
1601 /*************************************************************
\r
1603 *************************************************************/
\r
1604 #ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */
\r
1606 #define OFS_CRCDI (0x0000u) /* CRC Data In Register */
\r
1607 #define OFS_CRCDI_L OFS_CRCDI
\r
1608 #define OFS_CRCDI_H OFS_CRCDI+1
\r
1609 #define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */
\r
1610 #define OFS_CRCDIRB_L OFS_CRCDIRB
\r
1611 #define OFS_CRCDIRB_H OFS_CRCDIRB+1
\r
1612 #define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */
\r
1613 #define OFS_CRCINIRES_L OFS_CRCINIRES
\r
1614 #define OFS_CRCINIRES_H OFS_CRCINIRES+1
\r
1615 #define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */
\r
1616 #define OFS_CRCRESR_L OFS_CRCRESR
\r
1617 #define OFS_CRCRESR_H OFS_CRCRESR+1
\r
1620 /*************************************************************
\r
1622 *************************************************************/
\r
1623 #ifdef __MSP430_HAS_CRC32__ /* Definition to show that Module is available */
\r
1626 //#define CRC32DIL0_O (0x0000u) /* CRC32 Data In */
\r
1627 #define OFS_CRC32DIW0 (0x0000u) /* CRC32 Data In */
\r
1628 #define OFS_CRC32DIW0_L OFS_CRC32DIW0
\r
1629 #define OFS_CRC32DIW0_H OFS_CRC32DIW0+1
\r
1630 #define OFS_CRC32DIW1 (0x0002u) /* CRC32 Data In */
\r
1631 #define OFS_CRC32DIW1_L OFS_CRC32DIW1
\r
1632 #define OFS_CRC32DIW1_H OFS_CRC32DIW1+1
\r
1633 #define CRC32DIB0 CRC32DIW0_L
\r
1635 //#define CRC32DIRBL0_O (0x0004u) /* CRC32 Data In Reversed Bit */
\r
1636 #define OFS_CRC32DIRBW1 (0x0004u) /* CRC32 Data In Reversed Bit */
\r
1637 #define OFS_CRC32DIRBW1_L OFS_CRC32DIRBW1
\r
1638 #define OFS_CRC32DIRBW1_H OFS_CRC32DIRBW1+1
\r
1639 #define OFS_CRC32DIRBW0 (0x0006u) /* CRC32 Data In Reversed Bit */
\r
1640 #define OFS_CRC32DIRBW0_L OFS_CRC32DIRBW0
\r
1641 #define OFS_CRC32DIRBW0_H OFS_CRC32DIRBW0+1
\r
1642 #define CRC32DIRBB0 CRC32DIRBW0_H
\r
1644 //#define CRC32INIRESL0_O (0x0008u) /* CRC32 Initialization and Result */
\r
1645 #define OFS_CRC32INIRESW0 (0x0008u) /* CRC32 Initialization and Result */
\r
1646 #define OFS_CRC32INIRESW0_L OFS_CRC32INIRESW0
\r
1647 #define OFS_CRC32INIRESW0_H OFS_CRC32INIRESW0+1
\r
1648 #define OFS_CRC32INIRESW1 (0x000Au) /* CRC32 Initialization and Result */
\r
1649 #define OFS_CRC32INIRESW1_L OFS_CRC32INIRESW1
\r
1650 #define OFS_CRC32INIRESW1_H OFS_CRC32INIRESW1+1
\r
1651 #define CRC32RESB0 CRC32INIRESW0_L
\r
1652 #define CRC32RESB1 CRC32INIRESW0_H
\r
1653 #define CRC32RESB2 CRC32INIRESW1_L
\r
1654 #define CRC32RESB3 CRC32INIRESW1_H
\r
1656 //#define CRC32RESRL0_O (0x000Cu) /* CRC32 Result Reverse */
\r
1657 #define OFS_CRC32RESRW1 (0x000Cu) /* CRC32 Result Reverse */
\r
1658 #define OFS_CRC32RESRW1_L OFS_CRC32RESRW1
\r
1659 #define OFS_CRC32RESRW1_H OFS_CRC32RESRW1+1
\r
1660 #define OFS_CRC32RESRW0 (0x000Eu) /* CRC32 Result Reverse */
\r
1661 #define OFS_CRC32RESRW0_L OFS_CRC32RESRW0
\r
1662 #define OFS_CRC32RESRW0_H OFS_CRC32RESRW0+1
\r
1663 #define CRC32RESRB3 CRC32RESRW1_L
\r
1664 #define CRC32RESRB2 CRC32RESRW1_H
\r
1665 #define CRC32RESRB1 CRC32RESRW0_L
\r
1666 #define CRC32RESRB0 CRC32RESRW0_H
\r
1668 //#define CRC16DIL0_O (0x0010u) /* CRC16 Data Input */
\r
1669 #define OFS_CRC16DIW0 (0x0010u) /* CRC16 Data Input */
\r
1670 #define OFS_CRC16DIW0_L OFS_CRC16DIW0
\r
1671 #define OFS_CRC16DIW0_H OFS_CRC16DIW0+1
\r
1672 #define OFS_CRC16DIW1 (0x0012u) /* CRC16 Data Input */
\r
1673 #define OFS_CRC16DIW1_L OFS_CRC16DIW1
\r
1674 #define OFS_CRC16DIW1_H OFS_CRC16DIW1+1
\r
1675 #define CRC16DIB0 CRC16DIW0_L
\r
1676 //#define CRC16DIRBL0_O (0x0014u) /* CRC16 Data In Reverse */
\r
1677 #define OFS_CRC16DIRBW1 (0x0014u) /* CRC16 Data In Reverse */
\r
1678 #define OFS_CRC16DIRBW1_L OFS_CRC16DIRBW1
\r
1679 #define OFS_CRC16DIRBW1_H OFS_CRC16DIRBW1+1
\r
1680 #define OFS_CRC16DIRBW0 (0x0016u) /* CRC16 Data In Reverse */
\r
1681 #define OFS_CRC16DIRBW0_L OFS_CRC16DIRBW0
\r
1682 #define OFS_CRC16DIRBW0_H OFS_CRC16DIRBW0+1
\r
1683 #define CRC16DIRBB0 CRC16DIRBW0_L
\r
1685 //#define CRC16INIRESL0_O (0x0018u) /* CRC16 Init and Result */
\r
1686 #define OFS_CRC16INIRESW0 (0x0018u) /* CRC16 Init and Result */
\r
1687 #define OFS_CRC16INIRESW0_L OFS_CRC16INIRESW0
\r
1688 #define OFS_CRC16INIRESW0_H OFS_CRC16INIRESW0+1
\r
1689 #define CRC16INIRESB1 CRC16INIRESW0_H
\r
1690 #define CRC16INIRESB0 CRC16INIRESW0_L
\r
1692 //#define CRC16RESRL0_O (0x001Eu) /* CRC16 Result Reverse */
\r
1693 #define OFS_CRC16RESRW0 (0x001Eu) /* CRC16 Result Reverse */
\r
1694 #define OFS_CRC16RESRW0_L OFS_CRC16RESRW0
\r
1695 #define OFS_CRC16RESRW0_H OFS_CRC16RESRW0+1
\r
1696 #define OFS_CRC16RESRW1 (0x001Cu) /* CRC16 Result Reverse */
\r
1697 #define OFS_CRC16RESRW1_L OFS_CRC16RESRW1
\r
1698 #define OFS_CRC16RESRW1_H OFS_CRC16RESRW1+1
\r
1699 #define CRC16RESRB1 CRC16RESRW0_L
\r
1700 #define CRC16RESRB0 CRC16RESRW0_H
\r
1703 /************************************************************
\r
1705 ************************************************************/
\r
1706 #ifdef __MSP430_HAS_CS__ /* Definition to show that Module is available */
\r
1708 #define OFS_CSCTL0 (0x0000u) /* CS Control Register 0 */
\r
1709 #define OFS_CSCTL0_L OFS_CSCTL0
\r
1710 #define OFS_CSCTL0_H OFS_CSCTL0+1
\r
1711 #define OFS_CSCTL1 (0x0002u) /* CS Control Register 1 */
\r
1712 #define OFS_CSCTL1_L OFS_CSCTL1
\r
1713 #define OFS_CSCTL1_H OFS_CSCTL1+1
\r
1714 #define OFS_CSCTL2 (0x0004u) /* CS Control Register 2 */
\r
1715 #define OFS_CSCTL2_L OFS_CSCTL2
\r
1716 #define OFS_CSCTL2_H OFS_CSCTL2+1
\r
1717 #define OFS_CSCTL3 (0x0006u) /* CS Control Register 3 */
\r
1718 #define OFS_CSCTL3_L OFS_CSCTL3
\r
1719 #define OFS_CSCTL3_H OFS_CSCTL3+1
\r
1720 #define OFS_CSCTL4 (0x0008u) /* CS Control Register 4 */
\r
1721 #define OFS_CSCTL4_L OFS_CSCTL4
\r
1722 #define OFS_CSCTL4_H OFS_CSCTL4+1
\r
1723 #define OFS_CSCTL5 (0x000Au) /* CS Control Register 5 */
\r
1724 #define OFS_CSCTL5_L OFS_CSCTL5
\r
1725 #define OFS_CSCTL5_H OFS_CSCTL5+1
\r
1726 #define OFS_CSCTL6 (0x000Cu) /* CS Control Register 6 */
\r
1727 #define OFS_CSCTL6_L OFS_CSCTL6
\r
1728 #define OFS_CSCTL6_H OFS_CSCTL6+1
\r
1730 /* CSCTL0 Control Bits */
\r
1732 #define CSKEY (0xA500u) /* CS Password */
\r
1733 #define CSKEY_H (0xA5) /* CS Password for high byte access */
\r
1735 /* CSCTL1 Control Bits */
\r
1736 #define DCOFSEL0 (0x0002u) /* DCO frequency select Bit: 0 */
\r
1737 #define DCOFSEL1 (0x0004u) /* DCO frequency select Bit: 1 */
\r
1738 #define DCOFSEL2 (0x0008u) /* DCO frequency select Bit: 2 */
\r
1739 #define DCORSEL (0x0040u) /* DCO range select. */
\r
1741 /* CSCTL1 Control Bits */
\r
1742 #define DCOFSEL0_L (0x0002u) /* DCO frequency select Bit: 0 */
\r
1743 #define DCOFSEL1_L (0x0004u) /* DCO frequency select Bit: 1 */
\r
1744 #define DCOFSEL2_L (0x0008u) /* DCO frequency select Bit: 2 */
\r
1745 #define DCORSEL_L (0x0040u) /* DCO range select. */
\r
1747 #define DCOFSEL_0 (0x0000u) /* DCO frequency select: 0 */
\r
1748 #define DCOFSEL_1 (0x0002u) /* DCO frequency select: 1 */
\r
1749 #define DCOFSEL_2 (0x0004u) /* DCO frequency select: 2 */
\r
1750 #define DCOFSEL_3 (0x0006u) /* DCO frequency select: 3 */
\r
1751 #define DCOFSEL_4 (0x0008u) /* DCO frequency select: 4 */
\r
1752 #define DCOFSEL_5 (0x000Au) /* DCO frequency select: 5 */
\r
1753 #define DCOFSEL_6 (0x000Cu) /* DCO frequency select: 6 */
\r
1754 #define DCOFSEL_7 (0x000Eu) /* DCO frequency select: 7 */
\r
1756 /* CSCTL2 Control Bits */
\r
1757 #define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */
\r
1758 #define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */
\r
1759 #define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */
\r
1760 //#define RESERVED (0x0004u) /* RESERVED */
\r
1761 //#define RESERVED (0x0008u) /* RESERVED */
\r
1762 #define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */
\r
1763 #define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */
\r
1764 #define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */
\r
1765 //#define RESERVED (0x0040u) /* RESERVED */
\r
1766 //#define RESERVED (0x0080u) /* RESERVED */
\r
1767 #define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */
\r
1768 #define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */
\r
1769 #define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */
\r
1770 //#define RESERVED (0x0400u) /* RESERVED */
\r
1771 //#define RESERVED (0x0800u) /* RESERVED */
\r
1772 //#define RESERVED (0x1000u) /* RESERVED */
\r
1773 //#define RESERVED (0x2000u) /* RESERVED */
\r
1774 //#define RESERVED (0x4000u) /* RESERVED */
\r
1775 //#define RESERVED (0x8000u) /* RESERVED */
\r
1777 /* CSCTL2 Control Bits */
\r
1778 #define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */
\r
1779 #define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */
\r
1780 #define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */
\r
1781 //#define RESERVED (0x0004u) /* RESERVED */
\r
1782 //#define RESERVED (0x0008u) /* RESERVED */
\r
1783 #define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */
\r
1784 #define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */
\r
1785 #define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */
\r
1786 //#define RESERVED (0x0040u) /* RESERVED */
\r
1787 //#define RESERVED (0x0080u) /* RESERVED */
\r
1788 //#define RESERVED (0x0400u) /* RESERVED */
\r
1789 //#define RESERVED (0x0800u) /* RESERVED */
\r
1790 //#define RESERVED (0x1000u) /* RESERVED */
\r
1791 //#define RESERVED (0x2000u) /* RESERVED */
\r
1792 //#define RESERVED (0x4000u) /* RESERVED */
\r
1793 //#define RESERVED (0x8000u) /* RESERVED */
\r
1795 /* CSCTL2 Control Bits */
\r
1796 //#define RESERVED (0x0004u) /* RESERVED */
\r
1797 //#define RESERVED (0x0008u) /* RESERVED */
\r
1798 //#define RESERVED (0x0040u) /* RESERVED */
\r
1799 //#define RESERVED (0x0080u) /* RESERVED */
\r
1800 #define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */
\r
1801 #define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */
\r
1802 #define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */
\r
1803 //#define RESERVED (0x0400u) /* RESERVED */
\r
1804 //#define RESERVED (0x0800u) /* RESERVED */
\r
1805 //#define RESERVED (0x1000u) /* RESERVED */
\r
1806 //#define RESERVED (0x2000u) /* RESERVED */
\r
1807 //#define RESERVED (0x4000u) /* RESERVED */
\r
1808 //#define RESERVED (0x8000u) /* RESERVED */
\r
1810 #define SELM_0 (0x0000u) /* MCLK Source Select 0 */
\r
1811 #define SELM_1 (0x0001u) /* MCLK Source Select 1 */
\r
1812 #define SELM_2 (0x0002u) /* MCLK Source Select 2 */
\r
1813 #define SELM_3 (0x0003u) /* MCLK Source Select 3 */
\r
1814 #define SELM_4 (0x0004u) /* MCLK Source Select 4 */
\r
1815 #define SELM_5 (0x0005u) /* MCLK Source Select 5 */
\r
1816 #define SELM_6 (0x0006u) /* MCLK Source Select 6 */
\r
1817 #define SELM_7 (0x0007u) /* MCLK Source Select 7 */
\r
1818 #define SELM__LFXTCLK (0x0000u) /* MCLK Source Select LFXTCLK */
\r
1819 #define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */
\r
1820 #define SELM__LFMODOSC (0x0002u) /* MCLK Source Select LFMODOSC */
\r
1821 #define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */
\r
1822 #define SELM__MODOSC (0x0004u) /* MCLK Source Select MODOSC */
\r
1823 #define SELM__HFXTCLK (0x0005u) /* MCLK Source Select HFXTCLK */
\r
1825 #define SELS_0 (0x0000u) /* SMCLK Source Select 0 */
\r
1826 #define SELS_1 (0x0010u) /* SMCLK Source Select 1 */
\r
1827 #define SELS_2 (0x0020u) /* SMCLK Source Select 2 */
\r
1828 #define SELS_3 (0x0030u) /* SMCLK Source Select 3 */
\r
1829 #define SELS_4 (0x0040u) /* SMCLK Source Select 4 */
\r
1830 #define SELS_5 (0x0050u) /* SMCLK Source Select 5 */
\r
1831 #define SELS_6 (0x0060u) /* SMCLK Source Select 6 */
\r
1832 #define SELS_7 (0x0070u) /* SMCLK Source Select 7 */
\r
1833 #define SELS__LFXTCLK (0x0000u) /* SMCLK Source Select LFXTCLK */
\r
1834 #define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */
\r
1835 #define SELS__LFMODOSC (0x0020u) /* SMCLK Source Select LFMODOSC */
\r
1836 #define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */
\r
1837 #define SELS__MODOSC (0x0040u) /* SMCLK Source Select MODOSC */
\r
1838 #define SELS__HFXTCLK (0x0050u) /* SMCLK Source Select HFXTCLK */
\r
1840 #define SELA_0 (0x0000u) /* ACLK Source Select 0 */
\r
1841 #define SELA_1 (0x0100u) /* ACLK Source Select 1 */
\r
1842 #define SELA_2 (0x0200u) /* ACLK Source Select 2 */
\r
1843 #define SELA_3 (0x0300u) /* ACLK Source Select 3 */
\r
1844 #define SELA_4 (0x0400u) /* ACLK Source Select 4 */
\r
1845 #define SELA_5 (0x0500u) /* ACLK Source Select 5 */
\r
1846 #define SELA_6 (0x0600u) /* ACLK Source Select 6 */
\r
1847 #define SELA_7 (0x0700u) /* ACLK Source Select 7 */
\r
1848 #define SELA__LFXTCLK (0x0000u) /* ACLK Source Select LFXTCLK */
\r
1849 #define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */
\r
1850 #define SELA__LFMODOSC (0x0200u) /* ACLK Source Select LFMODOSC */
\r
1852 /* CSCTL3 Control Bits */
\r
1853 #define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */
\r
1854 #define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */
\r
1855 #define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */
\r
1856 //#define RESERVED (0x0004u) /* RESERVED */
\r
1857 //#define RESERVED (0x0008u) /* RESERVED */
\r
1858 #define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */
\r
1859 #define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */
\r
1860 #define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */
\r
1861 //#define RESERVED (0x0040u) /* RESERVED */
\r
1862 //#define RESERVED (0x0080u) /* RESERVED */
\r
1863 #define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */
\r
1864 #define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */
\r
1865 #define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */
\r
1866 //#define RESERVED (0x0400u) /* RESERVED */
\r
1867 //#define RESERVED (0x0800u) /* RESERVED */
\r
1868 //#define RESERVED (0x1000u) /* RESERVED */
\r
1869 //#define RESERVED (0x2000u) /* RESERVED */
\r
1870 //#define RESERVED (0x4000u) /* RESERVED */
\r
1871 //#define RESERVED (0x8000u) /* RESERVED */
\r
1873 /* CSCTL3 Control Bits */
\r
1874 #define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */
\r
1875 #define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */
\r
1876 #define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */
\r
1877 //#define RESERVED (0x0004u) /* RESERVED */
\r
1878 //#define RESERVED (0x0008u) /* RESERVED */
\r
1879 #define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */
\r
1880 #define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */
\r
1881 #define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */
\r
1882 //#define RESERVED (0x0040u) /* RESERVED */
\r
1883 //#define RESERVED (0x0080u) /* RESERVED */
\r
1884 //#define RESERVED (0x0400u) /* RESERVED */
\r
1885 //#define RESERVED (0x0800u) /* RESERVED */
\r
1886 //#define RESERVED (0x1000u) /* RESERVED */
\r
1887 //#define RESERVED (0x2000u) /* RESERVED */
\r
1888 //#define RESERVED (0x4000u) /* RESERVED */
\r
1889 //#define RESERVED (0x8000u) /* RESERVED */
\r
1891 /* CSCTL3 Control Bits */
\r
1892 //#define RESERVED (0x0004u) /* RESERVED */
\r
1893 //#define RESERVED (0x0008u) /* RESERVED */
\r
1894 //#define RESERVED (0x0040u) /* RESERVED */
\r
1895 //#define RESERVED (0x0080u) /* RESERVED */
\r
1896 #define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */
\r
1897 #define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */
\r
1898 #define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */
\r
1899 //#define RESERVED (0x0400u) /* RESERVED */
\r
1900 //#define RESERVED (0x0800u) /* RESERVED */
\r
1901 //#define RESERVED (0x1000u) /* RESERVED */
\r
1902 //#define RESERVED (0x2000u) /* RESERVED */
\r
1903 //#define RESERVED (0x4000u) /* RESERVED */
\r
1904 //#define RESERVED (0x8000u) /* RESERVED */
\r
1906 #define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */
\r
1907 #define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */
\r
1908 #define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */
\r
1909 #define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */
\r
1910 #define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */
\r
1911 #define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */
\r
1912 #define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */
\r
1913 #define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */
\r
1914 #define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */
\r
1915 #define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */
\r
1916 #define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */
\r
1917 #define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */
\r
1919 #define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */
\r
1920 #define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */
\r
1921 #define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */
\r
1922 #define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */
\r
1923 #define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */
\r
1924 #define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */
\r
1925 #define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */
\r
1926 #define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */
\r
1927 #define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */
\r
1928 #define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */
\r
1929 #define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */
\r
1930 #define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */
\r
1932 #define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */
\r
1933 #define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */
\r
1934 #define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */
\r
1935 #define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */
\r
1936 #define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */
\r
1937 #define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */
\r
1938 #define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */
\r
1939 #define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */
\r
1940 #define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */
\r
1941 #define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */
\r
1942 #define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */
\r
1943 #define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */
\r
1945 /* CSCTL4 Control Bits */
\r
1946 #define LFXTOFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
\r
1947 #define SMCLKOFF (0x0002u) /* SMCLK Off */
\r
1948 #define VLOOFF (0x0008u) /* VLO Off */
\r
1949 #define LFXTBYPASS (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
\r
1950 #define LFXTAGCOFF (0x0020u) /* LFXT automatic gain control off */
\r
1951 #define LFXTDRIVE0 (0x0040u) /* LFXT Drive Level mode Bit 0 */
\r
1952 #define LFXTDRIVE1 (0x0080u) /* LFXT Drive Level mode Bit 1 */
\r
1953 #define HFXTOFF (0x0100u) /* High Frequency Oscillator disable */
\r
1954 #define HFFREQ0 (0x0400u) /* HFXT frequency selection Bit 1 */
\r
1955 #define HFFREQ1 (0x0800u) /* HFXT frequency selection Bit 0 */
\r
1956 #define HFXTBYPASS (0x1000u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
\r
1957 #define HFXTDRIVE0 (0x4000u) /* HFXT Drive Level mode Bit 0 */
\r
1958 #define HFXTDRIVE1 (0x8000u) /* HFXT Drive Level mode Bit 1 */
\r
1960 /* CSCTL4 Control Bits */
\r
1961 #define LFXTOFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
\r
1962 #define SMCLKOFF_L (0x0002u) /* SMCLK Off */
\r
1963 #define VLOOFF_L (0x0008u) /* VLO Off */
\r
1964 #define LFXTBYPASS_L (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
\r
1965 #define LFXTAGCOFF_L (0x0020u) /* LFXT automatic gain control off */
\r
1966 #define LFXTDRIVE0_L (0x0040u) /* LFXT Drive Level mode Bit 0 */
\r
1967 #define LFXTDRIVE1_L (0x0080u) /* LFXT Drive Level mode Bit 1 */
\r
1969 /* CSCTL4 Control Bits */
\r
1970 #define HFXTOFF_H (0x0001u) /* High Frequency Oscillator disable */
\r
1971 #define HFFREQ0_H (0x0004u) /* HFXT frequency selection Bit 1 */
\r
1972 #define HFFREQ1_H (0x0008u) /* HFXT frequency selection Bit 0 */
\r
1973 #define HFXTBYPASS_H (0x0010u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
\r
1974 #define HFXTDRIVE0_H (0x0040u) /* HFXT Drive Level mode Bit 0 */
\r
1975 #define HFXTDRIVE1_H (0x0080u) /* HFXT Drive Level mode Bit 1 */
\r
1977 #define LFXTDRIVE_0 (0x0000u) /* LFXT Drive Level mode: 0 */
\r
1978 #define LFXTDRIVE_1 (0x0040u) /* LFXT Drive Level mode: 1 */
\r
1979 #define LFXTDRIVE_2 (0x0080u) /* LFXT Drive Level mode: 2 */
\r
1980 #define LFXTDRIVE_3 (0x00C0u) /* LFXT Drive Level mode: 3 */
\r
1982 #define HFFREQ_0 (0x0000u) /* HFXT frequency selection: 0 */
\r
1983 #define HFFREQ_1 (0x0400u) /* HFXT frequency selection: 1 */
\r
1984 #define HFFREQ_2 (0x0800u) /* HFXT frequency selection: 2 */
\r
1985 #define HFFREQ_3 (0x0C00u) /* HFXT frequency selection: 3 */
\r
1987 #define HFXTDRIVE_0 (0x0000u) /* HFXT Drive Level mode: 0 */
\r
1988 #define HFXTDRIVE_1 (0x4000u) /* HFXT Drive Level mode: 1 */
\r
1989 #define HFXTDRIVE_2 (0x8000u) /* HFXT Drive Level mode: 2 */
\r
1990 #define HFXTDRIVE_3 (0xC000u) /* HFXT Drive Level mode: 3 */
\r
1992 /* CSCTL5 Control Bits */
\r
1993 #define LFXTOFFG (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */
\r
1994 #define HFXTOFFG (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */
\r
1995 #define ENSTFCNT1 (0x0040u) /* Enable start counter for XT1 */
\r
1996 #define ENSTFCNT2 (0x0080u) /* Enable start counter for XT2 */
\r
1998 /* CSCTL5 Control Bits */
\r
1999 #define LFXTOFFG_L (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */
\r
2000 #define HFXTOFFG_L (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */
\r
2001 #define ENSTFCNT1_L (0x0040u) /* Enable start counter for XT1 */
\r
2002 #define ENSTFCNT2_L (0x0080u) /* Enable start counter for XT2 */
\r
2004 /* CSCTL6 Control Bits */
\r
2005 #define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */
\r
2006 #define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */
\r
2007 #define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */
\r
2008 #define MODCLKREQEN (0x0008u) /* MODOSC Clock Request Enable */
\r
2010 /* CSCTL6 Control Bits */
\r
2011 #define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */
\r
2012 #define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */
\r
2013 #define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */
\r
2014 #define MODCLKREQEN_L (0x0008u) /* MODOSC Clock Request Enable */
\r
2017 /************************************************************
\r
2019 ************************************************************/
\r
2020 #ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
\r
2022 #define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */
\r
2023 #define OFS_DMACTL0_L OFS_DMACTL0
\r
2024 #define OFS_DMACTL0_H OFS_DMACTL0+1
\r
2025 #define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */
\r
2026 #define OFS_DMACTL1_L OFS_DMACTL1
\r
2027 #define OFS_DMACTL1_H OFS_DMACTL1+1
\r
2028 #define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */
\r
2029 #define OFS_DMACTL2_L OFS_DMACTL2
\r
2030 #define OFS_DMACTL2_H OFS_DMACTL2+1
\r
2031 #define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */
\r
2032 #define OFS_DMACTL3_L OFS_DMACTL3
\r
2033 #define OFS_DMACTL3_H OFS_DMACTL3+1
\r
2034 #define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */
\r
2035 #define OFS_DMACTL4_L OFS_DMACTL4
\r
2036 #define OFS_DMACTL4_H OFS_DMACTL4+1
\r
2037 #define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */
\r
2038 #define OFS_DMAIV_L OFS_DMAIV
\r
2039 #define OFS_DMAIV_H OFS_DMAIV+1
\r
2041 #define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */
\r
2042 #define OFS_DMA0CTL_L OFS_DMA0CTL
\r
2043 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
\r
2044 #define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */
\r
2045 #define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */
\r
2046 #define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */
\r
2048 #define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */
\r
2049 #define OFS_DMA1CTL_L OFS_DMA1CTL
\r
2050 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
\r
2051 #define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */
\r
2052 #define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */
\r
2053 #define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */
\r
2055 #define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */
\r
2056 #define OFS_DMA2CTL_L OFS_DMA2CTL
\r
2057 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
\r
2058 #define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */
\r
2059 #define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */
\r
2060 #define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */
\r
2062 /* DMACTL0 Control Bits */
\r
2063 #define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */
\r
2064 #define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */
\r
2065 #define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */
\r
2066 #define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */
\r
2067 #define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */
\r
2068 #define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */
\r
2069 #define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */
\r
2070 #define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */
\r
2071 #define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */
\r
2072 #define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */
\r
2074 /* DMACTL0 Control Bits */
\r
2075 #define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */
\r
2076 #define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */
\r
2077 #define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */
\r
2078 #define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */
\r
2079 #define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */
\r
2081 /* DMACTL0 Control Bits */
\r
2082 #define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */
\r
2083 #define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */
\r
2084 #define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */
\r
2085 #define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */
\r
2086 #define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */
\r
2088 /* DMACTL01 Control Bits */
\r
2089 #define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */
\r
2090 #define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */
\r
2091 #define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */
\r
2092 #define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */
\r
2093 #define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */
\r
2095 /* DMACTL01 Control Bits */
\r
2096 #define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */
\r
2097 #define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */
\r
2098 #define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */
\r
2099 #define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */
\r
2100 #define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */
\r
2102 /* DMACTL4 Control Bits */
\r
2103 #define ENNMI (0x0001u) /* Enable NMI interruption of DMA */
\r
2104 #define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */
\r
2105 #define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
\r
2107 /* DMACTL4 Control Bits */
\r
2108 #define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */
\r
2109 #define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */
\r
2110 #define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
\r
2112 /* DMAxCTL Control Bits */
\r
2113 #define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */
\r
2114 #define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */
\r
2115 #define DMAIE (0x0004u) /* DMA interrupt enable */
\r
2116 #define DMAIFG (0x0008u) /* DMA interrupt flag */
\r
2117 #define DMAEN (0x0010u) /* DMA enable */
\r
2118 #define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */
\r
2119 #define DMASRCBYTE (0x0040u) /* DMA source byte */
\r
2120 #define DMADSTBYTE (0x0080u) /* DMA destination byte */
\r
2121 #define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */
\r
2122 #define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */
\r
2123 #define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */
\r
2124 #define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */
\r
2125 #define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */
\r
2126 #define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */
\r
2127 #define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */
\r
2129 /* DMAxCTL Control Bits */
\r
2130 #define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */
\r
2131 #define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */
\r
2132 #define DMAIE_L (0x0004u) /* DMA interrupt enable */
\r
2133 #define DMAIFG_L (0x0008u) /* DMA interrupt flag */
\r
2134 #define DMAEN_L (0x0010u) /* DMA enable */
\r
2135 #define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */
\r
2136 #define DMASRCBYTE_L (0x0040u) /* DMA source byte */
\r
2137 #define DMADSTBYTE_L (0x0080u) /* DMA destination byte */
\r
2139 /* DMAxCTL Control Bits */
\r
2140 #define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */
\r
2141 #define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */
\r
2142 #define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */
\r
2143 #define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */
\r
2144 #define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */
\r
2145 #define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */
\r
2146 #define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */
\r
2148 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
\r
2149 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
\r
2150 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
\r
2151 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
\r
2153 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
\r
2154 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
\r
2155 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
\r
2156 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
\r
2158 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
\r
2159 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
\r
2160 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
\r
2161 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
\r
2163 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
\r
2164 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
\r
2165 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
\r
2166 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
\r
2167 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
\r
2168 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
\r
2169 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
\r
2170 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
\r
2172 /* DMAIV Definitions */
\r
2173 #define DMAIV_NONE (0x0000u) /* No Interrupt pending */
\r
2174 #define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/
\r
2175 #define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/
\r
2176 #define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/
\r
2179 /************************************************************
\r
2180 * EXTENDED SCAN INTERFACE
\r
2181 ************************************************************/
\r
2182 #ifdef __MSP430_HAS_ESI__ /* Definition to show that Module is available */
\r
2184 #define OFS_ESIDEBUG1 (0x0000u) /* ESI debug register 1 */
\r
2185 #define OFS_ESIDEBUG1_L OFS_ESIDEBUG1
\r
2186 #define OFS_ESIDEBUG1_H OFS_ESIDEBUG1+1
\r
2187 #define OFS_ESIDEBUG2 (0x0002u) /* ESI debug register 2 */
\r
2188 #define OFS_ESIDEBUG2_L OFS_ESIDEBUG2
\r
2189 #define OFS_ESIDEBUG2_H OFS_ESIDEBUG2+1
\r
2190 #define OFS_ESIDEBUG3 (0x0004u) /* ESI debug register 3 */
\r
2191 #define OFS_ESIDEBUG3_L OFS_ESIDEBUG3
\r
2192 #define OFS_ESIDEBUG3_H OFS_ESIDEBUG3+1
\r
2193 #define OFS_ESIDEBUG4 (0x0006u) /* ESI debug register 4 */
\r
2194 #define OFS_ESIDEBUG4_L OFS_ESIDEBUG4
\r
2195 #define OFS_ESIDEBUG4_H OFS_ESIDEBUG4+1
\r
2196 #define OFS_ESIDEBUG5 (0x0008u) /* ESI debug register 5 */
\r
2197 #define OFS_ESIDEBUG5_L OFS_ESIDEBUG5
\r
2198 #define OFS_ESIDEBUG5_H OFS_ESIDEBUG5+1
\r
2199 #define OFS_ESICNT0 (0x0010u) /* ESI PSM counter 0 */
\r
2200 #define OFS_ESICNT0_L OFS_ESICNT0
\r
2201 #define OFS_ESICNT0_H OFS_ESICNT0+1
\r
2202 #define OFS_ESICNT1 (0x0012u) /* ESI PSM counter 1 */
\r
2203 #define OFS_ESICNT1_L OFS_ESICNT1
\r
2204 #define OFS_ESICNT1_H OFS_ESICNT1+1
\r
2205 #define OFS_ESICNT2 (0x0014u) /* ESI PSM counter 2 */
\r
2206 #define OFS_ESICNT2_L OFS_ESICNT2
\r
2207 #define OFS_ESICNT2_H OFS_ESICNT2+1
\r
2208 #define OFS_ESICNT3 (0x0016u) /* ESI oscillator counter register */
\r
2209 #define OFS_ESICNT3_L OFS_ESICNT3
\r
2210 #define OFS_ESICNT3_H OFS_ESICNT3+1
\r
2211 #define OFS_ESIIV (0x001Au) /* ESI interrupt vector */
\r
2212 #define OFS_ESIIV_L OFS_ESIIV
\r
2213 #define OFS_ESIIV_H OFS_ESIIV+1
\r
2214 #define OFS_ESIINT1 (0x001Cu) /* ESI interrupt register 1 */
\r
2215 #define OFS_ESIINT1_L OFS_ESIINT1
\r
2216 #define OFS_ESIINT1_H OFS_ESIINT1+1
\r
2217 #define OFS_ESIINT2 (0x001Eu) /* ESI interrupt register 2 */
\r
2218 #define OFS_ESIINT2_L OFS_ESIINT2
\r
2219 #define OFS_ESIINT2_H OFS_ESIINT2+1
\r
2220 #define OFS_ESIAFE (0x0020u) /* ESI AFE control register */
\r
2221 #define OFS_ESIAFE_L OFS_ESIAFE
\r
2222 #define OFS_ESIAFE_H OFS_ESIAFE+1
\r
2223 #define OFS_ESIPPU (0x0022u) /* ESI PPU control register */
\r
2224 #define OFS_ESIPPU_L OFS_ESIPPU
\r
2225 #define OFS_ESIPPU_H OFS_ESIPPU+1
\r
2226 #define OFS_ESITSM (0x0024u) /* ESI TSM control register */
\r
2227 #define OFS_ESITSM_L OFS_ESITSM
\r
2228 #define OFS_ESITSM_H OFS_ESITSM+1
\r
2229 #define OFS_ESIPSM (0x0026u) /* ESI PSM control register */
\r
2230 #define OFS_ESIPSM_L OFS_ESIPSM
\r
2231 #define OFS_ESIPSM_H OFS_ESIPSM+1
\r
2232 #define OFS_ESIOSC (0x0028u) /* ESI oscillator control register*/
\r
2233 #define OFS_ESIOSC_L OFS_ESIOSC
\r
2234 #define OFS_ESIOSC_H OFS_ESIOSC+1
\r
2235 #define OFS_ESICTL (0x002Au) /* ESI control register */
\r
2236 #define OFS_ESICTL_L OFS_ESICTL
\r
2237 #define OFS_ESICTL_H OFS_ESICTL+1
\r
2238 #define OFS_ESITHR1 (0x002Cu) /* ESI PSM Counter Threshold 1 register */
\r
2239 #define OFS_ESITHR1_L OFS_ESITHR1
\r
2240 #define OFS_ESITHR1_H OFS_ESITHR1+1
\r
2241 #define OFS_ESITHR2 (0x002Eu) /* ESI PSM Counter Threshold 2 register */
\r
2242 #define OFS_ESITHR2_L OFS_ESITHR2
\r
2243 #define OFS_ESITHR2_H OFS_ESITHR2+1
\r
2244 #define OFS_ESIDAC1R0 (0x0040u) /* ESI DAC1 register 0 */
\r
2245 #define OFS_ESIDAC1R0_L OFS_ESIDAC1R0
\r
2246 #define OFS_ESIDAC1R0_H OFS_ESIDAC1R0+1
\r
2247 #define OFS_ESIDAC1R1 (0x0042u) /* ESI DAC1 register 1 */
\r
2248 #define OFS_ESIDAC1R1_L OFS_ESIDAC1R1
\r
2249 #define OFS_ESIDAC1R1_H OFS_ESIDAC1R1+1
\r
2250 #define OFS_ESIDAC1R2 (0x0044u) /* ESI DAC1 register 2 */
\r
2251 #define OFS_ESIDAC1R2_L OFS_ESIDAC1R2
\r
2252 #define OFS_ESIDAC1R2_H OFS_ESIDAC1R2+1
\r
2253 #define OFS_ESIDAC1R3 (0x0046u) /* ESI DAC1 register 3 */
\r
2254 #define OFS_ESIDAC1R3_L OFS_ESIDAC1R3
\r
2255 #define OFS_ESIDAC1R3_H OFS_ESIDAC1R3+1
\r
2256 #define OFS_ESIDAC1R4 (0x0048u) /* ESI DAC1 register 4 */
\r
2257 #define OFS_ESIDAC1R4_L OFS_ESIDAC1R4
\r
2258 #define OFS_ESIDAC1R4_H OFS_ESIDAC1R4+1
\r
2259 #define OFS_ESIDAC1R5 (0x004Au) /* ESI DAC1 register 5 */
\r
2260 #define OFS_ESIDAC1R5_L OFS_ESIDAC1R5
\r
2261 #define OFS_ESIDAC1R5_H OFS_ESIDAC1R5+1
\r
2262 #define OFS_ESIDAC1R6 (0x004Cu) /* ESI DAC1 register 6 */
\r
2263 #define OFS_ESIDAC1R6_L OFS_ESIDAC1R6
\r
2264 #define OFS_ESIDAC1R6_H OFS_ESIDAC1R6+1
\r
2265 #define OFS_ESIDAC1R7 (0x004Eu) /* ESI DAC1 register 7 */
\r
2266 #define OFS_ESIDAC1R7_L OFS_ESIDAC1R7
\r
2267 #define OFS_ESIDAC1R7_H OFS_ESIDAC1R7+1
\r
2268 #define OFS_ESIDAC2R0 (0x0050u) /* ESI DAC2 register 0 */
\r
2269 #define OFS_ESIDAC2R0_L OFS_ESIDAC2R0
\r
2270 #define OFS_ESIDAC2R0_H OFS_ESIDAC2R0+1
\r
2271 #define OFS_ESIDAC2R1 (0x0052u) /* ESI DAC2 register 1 */
\r
2272 #define OFS_ESIDAC2R1_L OFS_ESIDAC2R1
\r
2273 #define OFS_ESIDAC2R1_H OFS_ESIDAC2R1+1
\r
2274 #define OFS_ESIDAC2R2 (0x0054u) /* ESI DAC2 register 2 */
\r
2275 #define OFS_ESIDAC2R2_L OFS_ESIDAC2R2
\r
2276 #define OFS_ESIDAC2R2_H OFS_ESIDAC2R2+1
\r
2277 #define OFS_ESIDAC2R3 (0x0056u) /* ESI DAC2 register 3 */
\r
2278 #define OFS_ESIDAC2R3_L OFS_ESIDAC2R3
\r
2279 #define OFS_ESIDAC2R3_H OFS_ESIDAC2R3+1
\r
2280 #define OFS_ESIDAC2R4 (0x0058u) /* ESI DAC2 register 4 */
\r
2281 #define OFS_ESIDAC2R4_L OFS_ESIDAC2R4
\r
2282 #define OFS_ESIDAC2R4_H OFS_ESIDAC2R4+1
\r
2283 #define OFS_ESIDAC2R5 (0x005Au) /* ESI DAC2 register 5 */
\r
2284 #define OFS_ESIDAC2R5_L OFS_ESIDAC2R5
\r
2285 #define OFS_ESIDAC2R5_H OFS_ESIDAC2R5+1
\r
2286 #define OFS_ESIDAC2R6 (0x005Cu) /* ESI DAC2 register 6 */
\r
2287 #define OFS_ESIDAC2R6_L OFS_ESIDAC2R6
\r
2288 #define OFS_ESIDAC2R6_H OFS_ESIDAC2R6+1
\r
2289 #define OFS_ESIDAC2R7 (0x005Eu) /* ESI DAC2 register 7 */
\r
2290 #define OFS_ESIDAC2R7_L OFS_ESIDAC2R7
\r
2291 #define OFS_ESIDAC2R7_H OFS_ESIDAC2R7+1
\r
2292 #define OFS_ESITSM0 (0x0060u) /* ESI TSM 0 */
\r
2293 #define OFS_ESITSM0_L OFS_ESITSM0
\r
2294 #define OFS_ESITSM0_H OFS_ESITSM0+1
\r
2295 #define OFS_ESITSM1 (0x0062u) /* ESI TSM 1 */
\r
2296 #define OFS_ESITSM1_L OFS_ESITSM1
\r
2297 #define OFS_ESITSM1_H OFS_ESITSM1+1
\r
2298 #define OFS_ESITSM2 (0x0064u) /* ESI TSM 2 */
\r
2299 #define OFS_ESITSM2_L OFS_ESITSM2
\r
2300 #define OFS_ESITSM2_H OFS_ESITSM2+1
\r
2301 #define OFS_ESITSM3 (0x0066u) /* ESI TSM 3 */
\r
2302 #define OFS_ESITSM3_L OFS_ESITSM3
\r
2303 #define OFS_ESITSM3_H OFS_ESITSM3+1
\r
2304 #define OFS_ESITSM4 (0x0068u) /* ESI TSM 4 */
\r
2305 #define OFS_ESITSM4_L OFS_ESITSM4
\r
2306 #define OFS_ESITSM4_H OFS_ESITSM4+1
\r
2307 #define OFS_ESITSM5 (0x006Au) /* ESI TSM 5 */
\r
2308 #define OFS_ESITSM5_L OFS_ESITSM5
\r
2309 #define OFS_ESITSM5_H OFS_ESITSM5+1
\r
2310 #define OFS_ESITSM6 (0x006Cu) /* ESI TSM 6 */
\r
2311 #define OFS_ESITSM6_L OFS_ESITSM6
\r
2312 #define OFS_ESITSM6_H OFS_ESITSM6+1
\r
2313 #define OFS_ESITSM7 (0x006Eu) /* ESI TSM 7 */
\r
2314 #define OFS_ESITSM7_L OFS_ESITSM7
\r
2315 #define OFS_ESITSM7_H OFS_ESITSM7+1
\r
2316 #define OFS_ESITSM8 (0x0070u) /* ESI TSM 8 */
\r
2317 #define OFS_ESITSM8_L OFS_ESITSM8
\r
2318 #define OFS_ESITSM8_H OFS_ESITSM8+1
\r
2319 #define OFS_ESITSM9 (0x0072u) /* ESI TSM 9 */
\r
2320 #define OFS_ESITSM9_L OFS_ESITSM9
\r
2321 #define OFS_ESITSM9_H OFS_ESITSM9+1
\r
2322 #define OFS_ESITSM10 (0x0074u) /* ESI TSM 10 */
\r
2323 #define OFS_ESITSM10_L OFS_ESITSM10
\r
2324 #define OFS_ESITSM10_H OFS_ESITSM10+1
\r
2325 #define OFS_ESITSM11 (0x0076u) /* ESI TSM 11 */
\r
2326 #define OFS_ESITSM11_L OFS_ESITSM11
\r
2327 #define OFS_ESITSM11_H OFS_ESITSM11+1
\r
2328 #define OFS_ESITSM12 (0x0078u) /* ESI TSM 12 */
\r
2329 #define OFS_ESITSM12_L OFS_ESITSM12
\r
2330 #define OFS_ESITSM12_H OFS_ESITSM12+1
\r
2331 #define OFS_ESITSM13 (0x007Au) /* ESI TSM 13 */
\r
2332 #define OFS_ESITSM13_L OFS_ESITSM13
\r
2333 #define OFS_ESITSM13_H OFS_ESITSM13+1
\r
2334 #define OFS_ESITSM14 (0x007Cu) /* ESI TSM 14 */
\r
2335 #define OFS_ESITSM14_L OFS_ESITSM14
\r
2336 #define OFS_ESITSM14_H OFS_ESITSM14+1
\r
2337 #define OFS_ESITSM15 (0x007Eu) /* ESI TSM 15 */
\r
2338 #define OFS_ESITSM15_L OFS_ESITSM15
\r
2339 #define OFS_ESITSM15_H OFS_ESITSM15+1
\r
2340 #define OFS_ESITSM16 (0x0080u) /* ESI TSM 16 */
\r
2341 #define OFS_ESITSM16_L OFS_ESITSM16
\r
2342 #define OFS_ESITSM16_H OFS_ESITSM16+1
\r
2343 #define OFS_ESITSM17 (0x0082u) /* ESI TSM 17 */
\r
2344 #define OFS_ESITSM17_L OFS_ESITSM17
\r
2345 #define OFS_ESITSM17_H OFS_ESITSM17+1
\r
2346 #define OFS_ESITSM18 (0x0084u) /* ESI TSM 18 */
\r
2347 #define OFS_ESITSM18_L OFS_ESITSM18
\r
2348 #define OFS_ESITSM18_H OFS_ESITSM18+1
\r
2349 #define OFS_ESITSM19 (0x0086u) /* ESI TSM 19 */
\r
2350 #define OFS_ESITSM19_L OFS_ESITSM19
\r
2351 #define OFS_ESITSM19_H OFS_ESITSM19+1
\r
2352 #define OFS_ESITSM20 (0x0088u) /* ESI TSM 20 */
\r
2353 #define OFS_ESITSM20_L OFS_ESITSM20
\r
2354 #define OFS_ESITSM20_H OFS_ESITSM20+1
\r
2355 #define OFS_ESITSM21 (0x008Au) /* ESI TSM 21 */
\r
2356 #define OFS_ESITSM21_L OFS_ESITSM21
\r
2357 #define OFS_ESITSM21_H OFS_ESITSM21+1
\r
2358 #define OFS_ESITSM22 (0x008Cu) /* ESI TSM 22 */
\r
2359 #define OFS_ESITSM22_L OFS_ESITSM22
\r
2360 #define OFS_ESITSM22_H OFS_ESITSM22+1
\r
2361 #define OFS_ESITSM23 (0x008Eu) /* ESI TSM 23 */
\r
2362 #define OFS_ESITSM23_L OFS_ESITSM23
\r
2363 #define OFS_ESITSM23_H OFS_ESITSM23+1
\r
2364 #define OFS_ESITSM24 (0x0090u) /* ESI TSM 24 */
\r
2365 #define OFS_ESITSM24_L OFS_ESITSM24
\r
2366 #define OFS_ESITSM24_H OFS_ESITSM24+1
\r
2367 #define OFS_ESITSM25 (0x0092u) /* ESI TSM 25 */
\r
2368 #define OFS_ESITSM25_L OFS_ESITSM25
\r
2369 #define OFS_ESITSM25_H OFS_ESITSM25+1
\r
2370 #define OFS_ESITSM26 (0x0094u) /* ESI TSM 26 */
\r
2371 #define OFS_ESITSM26_L OFS_ESITSM26
\r
2372 #define OFS_ESITSM26_H OFS_ESITSM26+1
\r
2373 #define OFS_ESITSM27 (0x0096u) /* ESI TSM 27 */
\r
2374 #define OFS_ESITSM27_L OFS_ESITSM27
\r
2375 #define OFS_ESITSM27_H OFS_ESITSM27+1
\r
2376 #define OFS_ESITSM28 (0x0098u) /* ESI TSM 28 */
\r
2377 #define OFS_ESITSM28_L OFS_ESITSM28
\r
2378 #define OFS_ESITSM28_H OFS_ESITSM28+1
\r
2379 #define OFS_ESITSM29 (0x009Au) /* ESI TSM 29 */
\r
2380 #define OFS_ESITSM29_L OFS_ESITSM29
\r
2381 #define OFS_ESITSM29_H OFS_ESITSM29+1
\r
2382 #define OFS_ESITSM30 (0x009Cu) /* ESI TSM 30 */
\r
2383 #define OFS_ESITSM30_L OFS_ESITSM30
\r
2384 #define OFS_ESITSM30_H OFS_ESITSM30+1
\r
2385 #define OFS_ESITSM31 (0x009Eu) /* ESI TSM 31 */
\r
2386 #define OFS_ESITSM31_L OFS_ESITSM31
\r
2387 #define OFS_ESITSM31_H OFS_ESITSM31+1
\r
2389 /* ESIIV Control Bits */
\r
2391 #define ESIIV_NONE (0x0000u) /* No ESI Interrupt Pending */
\r
2392 #define ESIIV_ESIIFG1 (0x0002u) /* rising edge of the ESISTOP(tsm) */
\r
2393 #define ESIIV_ESIIFG0 (0x0004u) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */
\r
2394 #define ESIIV_ESIIFG8 (0x0006u) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */
\r
2395 #define ESIIV_ESIIFG3 (0x0008u) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */
\r
2396 #define ESIIV_ESIIFG6 (0x000Au) /* PSM transitions to a state with a Q7 bit */
\r
2397 #define ESIIV_ESIIFG5 (0x000Cu) /* PSM transitions to a state with a Q6 bit */
\r
2398 #define ESIIV_ESIIFG4 (0x000Eu) /* ESICNT2 counter conditions selected with the ESIIS2x bits */
\r
2399 #define ESIIV_ESIIFG7 (0x0010u) /* ESICNT0 counter conditions selected with the ESIIS0x bits */
\r
2400 #define ESIIV_ESIIFG2 (0x0012u) /* start of a TSM sequence */
\r
2402 /* ESIINT1 Control Bits */
\r
2403 #define ESIIFGSET22 (0x8000u) /* ESIIFG8 interrupt flag source */
\r
2404 #define ESIIFGSET21 (0x4000u) /* ESIIFG8 interrupt flag source */
\r
2405 #define ESIIFGSET20 (0x2000u) /* ESIIFG8 interrupt flag source */
\r
2406 #define ESIIFGSET12 (0x1000u) /* ESIIFG0 interrupt flag source */
\r
2407 #define ESIIFGSET11 (0x0800u) /* ESIIFG0 interrupt flag source */
\r
2408 #define ESIIFGSET10 (0x0400u) /* ESIIFG0 interrupt flag source */
\r
2409 #define ESIIE8 (0x0100u) /* Interrupt enable */
\r
2410 #define ESIIE7 (0x0080u) /* Interrupt enable */
\r
2411 #define ESIIE6 (0x0040u) /* Interrupt enable */
\r
2412 #define ESIIE5 (0x0020u) /* Interrupt enable */
\r
2413 #define ESIIE4 (0x0010u) /* Interrupt enable */
\r
2414 #define ESIIE3 (0x0008u) /* Interrupt enable */
\r
2415 #define ESIIE2 (0x0004u) /* Interrupt enable */
\r
2416 #define ESIIE1 (0x0002u) /* Interrupt enable */
\r
2417 #define ESIIE0 (0x0001u) /* Interrupt enable */
\r
2419 /* ESIINT1 Control Bits */
\r
2420 #define ESIIE7_L (0x0080u) /* Interrupt enable */
\r
2421 #define ESIIE6_L (0x0040u) /* Interrupt enable */
\r
2422 #define ESIIE5_L (0x0020u) /* Interrupt enable */
\r
2423 #define ESIIE4_L (0x0010u) /* Interrupt enable */
\r
2424 #define ESIIE3_L (0x0008u) /* Interrupt enable */
\r
2425 #define ESIIE2_L (0x0004u) /* Interrupt enable */
\r
2426 #define ESIIE1_L (0x0002u) /* Interrupt enable */
\r
2427 #define ESIIE0_L (0x0001u) /* Interrupt enable */
\r
2429 /* ESIINT1 Control Bits */
\r
2430 #define ESIIFGSET22_H (0x0080u) /* ESIIFG8 interrupt flag source */
\r
2431 #define ESIIFGSET21_H (0x0040u) /* ESIIFG8 interrupt flag source */
\r
2432 #define ESIIFGSET20_H (0x0020u) /* ESIIFG8 interrupt flag source */
\r
2433 #define ESIIFGSET12_H (0x0010u) /* ESIIFG0 interrupt flag source */
\r
2434 #define ESIIFGSET11_H (0x0008u) /* ESIIFG0 interrupt flag source */
\r
2435 #define ESIIFGSET10_H (0x0004u) /* ESIIFG0 interrupt flag source */
\r
2436 #define ESIIE8_H (0x0001u) /* Interrupt enable */
\r
2438 #define ESIIFGSET2_0 (0x0000u) /* ESIIFG8 is set when ESIOUT4 is set */
\r
2439 #define ESIIFGSET2_1 (0x2000u) /* ESIIFG8 is set when ESIOUT4 is reset */
\r
2440 #define ESIIFGSET2_2 (0x4000u) /* ESIIFG8 is set when ESIOUT5 is set */
\r
2441 #define ESIIFGSET2_3 (0x6000u) /* ESIIFG8 is set when ESIOUT5 is reset */
\r
2442 #define ESIIFGSET2_4 (0x8000u) /* ESIIFG8 is set when ESIOUT6 is set */
\r
2443 #define ESIIFGSET2_5 (0xA000u) /* ESIIFG8 is set when ESIOUT6 is reset */
\r
2444 #define ESIIFGSET2_6 (0xC000u) /* ESIIFG8 is set when ESIOUT7 is set */
\r
2445 #define ESIIFGSET2_7 (0xE000u) /* ESIIFG8 is set when ESIOUT7 is reset */
\r
2446 #define ESIIFGSET1_0 (0x0000u) /* ESIIFG0 is set when ESIOUT0 is set */
\r
2447 #define ESIIFGSET1_1 (0x0400u) /* ESIIFG0 is set when ESIOUT0 is reset */
\r
2448 #define ESIIFGSET1_2 (0x0800u) /* ESIIFG0 is set when ESIOUT1 is set */
\r
2449 #define ESIIFGSET1_3 (0x0C00u) /* ESIIFG0 is set when ESIOUT1 is reset */
\r
2450 #define ESIIFGSET1_4 (0x1000u) /* ESIIFG0 is set when ESIOUT2 is set */
\r
2451 #define ESIIFGSET1_5 (0x1400u) /* ESIIFG0 is set when ESIOUT2 is reset */
\r
2452 #define ESIIFGSET1_6 (0x1800u) /* ESIIFG0 is set when ESIOUT3 is set */
\r
2453 #define ESIIFGSET1_7 (0x1C00u) /* ESIIFG0 is set when ESIOUT3 is reset */
\r
2455 /* ESIINT2 Control Bits */
\r
2456 #define ESIIS21 (0x4000u) /* SIFIFG4 interrupt flag source */
\r
2457 #define ESIIS20 (0x2000u) /* SIFIFG4 interrupt flag source */
\r
2458 #define ESIIS01 (0x0800u) /* SIFIFG7 interrupt flag source */
\r
2459 #define ESIIS00 (0x0400u) /* SIFIFG7 interrupt flag source */
\r
2460 #define ESIIFG8 (0x0100u) /* ESIIFG8 interrupt pending */
\r
2461 #define ESIIFG7 (0x0080u) /* ESIIFG7 interrupt pending */
\r
2462 #define ESIIFG6 (0x0040u) /* ESIIFG6 interrupt pending */
\r
2463 #define ESIIFG5 (0x0020u) /* ESIIFG5 interrupt pending */
\r
2464 #define ESIIFG4 (0x0010u) /* ESIIFG4 interrupt pending */
\r
2465 #define ESIIFG3 (0x0008u) /* ESIIFG3 interrupt pending */
\r
2466 #define ESIIFG2 (0x0004u) /* ESIIFG2 interrupt pending */
\r
2467 #define ESIIFG1 (0x0002u) /* ESIIFG1 interrupt pending */
\r
2468 #define ESIIFG0 (0x0001u) /* ESIIFG0 interrupt pending */
\r
2470 /* ESIINT2 Control Bits */
\r
2471 #define ESIIFG7_L (0x0080u) /* ESIIFG7 interrupt pending */
\r
2472 #define ESIIFG6_L (0x0040u) /* ESIIFG6 interrupt pending */
\r
2473 #define ESIIFG5_L (0x0020u) /* ESIIFG5 interrupt pending */
\r
2474 #define ESIIFG4_L (0x0010u) /* ESIIFG4 interrupt pending */
\r
2475 #define ESIIFG3_L (0x0008u) /* ESIIFG3 interrupt pending */
\r
2476 #define ESIIFG2_L (0x0004u) /* ESIIFG2 interrupt pending */
\r
2477 #define ESIIFG1_L (0x0002u) /* ESIIFG1 interrupt pending */
\r
2478 #define ESIIFG0_L (0x0001u) /* ESIIFG0 interrupt pending */
\r
2480 /* ESIINT2 Control Bits */
\r
2481 #define ESIIS21_H (0x0040u) /* SIFIFG4 interrupt flag source */
\r
2482 #define ESIIS20_H (0x0020u) /* SIFIFG4 interrupt flag source */
\r
2483 #define ESIIS01_H (0x0008u) /* SIFIFG7 interrupt flag source */
\r
2484 #define ESIIS00_H (0x0004u) /* SIFIFG7 interrupt flag source */
\r
2485 #define ESIIFG8_H (0x0001u) /* ESIIFG8 interrupt pending */
\r
2487 #define ESIIS2_0 (0x0000u) /* SIFIFG4 interrupt flag source: SIFCNT2 */
\r
2488 #define ESIIS2_1 (0x2000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */
\r
2489 #define ESIIS2_2 (0x4000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */
\r
2490 #define ESIIS2_3 (0x6000u) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */
\r
2491 #define ESIIS0_0 (0x0000u) /* SIFIFG7 interrupt flag source: SIFCNT0 */
\r
2492 #define ESIIS0_1 (0x0400u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */
\r
2493 #define ESIIS0_2 (0x0800u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */
\r
2494 #define ESIIS0_3 (0x0C00u) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */
\r
2496 /* ESIAFE Control Bits */
\r
2497 #define ESIDAC2EN (0x0800u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */
\r
2498 #define ESICA2EN (0x0400u) /* Enable ESICA(tsm) control for comparator in AFE2 */
\r
2499 #define ESICA2INV (0x0200u) /* Invert AFE2's comparator output */
\r
2500 #define ESICA1INV (0x0100u) /* Invert AFE1's comparator output */
\r
2501 #define ESICA2X (0x0080u) /* AFE2's comparator input select */
\r
2502 #define ESICA1X (0x0040u) /* AFE1's comparator input select */
\r
2503 #define ESICISEL (0x0020u) /* Comparator input select for AFE1 only */
\r
2504 #define ESICACI3 (0x0010u) /* Comparator input select for AFE1 only */
\r
2505 #define ESIVSS (0x0008u) /* Sample-and-hold ESIVSS select */
\r
2506 #define ESIVCC2 (0x0004u) /* Mid-voltage generator */
\r
2507 #define ESISH (0x0002u) /* Sample-and-hold enable */
\r
2508 #define ESITEN (0x0001u) /* Excitation enable */
\r
2510 /* ESIAFE Control Bits */
\r
2511 #define ESICA2X_L (0x0080u) /* AFE2's comparator input select */
\r
2512 #define ESICA1X_L (0x0040u) /* AFE1's comparator input select */
\r
2513 #define ESICISEL_L (0x0020u) /* Comparator input select for AFE1 only */
\r
2514 #define ESICACI3_L (0x0010u) /* Comparator input select for AFE1 only */
\r
2515 #define ESIVSS_L (0x0008u) /* Sample-and-hold ESIVSS select */
\r
2516 #define ESIVCC2_L (0x0004u) /* Mid-voltage generator */
\r
2517 #define ESISH_L (0x0002u) /* Sample-and-hold enable */
\r
2518 #define ESITEN_L (0x0001u) /* Excitation enable */
\r
2520 /* ESIAFE Control Bits */
\r
2521 #define ESIDAC2EN_H (0x0008u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */
\r
2522 #define ESICA2EN_H (0x0004u) /* Enable ESICA(tsm) control for comparator in AFE2 */
\r
2523 #define ESICA2INV_H (0x0002u) /* Invert AFE2's comparator output */
\r
2524 #define ESICA1INV_H (0x0001u) /* Invert AFE1's comparator output */
\r
2526 /* ESIPPU Control Bits */
\r
2527 #define ESITCHOUT1 (0x0200u) /* Latched AFE1 comparator output for test channel 1 */
\r
2528 #define ESITCHOUT0 (0x0100u) /* Lachted AFE1 comparator output for test channel 0 */
\r
2529 #define ESIOUT7 (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */
\r
2530 #define ESIOUT6 (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */
\r
2531 #define ESIOUT5 (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */
\r
2532 #define ESIOUT4 (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */
\r
2533 #define ESIOUT3 (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */
\r
2534 #define ESIOUT2 (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */
\r
2535 #define ESIOUT1 (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */
\r
2536 #define ESIOUT0 (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */
\r
2538 /* ESIPPU Control Bits */
\r
2539 #define ESIOUT7_L (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */
\r
2540 #define ESIOUT6_L (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */
\r
2541 #define ESIOUT5_L (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */
\r
2542 #define ESIOUT4_L (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */
\r
2543 #define ESIOUT3_L (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */
\r
2544 #define ESIOUT2_L (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */
\r
2545 #define ESIOUT1_L (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */
\r
2546 #define ESIOUT0_L (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */
\r
2548 /* ESIPPU Control Bits */
\r
2549 #define ESITCHOUT1_H (0x0002u) /* Latched AFE1 comparator output for test channel 1 */
\r
2550 #define ESITCHOUT0_H (0x0001u) /* Lachted AFE1 comparator output for test channel 0 */
\r
2552 /* ESITSM Control Bits */
\r
2553 #define ESICLKAZSEL (0x4000u) /* Functionality selection of ESITSMx bit5 */
\r
2554 #define ESITSMTRG1 (0x2000u) /* TSM start trigger selection */
\r
2555 #define ESITSMTRG0 (0x1000u) /* TSM start trigger selection */
\r
2556 #define ESISTART (0x0800u) /* TSM software start trigger */
\r
2557 #define ESITSMRP (0x0400u) /* TSM repeat modee */
\r
2558 #define ESIDIV3B2 (0x0200u) /* TSM start trigger ACLK divider */
\r
2559 #define ESIDIV3B1 (0x0100u) /* TSM start trigger ACLK divider */
\r
2560 #define ESIDIV3B0 (0x0080u) /* TSM start trigger ACLK divider */
\r
2561 #define ESIDIV3A2 (0x0040u) /* TSM start trigger ACLK divider */
\r
2562 #define ESIDIV3A1 (0x0020u) /* TSM start trigger ACLK divider */
\r
2563 #define ESIDIV3A0 (0x0010u) /* TSM start trigger ACLK divider */
\r
2564 #define ESIDIV21 (0x0008u) /* ACLK divider */
\r
2565 #define ESIDIV20 (0x0004u) /* ACLK divider */
\r
2566 #define ESIDIV11 (0x0002u) /* TSM SMCLK divider */
\r
2567 #define ESIDIV10 (0x0001u) /* TSM SMCLK divider */
\r
2569 /* ESITSM Control Bits */
\r
2570 #define ESIDIV3B0_L (0x0080u) /* TSM start trigger ACLK divider */
\r
2571 #define ESIDIV3A2_L (0x0040u) /* TSM start trigger ACLK divider */
\r
2572 #define ESIDIV3A1_L (0x0020u) /* TSM start trigger ACLK divider */
\r
2573 #define ESIDIV3A0_L (0x0010u) /* TSM start trigger ACLK divider */
\r
2574 #define ESIDIV21_L (0x0008u) /* ACLK divider */
\r
2575 #define ESIDIV20_L (0x0004u) /* ACLK divider */
\r
2576 #define ESIDIV11_L (0x0002u) /* TSM SMCLK divider */
\r
2577 #define ESIDIV10_L (0x0001u) /* TSM SMCLK divider */
\r
2579 /* ESITSM Control Bits */
\r
2580 #define ESICLKAZSEL_H (0x0040u) /* Functionality selection of ESITSMx bit5 */
\r
2581 #define ESITSMTRG1_H (0x0020u) /* TSM start trigger selection */
\r
2582 #define ESITSMTRG0_H (0x0010u) /* TSM start trigger selection */
\r
2583 #define ESISTART_H (0x0008u) /* TSM software start trigger */
\r
2584 #define ESITSMRP_H (0x0004u) /* TSM repeat modee */
\r
2585 #define ESIDIV3B2_H (0x0002u) /* TSM start trigger ACLK divider */
\r
2586 #define ESIDIV3B1_H (0x0001u) /* TSM start trigger ACLK divider */
\r
2588 #define ESITSMTRG_0 (0x0000u) /* Halt mode */
\r
2589 #define ESITSMTRG_1 (0x1000u) /* TSM start trigger ACLK divider */
\r
2590 #define ESITSMTRG_2 (0x2000u) /* Software trigger for TSM */
\r
2591 #define ESITSMTRG_3 (0x3000u) /* Either the ACLK divider or the ESISTART biT */
\r
2592 #define ESIDIV3B_0 (0x0000u) /* TSM start trigger ACLK divider */
\r
2593 #define ESIDIV3B_1 (0x0080u) /* TSM start trigger ACLK divider */
\r
2594 #define ESIDIV3B_2 (0x0100u) /* TSM start trigger ACLK divider */
\r
2595 #define ESIDIV3B_3 (0x0180u) /* TSM start trigger ACLK divider */
\r
2596 #define ESIDIV3B_4 (0x0200u) /* TSM start trigger ACLK divider */
\r
2597 #define ESIDIV3B_5 (0x0280u) /* TSM start trigger ACLK divider */
\r
2598 #define ESIDIV3B_6 (0x0300u) /* TSM start trigger ACLK divider */
\r
2599 #define ESIDIV3B_7 (0x0380u) /* TSM start trigger ACLK divider */
\r
2600 #define ESIDIV3A_0 (0x0000u) /* TSM start trigger ACLK divider */
\r
2601 #define ESIDIV3A_1 (0x0010u) /* TSM start trigger ACLK divider */
\r
2602 #define ESIDIV3A_2 (0x0020u) /* TSM start trigger ACLK divider */
\r
2603 #define ESIDIV3A_3 (0x0030u) /* TSM start trigger ACLK divider */
\r
2604 #define ESIDIV3A_4 (0x0040u) /* TSM start trigger ACLK divider */
\r
2605 #define ESIDIV3A_5 (0x0050u) /* TSM start trigger ACLK divider */
\r
2606 #define ESIDIV3A_6 (0x0060u) /* TSM start trigger ACLK divider */
\r
2607 #define ESIDIV3A_7 (0x0070u) /* TSM start trigger ACLK divider */
\r
2608 #define ESIDIV2_0 (0x0000u) /* ACLK divider mode: 0 */
\r
2609 #define ESIDIV2_1 (0x0004u) /* ACLK divider mode: 1 */
\r
2610 #define ESIDIV2_2 (0x0008u) /* ACLK divider mode: 2 */
\r
2611 #define ESIDIV2_3 (0x000Cu) /* ACLK divider mode: 3 */
\r
2612 #define ESIDIV2__1 (0x0000u) /* ACLK divider = /1 */
\r
2613 #define ESIDIV2__2 (0x0004u) /* ACLK divider = /2 */
\r
2614 #define ESIDIV2__4 (0x0008u) /* ACLK divider = /4 */
\r
2615 #define ESIDIV2__8 (0x000Cu) /* ACLK divider = /8 */
\r
2616 #define ESIDIV1_0 (0x0000u) /* TSM SMCLK/ESIOSC divider mode: 0 */
\r
2617 #define ESIDIV1_1 (0x0001u) /* TSM SMCLK/ESIOSC divider mode: 1 */
\r
2618 #define ESIDIV1_2 (0x0002u) /* TSM SMCLK/ESIOSC divider mode: 2 */
\r
2619 #define ESIDIV1_3 (0x0003u) /* TSM SMCLK/ESIOSC divider mode: 3 */
\r
2620 #define ESIDIV1__1 (0x0000u) /* TSM SMCLK/ESIOSC divider = /1 */
\r
2621 #define ESIDIV1__2 (0x0001u) /* TSM SMCLK/ESIOSC divider = /2 */
\r
2622 #define ESIDIV1__4 (0x0002u) /* TSM SMCLK/ESIOSC divider = /4 */
\r
2623 #define ESIDIV1__8 (0x0003u) /* TSM SMCLK/ESIOSC divider = /8 */
\r
2625 /* ESIPSM Control Bits */
\r
2626 #define ESICNT2RST (0x8000u) /* ESI Counter 2 reset */
\r
2627 #define ESICNT1RST (0x4000u) /* ESI Counter 1 reset */
\r
2628 #define ESICNT0RST (0x2000u) /* ESI Counter 0 reset */
\r
2629 #define ESITEST4SEL1 (0x0200u) /* Output signal selection for SIFTEST4 pin */
\r
2630 #define ESITEST4SEL0 (0x0100u) /* Output signal selection for SIFTEST4 pin */
\r
2631 #define ESIV2SEL (0x0080u) /* Source Selection for V2 bit*/
\r
2632 #define ESICNT2EN (0x0020u) /* ESICNT2 enable (down counter) */
\r
2633 #define ESICNT1EN (0x0010u) /* ESICNT1 enable (up/down counter) */
\r
2634 #define ESICNT0EN (0x0008u) /* ESICNT0 enable (up counter) */
\r
2635 #define ESIQ7TRG (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */
\r
2636 #define ESIQ6EN (0x0001u) /* Q6 enable */
\r
2638 /* ESIPSM Control Bits */
\r
2639 #define ESIV2SEL_L (0x0080u) /* Source Selection for V2 bit*/
\r
2640 #define ESICNT2EN_L (0x0020u) /* ESICNT2 enable (down counter) */
\r
2641 #define ESICNT1EN_L (0x0010u) /* ESICNT1 enable (up/down counter) */
\r
2642 #define ESICNT0EN_L (0x0008u) /* ESICNT0 enable (up counter) */
\r
2643 #define ESIQ7TRG_L (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */
\r
2644 #define ESIQ6EN_L (0x0001u) /* Q6 enable */
\r
2646 /* ESIPSM Control Bits */
\r
2647 #define ESICNT2RST_H (0x0080u) /* ESI Counter 2 reset */
\r
2648 #define ESICNT1RST_H (0x0040u) /* ESI Counter 1 reset */
\r
2649 #define ESICNT0RST_H (0x0020u) /* ESI Counter 0 reset */
\r
2650 #define ESITEST4SEL1_H (0x0002u) /* Output signal selection for SIFTEST4 pin */
\r
2651 #define ESITEST4SEL0_H (0x0001u) /* Output signal selection for SIFTEST4 pin */
\r
2653 #define ESITEST4SEL_0 (0x0000u) /* Q1 signal from PSM table */
\r
2654 #define ESITEST4SEL_1 (0x0100u) /* Q2 signal from PSM table */
\r
2655 #define ESITEST4SEL_2 (0x0200u) /* TSM clock signal from Timing State Machine */
\r
2656 #define ESITEST4SEL_3 (0x0300u) /* AFE1's comparator output signal Comp1Out */
\r
2658 /* ESIOSC Control Bits */
\r
2659 #define ESICLKFQ5 (0x2000u) /* Internal oscillator frequency adjust */
\r
2660 #define ESICLKFQ4 (0x1000u) /* Internal oscillator frequency adjust */
\r
2661 #define ESICLKFQ3 (0x0800u) /* Internal oscillator frequency adjust */
\r
2662 #define ESICLKFQ2 (0x0400u) /* Internal oscillator frequency adjust */
\r
2663 #define ESICLKFQ1 (0x0200u) /* Internal oscillator frequency adjust */
\r
2664 #define ESICLKFQ0 (0x0100u) /* Internal oscillator frequency adjust */
\r
2665 #define ESICLKGON (0x0002u) /* Internal oscillator control */
\r
2666 #define ESIHFSEL (0x0001u) /* Internal oscillator enable */
\r
2668 /* ESIOSC Control Bits */
\r
2669 #define ESICLKGON_L (0x0002u) /* Internal oscillator control */
\r
2670 #define ESIHFSEL_L (0x0001u) /* Internal oscillator enable */
\r
2672 /* ESIOSC Control Bits */
\r
2673 #define ESICLKFQ5_H (0x0020u) /* Internal oscillator frequency adjust */
\r
2674 #define ESICLKFQ4_H (0x0010u) /* Internal oscillator frequency adjust */
\r
2675 #define ESICLKFQ3_H (0x0008u) /* Internal oscillator frequency adjust */
\r
2676 #define ESICLKFQ2_H (0x0004u) /* Internal oscillator frequency adjust */
\r
2677 #define ESICLKFQ1_H (0x0002u) /* Internal oscillator frequency adjust */
\r
2678 #define ESICLKFQ0_H (0x0001u) /* Internal oscillator frequency adjust */
\r
2680 /* ESICTL Control Bits */
\r
2681 #define ESIS3SEL2 (0x8000u) /* PPUS3 source select */
\r
2682 #define ESIS3SEL1 (0x4000u) /* PPUS3 source select */
\r
2683 #define ESIS3SEL0 (0x2000u) /* PPUS3 source select */
\r
2684 #define ESIS2SEL2 (0x1000u) /* PPUS2 source select */
\r
2685 #define ESIS2SEL1 (0x0800u) /* PPUS2 source select */
\r
2686 #define ESIS2SEL0 (0x0400u) /* PPUS2 source select */
\r
2687 #define ESIS1SEL2 (0x0200u) /* PPUS1 source select */
\r
2688 #define ESIS1SEL1 (0x0100u) /* PPUS1 source select */
\r
2689 #define ESIS1SEL0 (0x0080u) /* PPUS1 source select */
\r
2690 #define ESITCH11 (0x0040u) /* select the comparator input for test channel 1 */
\r
2691 #define ESITCH10 (0x0020u) /* select the comparator input for test channel 1 */
\r
2692 #define ESITCH01 (0x0010u) /* select the comparator input for test channel 0 */
\r
2693 #define ESITCH00 (0x0008u) /* select the comparator input for test channel 0 */
\r
2694 #define ESICS (0x0004u) /* Comparator output/Timer_A input selection */
\r
2695 #define ESITESTD (0x0002u) /* Test cycle insertion */
\r
2696 #define ESIEN (0x0001u) /* Extended Scan interface enable */
\r
2698 /* ESICTL Control Bits */
\r
2699 #define ESIS1SEL0_L (0x0080u) /* PPUS1 source select */
\r
2700 #define ESITCH11_L (0x0040u) /* select the comparator input for test channel 1 */
\r
2701 #define ESITCH10_L (0x0020u) /* select the comparator input for test channel 1 */
\r
2702 #define ESITCH01_L (0x0010u) /* select the comparator input for test channel 0 */
\r
2703 #define ESITCH00_L (0x0008u) /* select the comparator input for test channel 0 */
\r
2704 #define ESICS_L (0x0004u) /* Comparator output/Timer_A input selection */
\r
2705 #define ESITESTD_L (0x0002u) /* Test cycle insertion */
\r
2706 #define ESIEN_L (0x0001u) /* Extended Scan interface enable */
\r
2708 /* ESICTL Control Bits */
\r
2709 #define ESIS3SEL2_H (0x0080u) /* PPUS3 source select */
\r
2710 #define ESIS3SEL1_H (0x0040u) /* PPUS3 source select */
\r
2711 #define ESIS3SEL0_H (0x0020u) /* PPUS3 source select */
\r
2712 #define ESIS2SEL2_H (0x0010u) /* PPUS2 source select */
\r
2713 #define ESIS2SEL1_H (0x0008u) /* PPUS2 source select */
\r
2714 #define ESIS2SEL0_H (0x0004u) /* PPUS2 source select */
\r
2715 #define ESIS1SEL2_H (0x0002u) /* PPUS1 source select */
\r
2716 #define ESIS1SEL1_H (0x0001u) /* PPUS1 source select */
\r
2718 #define ESIS3SEL_0 (0x0000u) /* ESIOUT0 is the PPUS3 source */
\r
2719 #define ESIS3SEL_1 (0x2000u) /* ESIOUT1 is the PPUS3 source */
\r
2720 #define ESIS3SEL_2 (0x4000u) /* ESIOUT2 is the PPUS3 source */
\r
2721 #define ESIS3SEL_3 (0x6000u) /* ESIOUT3 is the PPUS3 source */
\r
2722 #define ESIS3SEL_4 (0x8000u) /* ESIOUT4 is the PPUS3 source */
\r
2723 #define ESIS3SEL_5 (0xA000u) /* ESIOUT5 is the PPUS3 source */
\r
2724 #define ESIS3SEL_6 (0xC000u) /* ESIOUT6 is the PPUS3 source */
\r
2725 #define ESIS3SEL_7 (0xE000u) /* ESIOUT7 is the PPUS3 source */
\r
2726 #define ESIS2SEL_0 (0x0000u) /* ESIOUT0 is the PPUS2 source */
\r
2727 #define ESIS2SEL_1 (0x0400u) /* ESIOUT1 is the PPUS2 source */
\r
2728 #define ESIS2SEL_2 (0x0800u) /* ESIOUT2 is the PPUS2 source */
\r
2729 #define ESIS2SEL_3 (0x0C00u) /* ESIOUT3 is the PPUS2 source */
\r
2730 #define ESIS2SEL_4 (0x1000u) /* ESIOUT4 is the PPUS2 source */
\r
2731 #define ESIS2SEL_5 (0x1400u) /* ESIOUT5 is the PPUS2 source */
\r
2732 #define ESIS2SEL_6 (0x1800u) /* ESIOUT6 is the PPUS2 source */
\r
2733 #define ESIS2SEL_7 (0x1C00u) /* ESIOUT7 is the PPUS2 source */
\r
2734 #define ESIS1SEL_0 (0x0000u) /* ESIOUT0 is the PPUS1 source */
\r
2735 #define ESIS1SEL_1 (0x0080u) /* ESIOUT1 is the PPUS1 source */
\r
2736 #define ESIS1SEL_2 (0x0100u) /* ESIOUT2 is the PPUS1 source */
\r
2737 #define ESIS1SEL_3 (0x0180u) /* ESIOUT3 is the PPUS1 source */
\r
2738 #define ESIS1SEL_4 (0x0200u) /* ESIOUT4 is the PPUS1 source */
\r
2739 #define ESIS1SEL_5 (0x0280u) /* ESIOUT5 is the PPUS1 source */
\r
2740 #define ESIS1SEL_6 (0x0300u) /* ESIOUT6 is the PPUS1 source */
\r
2741 #define ESIS1SEL_7 (0x0380u) /* ESIOUT7 is the PPUS1 source */
\r
2742 #define ESITCH1_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */
\r
2743 #define ESITCH1_1 (0x0400u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */
\r
2744 #define ESITCH1_2 (0x0800u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */
\r
2745 #define ESITCH1_3 (0x0C00u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */
\r
2746 #define ESITCH0_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */
\r
2747 #define ESITCH0_1 (0x0008u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */
\r
2748 #define ESITCH0_2 (0x0010u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */
\r
2749 #define ESITCH0_3 (0x0018u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */
\r
2751 /* Timing State Machine Control Bits */
\r
2752 #define ESIREPEAT4 (0x8000u) /* These bits together with the ESICLK bit configure the duration of this state */
\r
2753 #define ESIREPEAT3 (0x4000u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
\r
2754 #define ESIREPEAT2 (0x2000u) /* */
\r
2755 #define ESIREPEAT1 (0x1000u) /* */
\r
2756 #define ESIREPEAT0 (0x0800u) /* */
\r
2757 #define ESICLK (0x0400u) /* This bit selects the clock source for the TSM */
\r
2758 #define ESISTOP (0x0200u) /* This bit indicates the end of the TSM sequence */
\r
2759 #define ESIDAC (0x0100u) /* TSM DAC on */
\r
2760 #define ESITESTS1 (0x0080u) /* TSM test cycle control */
\r
2761 #define ESIRSON (0x0040u) /* Internal output latches enabled */
\r
2762 #define ESICLKON (0x0020u) /* High-frequency clock on */
\r
2763 #define ESICA (0x0010u) /* TSM comparator on */
\r
2764 #define ESIEX (0x0008u) /* Excitation and sample-and-hold */
\r
2765 #define ESILCEN (0x0004u) /* LC enable */
\r
2766 #define ESICH1 (0x0002u) /* Input channel select */
\r
2767 #define ESICH0 (0x0001u) /* Input channel select */
\r
2769 /* Timing State Machine Control Bits */
\r
2770 #define ESITESTS1_L (0x0080u) /* TSM test cycle control */
\r
2771 #define ESIRSON_L (0x0040u) /* Internal output latches enabled */
\r
2772 #define ESICLKON_L (0x0020u) /* High-frequency clock on */
\r
2773 #define ESICA_L (0x0010u) /* TSM comparator on */
\r
2774 #define ESIEX_L (0x0008u) /* Excitation and sample-and-hold */
\r
2775 #define ESILCEN_L (0x0004u) /* LC enable */
\r
2776 #define ESICH1_L (0x0002u) /* Input channel select */
\r
2777 #define ESICH0_L (0x0001u) /* Input channel select */
\r
2779 /* Timing State Machine Control Bits */
\r
2780 #define ESIREPEAT4_H (0x0080u) /* These bits together with the ESICLK bit configure the duration of this state */
\r
2781 #define ESIREPEAT3_H (0x0040u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
\r
2782 #define ESIREPEAT2_H (0x0020u) /* */
\r
2783 #define ESIREPEAT1_H (0x0010u) /* */
\r
2784 #define ESIREPEAT0_H (0x0008u) /* */
\r
2785 #define ESICLK_H (0x0004u) /* This bit selects the clock source for the TSM */
\r
2786 #define ESISTOP_H (0x0002u) /* This bit indicates the end of the TSM sequence */
\r
2787 #define ESIDAC_H (0x0001u) /* TSM DAC on */
\r
2789 #define ESICAAZ (0x0020u) /* Comparator Offset calibration annulation */
\r
2791 #define ESIREPEAT_0 (0x0000u) /* These bits configure the duration of this state */
\r
2792 #define ESIREPEAT_1 (0x0800u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
\r
2793 #define ESIREPEAT_2 (0x1000u)
\r
2794 #define ESIREPEAT_3 (0x1800u)
\r
2795 #define ESIREPEAT_4 (0x2000u)
\r
2796 #define ESIREPEAT_5 (0x2800u)
\r
2797 #define ESIREPEAT_6 (0x3000u)
\r
2798 #define ESIREPEAT_7 (0x3800u)
\r
2799 #define ESIREPEAT_8 (0x4000u)
\r
2800 #define ESIREPEAT_9 (0x4800u)
\r
2801 #define ESIREPEAT_10 (0x5000u)
\r
2802 #define ESIREPEAT_11 (0x5800u)
\r
2803 #define ESIREPEAT_12 (0x6000u)
\r
2804 #define ESIREPEAT_13 (0x6800u)
\r
2805 #define ESIREPEAT_14 (0x7000u)
\r
2806 #define ESIREPEAT_15 (0x7800u)
\r
2807 #define ESIREPEAT_16 (0x8000u)
\r
2808 #define ESIREPEAT_17 (0x8800u)
\r
2809 #define ESIREPEAT_18 (0x9000u)
\r
2810 #define ESIREPEAT_19 (0x9800u)
\r
2811 #define ESIREPEAT_20 (0xA000u)
\r
2812 #define ESIREPEAT_21 (0xA800u)
\r
2813 #define ESIREPEAT_22 (0xB000u)
\r
2814 #define ESIREPEAT_23 (0xB800u)
\r
2815 #define ESIREPEAT_24 (0xC000u)
\r
2816 #define ESIREPEAT_25 (0xC800u)
\r
2817 #define ESIREPEAT_26 (0xD000u)
\r
2818 #define ESIREPEAT_27 (0xD800u)
\r
2819 #define ESIREPEAT_28 (0xE000u)
\r
2820 #define ESIREPEAT_29 (0xE800u)
\r
2821 #define ESIREPEAT_30 (0xF000u)
\r
2822 #define ESIREPEAT_31 (0xF800u)
\r
2823 #define ESICH_0 (0x0000u) /* Input channel select: ESICH0 */
\r
2824 #define ESICH_1 (0x0001u) /* Input channel select: ESICH1 */
\r
2825 #define ESICH_2 (0x0002u) /* Input channel select: ESICH2 */
\r
2826 #define ESICH_3 (0x0003u) /* Input channel select: ESICH3 */
\r
2828 /************************************************************
\r
2829 * EXTENDED SCAN INTERFACE RAM
\r
2830 ************************************************************/
\r
2831 #ifdef __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */
\r
2833 #define OFS_ESIRAM0 (0x0000u) /* ESI RAM 0 */
\r
2834 #define OFS_ESIRAM1 (0x0001u) /* ESI RAM 1 */
\r
2835 #define OFS_ESIRAM2 (0x0002u) /* ESI RAM 2 */
\r
2836 #define OFS_ESIRAM3 (0x0003u) /* ESI RAM 3 */
\r
2837 #define OFS_ESIRAM4 (0x0004u) /* ESI RAM 4 */
\r
2838 #define OFS_ESIRAM5 (0x0005u) /* ESI RAM 5 */
\r
2839 #define OFS_ESIRAM6 (0x0006u) /* ESI RAM 6 */
\r
2840 #define OFS_ESIRAM7 (0x0007u) /* ESI RAM 7 */
\r
2841 #define OFS_ESIRAM8 (0x0008u) /* ESI RAM 8 */
\r
2842 #define OFS_ESIRAM9 (0x0009u) /* ESI RAM 9 */
\r
2843 #define OFS_ESIRAM10 (0x000Au) /* ESI RAM 10 */
\r
2844 #define OFS_ESIRAM11 (0x000Bu) /* ESI RAM 11 */
\r
2845 #define OFS_ESIRAM12 (0x000Cu) /* ESI RAM 12 */
\r
2846 #define OFS_ESIRAM13 (0x000Du) /* ESI RAM 13 */
\r
2847 #define OFS_ESIRAM14 (0x000Eu) /* ESI RAM 14 */
\r
2848 #define OFS_ESIRAM15 (0x000Fu) /* ESI RAM 15 */
\r
2849 #define OFS_ESIRAM16 (0x0010u) /* ESI RAM 16 */
\r
2850 #define OFS_ESIRAM17 (0x0011u) /* ESI RAM 17 */
\r
2851 #define OFS_ESIRAM18 (0x0012u) /* ESI RAM 18 */
\r
2852 #define OFS_ESIRAM19 (0x0013u) /* ESI RAM 19 */
\r
2853 #define OFS_ESIRAM20 (0x0014u) /* ESI RAM 20 */
\r
2854 #define OFS_ESIRAM21 (0x0015u) /* ESI RAM 21 */
\r
2855 #define OFS_ESIRAM22 (0x0016u) /* ESI RAM 22 */
\r
2856 #define OFS_ESIRAM23 (0x0017u) /* ESI RAM 23 */
\r
2857 #define OFS_ESIRAM24 (0x0018u) /* ESI RAM 24 */
\r
2858 #define OFS_ESIRAM25 (0x0019u) /* ESI RAM 25 */
\r
2859 #define OFS_ESIRAM26 (0x001Au) /* ESI RAM 26 */
\r
2860 #define OFS_ESIRAM27 (0x001Bu) /* ESI RAM 27 */
\r
2861 #define OFS_ESIRAM28 (0x001Cu) /* ESI RAM 28 */
\r
2862 #define OFS_ESIRAM29 (0x001Du) /* ESI RAM 29 */
\r
2863 #define OFS_ESIRAM30 (0x001Eu) /* ESI RAM 30 */
\r
2864 #define OFS_ESIRAM31 (0x001Fu) /* ESI RAM 31 */
\r
2865 #define OFS_ESIRAM32 (0x0020u) /* ESI RAM 32 */
\r
2866 #define OFS_ESIRAM33 (0x0021u) /* ESI RAM 33 */
\r
2867 #define OFS_ESIRAM34 (0x0022u) /* ESI RAM 34 */
\r
2868 #define OFS_ESIRAM35 (0x0023u) /* ESI RAM 35 */
\r
2869 #define OFS_ESIRAM36 (0x0024u) /* ESI RAM 36 */
\r
2870 #define OFS_ESIRAM37 (0x0025u) /* ESI RAM 37 */
\r
2871 #define OFS_ESIRAM38 (0x0026u) /* ESI RAM 38 */
\r
2872 #define OFS_ESIRAM39 (0x0027u) /* ESI RAM 39 */
\r
2873 #define OFS_ESIRAM40 (0x0028u) /* ESI RAM 40 */
\r
2874 #define OFS_ESIRAM41 (0x0029u) /* ESI RAM 41 */
\r
2875 #define OFS_ESIRAM42 (0x002Au) /* ESI RAM 42 */
\r
2876 #define OFS_ESIRAM43 (0x002Bu) /* ESI RAM 43 */
\r
2877 #define OFS_ESIRAM44 (0x002Cu) /* ESI RAM 44 */
\r
2878 #define OFS_ESIRAM45 (0x002Du) /* ESI RAM 45 */
\r
2879 #define OFS_ESIRAM46 (0x002Eu) /* ESI RAM 46 */
\r
2880 #define OFS_ESIRAM47 (0x002Fu) /* ESI RAM 47 */
\r
2881 #define OFS_ESIRAM48 (0x0030u) /* ESI RAM 48 */
\r
2882 #define OFS_ESIRAM49 (0x0031u) /* ESI RAM 49 */
\r
2883 #define OFS_ESIRAM50 (0x0032u) /* ESI RAM 50 */
\r
2884 #define OFS_ESIRAM51 (0x0033u) /* ESI RAM 51 */
\r
2885 #define OFS_ESIRAM52 (0x0034u) /* ESI RAM 52 */
\r
2886 #define OFS_ESIRAM53 (0x0035u) /* ESI RAM 53 */
\r
2887 #define OFS_ESIRAM54 (0x0036u) /* ESI RAM 54 */
\r
2888 #define OFS_ESIRAM55 (0x0037u) /* ESI RAM 55 */
\r
2889 #define OFS_ESIRAM56 (0x0038u) /* ESI RAM 56 */
\r
2890 #define OFS_ESIRAM57 (0x0039u) /* ESI RAM 57 */
\r
2891 #define OFS_ESIRAM58 (0x003Au) /* ESI RAM 58 */
\r
2892 #define OFS_ESIRAM59 (0x003Bu) /* ESI RAM 59 */
\r
2893 #define OFS_ESIRAM60 (0x003Cu) /* ESI RAM 60 */
\r
2894 #define OFS_ESIRAM61 (0x003Du) /* ESI RAM 61 */
\r
2895 #define OFS_ESIRAM62 (0x003Eu) /* ESI RAM 62 */
\r
2896 #define OFS_ESIRAM63 (0x003Fu) /* ESI RAM 63 */
\r
2897 #define OFS_ESIRAM64 (0x0040u) /* ESI RAM 64 */
\r
2898 #define OFS_ESIRAM65 (0x0041u) /* ESI RAM 65 */
\r
2899 #define OFS_ESIRAM66 (0x0042u) /* ESI RAM 66 */
\r
2900 #define OFS_ESIRAM67 (0x0043u) /* ESI RAM 67 */
\r
2901 #define OFS_ESIRAM68 (0x0044u) /* ESI RAM 68 */
\r
2902 #define OFS_ESIRAM69 (0x0045u) /* ESI RAM 69 */
\r
2903 #define OFS_ESIRAM70 (0x0046u) /* ESI RAM 70 */
\r
2904 #define OFS_ESIRAM71 (0x0047u) /* ESI RAM 71 */
\r
2905 #define OFS_ESIRAM72 (0x0048u) /* ESI RAM 72 */
\r
2906 #define OFS_ESIRAM73 (0x0049u) /* ESI RAM 73 */
\r
2907 #define OFS_ESIRAM74 (0x004Au) /* ESI RAM 74 */
\r
2908 #define OFS_ESIRAM75 (0x004Bu) /* ESI RAM 75 */
\r
2909 #define OFS_ESIRAM76 (0x004Cu) /* ESI RAM 76 */
\r
2910 #define OFS_ESIRAM77 (0x004Du) /* ESI RAM 77 */
\r
2911 #define OFS_ESIRAM78 (0x004Eu) /* ESI RAM 78 */
\r
2912 #define OFS_ESIRAM79 (0x004Fu) /* ESI RAM 79 */
\r
2913 #define OFS_ESIRAM80 (0x0050u) /* ESI RAM 80 */
\r
2914 #define OFS_ESIRAM81 (0x0051u) /* ESI RAM 81 */
\r
2915 #define OFS_ESIRAM82 (0x0052u) /* ESI RAM 82 */
\r
2916 #define OFS_ESIRAM83 (0x0053u) /* ESI RAM 83 */
\r
2917 #define OFS_ESIRAM84 (0x0054u) /* ESI RAM 84 */
\r
2918 #define OFS_ESIRAM85 (0x0055u) /* ESI RAM 85 */
\r
2919 #define OFS_ESIRAM86 (0x0056u) /* ESI RAM 86 */
\r
2920 #define OFS_ESIRAM87 (0x0057u) /* ESI RAM 87 */
\r
2921 #define OFS_ESIRAM88 (0x0058u) /* ESI RAM 88 */
\r
2922 #define OFS_ESIRAM89 (0x0059u) /* ESI RAM 89 */
\r
2923 #define OFS_ESIRAM90 (0x005Au) /* ESI RAM 90 */
\r
2924 #define OFS_ESIRAM91 (0x005Bu) /* ESI RAM 91 */
\r
2925 #define OFS_ESIRAM92 (0x005Cu) /* ESI RAM 92 */
\r
2926 #define OFS_ESIRAM93 (0x005Du) /* ESI RAM 93 */
\r
2927 #define OFS_ESIRAM94 (0x005Eu) /* ESI RAM 94 */
\r
2928 #define OFS_ESIRAM95 (0x005Fu) /* ESI RAM 95 */
\r
2929 #define OFS_ESIRAM96 (0x0060u) /* ESI RAM 96 */
\r
2930 #define OFS_ESIRAM97 (0x0061u) /* ESI RAM 97 */
\r
2931 #define OFS_ESIRAM98 (0x0062u) /* ESI RAM 98 */
\r
2932 #define OFS_ESIRAM99 (0x0063u) /* ESI RAM 99 */
\r
2933 #define OFS_ESIRAM100 (0x0064u) /* ESI RAM 100 */
\r
2934 #define OFS_ESIRAM101 (0x0065u) /* ESI RAM 101 */
\r
2935 #define OFS_ESIRAM102 (0x0066u) /* ESI RAM 102 */
\r
2936 #define OFS_ESIRAM103 (0x0067u) /* ESI RAM 103 */
\r
2937 #define OFS_ESIRAM104 (0x0068u) /* ESI RAM 104 */
\r
2938 #define OFS_ESIRAM105 (0x0069u) /* ESI RAM 105 */
\r
2939 #define OFS_ESIRAM106 (0x006Au) /* ESI RAM 106 */
\r
2940 #define OFS_ESIRAM107 (0x006Bu) /* ESI RAM 107 */
\r
2941 #define OFS_ESIRAM108 (0x006Cu) /* ESI RAM 108 */
\r
2942 #define OFS_ESIRAM109 (0x006Du) /* ESI RAM 109 */
\r
2943 #define OFS_ESIRAM110 (0x006Eu) /* ESI RAM 110 */
\r
2944 #define OFS_ESIRAM111 (0x006Fu) /* ESI RAM 111 */
\r
2945 #define OFS_ESIRAM112 (0x0070u) /* ESI RAM 112 */
\r
2946 #define OFS_ESIRAM113 (0x0071u) /* ESI RAM 113 */
\r
2947 #define OFS_ESIRAM114 (0x0072u) /* ESI RAM 114 */
\r
2948 #define OFS_ESIRAM115 (0x0073u) /* ESI RAM 115 */
\r
2949 #define OFS_ESIRAM116 (0x0074u) /* ESI RAM 116 */
\r
2950 #define OFS_ESIRAM117 (0x0075u) /* ESI RAM 117 */
\r
2951 #define OFS_ESIRAM118 (0x0076u) /* ESI RAM 118 */
\r
2952 #define OFS_ESIRAM119 (0x0077u) /* ESI RAM 119 */
\r
2953 #define OFS_ESIRAM120 (0x0078u) /* ESI RAM 120 */
\r
2954 #define OFS_ESIRAM121 (0x0079u) /* ESI RAM 121 */
\r
2955 #define OFS_ESIRAM122 (0x007Au) /* ESI RAM 122 */
\r
2956 #define OFS_ESIRAM123 (0x007Bu) /* ESI RAM 123 */
\r
2957 #define OFS_ESIRAM124 (0x007Cu) /* ESI RAM 124 */
\r
2958 #define OFS_ESIRAM125 (0x007Du) /* ESI RAM 125 */
\r
2959 #define OFS_ESIRAM126 (0x007Eu) /* ESI RAM 126 */
\r
2960 #define OFS_ESIRAM127 (0x007Fu) /* ESI RAM 127 */
\r
2962 /*************************************************************
\r
2964 *************************************************************/
\r
2965 #ifdef __MSP430_HAS_FRAM__ /* Definition to show that Module is available */
\r
2967 #define OFS_FRCTL0 (0x0000u) /* FRAM Controller Control 0 */
\r
2968 #define OFS_FRCTL0_L OFS_FRCTL0
\r
2969 #define OFS_FRCTL0_H OFS_FRCTL0+1
\r
2970 #define OFS_GCCTL0 (0x0004u) /* General Control 0 */
\r
2971 #define OFS_GCCTL0_L OFS_GCCTL0
\r
2972 #define OFS_GCCTL0_H OFS_GCCTL0+1
\r
2973 #define OFS_GCCTL1 (0x0006u) /* General Control 1 */
\r
2974 #define OFS_GCCTL1_L OFS_GCCTL1
\r
2975 #define OFS_GCCTL1_H OFS_GCCTL1+1
\r
2977 #define FRCTLPW (0xA500u) /* FRAM password for write */
\r
2978 #define FRPW (0x9600u) /* FRAM password returned by read */
\r
2979 #define FWPW (0xA500u) /* FRAM password for write */
\r
2980 #define FXPW (0x3300u) /* for use with XOR instruction */
\r
2982 /* FRCTL0 Control Bits */
\r
2983 //#define RESERVED (0x0001u) /* RESERVED */
\r
2984 //#define RESERVED (0x0002u) /* RESERVED */
\r
2985 //#define RESERVED (0x0004u) /* RESERVED */
\r
2986 #define NWAITS0 (0x0010u) /* FRAM Wait state control Bit: 0 */
\r
2987 #define NWAITS1 (0x0020u) /* FRAM Wait state control Bit: 1 */
\r
2988 #define NWAITS2 (0x0040u) /* FRAM Wait state control Bit: 2 */
\r
2989 //#define RESERVED (0x0080u) /* RESERVED */
\r
2991 /* FRCTL0 Control Bits */
\r
2992 //#define RESERVED (0x0001u) /* RESERVED */
\r
2993 //#define RESERVED (0x0002u) /* RESERVED */
\r
2994 //#define RESERVED (0x0004u) /* RESERVED */
\r
2995 #define NWAITS0_L (0x0010u) /* FRAM Wait state control Bit: 0 */
\r
2996 #define NWAITS1_L (0x0020u) /* FRAM Wait state control Bit: 1 */
\r
2997 #define NWAITS2_L (0x0040u) /* FRAM Wait state control Bit: 2 */
\r
2998 //#define RESERVED (0x0080u) /* RESERVED */
\r
3000 #define NWAITS_0 (0x0000u) /* FRAM Wait state control: 0 */
\r
3001 #define NWAITS_1 (0x0010u) /* FRAM Wait state control: 1 */
\r
3002 #define NWAITS_2 (0x0020u) /* FRAM Wait state control: 2 */
\r
3003 #define NWAITS_3 (0x0030u) /* FRAM Wait state control: 3 */
\r
3004 #define NWAITS_4 (0x0040u) /* FRAM Wait state control: 4 */
\r
3005 #define NWAITS_5 (0x0050u) /* FRAM Wait state control: 5 */
\r
3006 #define NWAITS_6 (0x0060u) /* FRAM Wait state control: 6 */
\r
3007 #define NWAITS_7 (0x0070u) /* FRAM Wait state control: 7 */
\r
3009 /* Legacy Defines */
\r
3010 #define NAUTO (0x0008u) /* FRAM Disables the wait state generator (obsolete on Rev.E and later)*/
\r
3011 #define NACCESS0 (0x0010u) /* FRAM Wait state Generator Access Time control Bit: 0 */
\r
3012 #define NACCESS1 (0x0020u) /* FRAM Wait state Generator Access Time control Bit: 1 */
\r
3013 #define NACCESS2 (0x0040u) /* FRAM Wait state Generator Access Time control Bit: 2 */
\r
3014 #define NACCESS_0 (0x0000u) /* FRAM Wait state Generator Access Time control: 0 */
\r
3015 #define NACCESS_1 (0x0010u) /* FRAM Wait state Generator Access Time control: 1 */
\r
3016 #define NACCESS_2 (0x0020u) /* FRAM Wait state Generator Access Time control: 2 */
\r
3017 #define NACCESS_3 (0x0030u) /* FRAM Wait state Generator Access Time control: 3 */
\r
3018 #define NACCESS_4 (0x0040u) /* FRAM Wait state Generator Access Time control: 4 */
\r
3019 #define NACCESS_5 (0x0050u) /* FRAM Wait state Generator Access Time control: 5 */
\r
3020 #define NACCESS_6 (0x0060u) /* FRAM Wait state Generator Access Time control: 6 */
\r
3021 #define NACCESS_7 (0x0070u) /* FRAM Wait state Generator Access Time control: 7 */
\r
3023 /* GCCTL0 Control Bits */
\r
3024 //#define RESERVED (0x0001u) /* RESERVED */
\r
3025 #define FRLPMPWR (0x0002u) /* FRAM Enable FRAM auto power up after LPM */
\r
3026 #define FRPWR (0x0004u) /* FRAM Power Control */
\r
3027 #define ACCTEIE (0x0008u) /* Enable NMI event if Access time error occurs */
\r
3028 //#define RESERVED (0x0010u) /* RESERVED */
\r
3029 #define CBDIE (0x0020u) /* Enable NMI event if correctable bit error detected */
\r
3030 #define UBDIE (0x0040u) /* Enable NMI event if uncorrectable bit error detected */
\r
3031 #define UBDRSTEN (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
\r
3033 /* GCCTL0 Control Bits */
\r
3034 //#define RESERVED (0x0001u) /* RESERVED */
\r
3035 #define FRLPMPWR_L (0x0002u) /* FRAM Enable FRAM auto power up after LPM */
\r
3036 #define FRPWR_L (0x0004u) /* FRAM Power Control */
\r
3037 #define ACCTEIE_L (0x0008u) /* Enable NMI event if Access time error occurs */
\r
3038 //#define RESERVED (0x0010u) /* RESERVED */
\r
3039 #define CBDIE_L (0x0020u) /* Enable NMI event if correctable bit error detected */
\r
3040 #define UBDIE_L (0x0040u) /* Enable NMI event if uncorrectable bit error detected */
\r
3041 #define UBDRSTEN_L (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
\r
3043 /* GCCTL1 Control Bits */
\r
3044 //#define RESERVED (0x0001u) /* RESERVED */
\r
3045 #define CBDIFG (0x0002u) /* FRAM correctable bit error flag */
\r
3046 #define UBDIFG (0x0004u) /* FRAM uncorrectable bit error flag */
\r
3047 #define ACCTEIFG (0x0008u) /* Access time error flag */
\r
3049 /* GCCTL1 Control Bits */
\r
3050 //#define RESERVED (0x0001u) /* RESERVED */
\r
3051 #define CBDIFG_L (0x0002u) /* FRAM correctable bit error flag */
\r
3052 #define UBDIFG_L (0x0004u) /* FRAM uncorrectable bit error flag */
\r
3053 #define ACCTEIFG_L (0x0008u) /* Access time error flag */
\r
3056 /************************************************************
\r
3058 ************************************************************/
\r
3059 #ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */
\r
3061 #define OFS_LCDCCTL0 (0x0000u) /* LCD_C Control Register 0 */
\r
3062 #define OFS_LCDCCTL0_L OFS_LCDCCTL0
\r
3063 #define OFS_LCDCCTL0_H OFS_LCDCCTL0+1
\r
3064 #define OFS_LCDCCTL1 (0x0002u) /* LCD_C Control Register 1 */
\r
3065 #define OFS_LCDCCTL1_L OFS_LCDCCTL1
\r
3066 #define OFS_LCDCCTL1_H OFS_LCDCCTL1+1
\r
3067 #define OFS_LCDCBLKCTL (0x0004u) /* LCD_C blinking control register */
\r
3068 #define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL
\r
3069 #define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1
\r
3070 #define OFS_LCDCMEMCTL (0x0006u) /* LCD_C memory control register */
\r
3071 #define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL
\r
3072 #define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1
\r
3073 #define OFS_LCDCVCTL (0x0008u) /* LCD_C Voltage Control Register */
\r
3074 #define OFS_LCDCVCTL_L OFS_LCDCVCTL
\r
3075 #define OFS_LCDCVCTL_H OFS_LCDCVCTL+1
\r
3076 #define OFS_LCDCPCTL0 (0x000Au) /* LCD_C Port Control Register 0 */
\r
3077 #define OFS_LCDCPCTL0_L OFS_LCDCPCTL0
\r
3078 #define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1
\r
3079 #define OFS_LCDCPCTL1 (0x000Cu) /* LCD_C Port Control Register 1 */
\r
3080 #define OFS_LCDCPCTL1_L OFS_LCDCPCTL1
\r
3081 #define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1
\r
3082 #define OFS_LCDCPCTL2 (0x000Eu) /* LCD_C Port Control Register 2 */
\r
3083 #define OFS_LCDCPCTL2_L OFS_LCDCPCTL2
\r
3084 #define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1
\r
3085 #define OFS_LCDCPCTL3 (0x0010u) /* LCD_C Port Control Register 3 */
\r
3086 #define OFS_LCDCPCTL3_L OFS_LCDCPCTL3
\r
3087 #define OFS_LCDCPCTL3_H OFS_LCDCPCTL3+1
\r
3088 #define OFS_LCDCCPCTL (0x0012u) /* LCD_C Charge Pump Control Register 3 */
\r
3089 #define OFS_LCDCCPCTL_L OFS_LCDCCPCTL
\r
3090 #define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1
\r
3091 #define OFS_LCDCIV (0x001Eu) /* LCD_C Interrupt Vector Register */
\r
3094 #define LCDON (0x0001u) /* LCD_C LCD On */
\r
3095 #define LCDLP (0x0002u) /* LCD_C Low Power Waveform */
\r
3096 #define LCDSON (0x0004u) /* LCD_C LCD Segments On */
\r
3097 #define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */
\r
3098 #define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */
\r
3099 #define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */
\r
3100 //#define RESERVED (0x0040u) /* LCD_C RESERVED */
\r
3101 #define LCDSSEL (0x0080u) /* LCD_C Clock Select */
\r
3102 #define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */
\r
3103 #define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */
\r
3104 #define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */
\r
3105 #define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */
\r
3106 #define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */
\r
3107 #define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */
\r
3108 #define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */
\r
3109 #define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */
\r
3112 #define LCDON_L (0x0001u) /* LCD_C LCD On */
\r
3113 #define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */
\r
3114 #define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */
\r
3115 #define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */
\r
3116 #define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */
\r
3117 #define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */
\r
3118 //#define RESERVED (0x0040u) /* LCD_C RESERVED */
\r
3119 #define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */
\r
3122 //#define RESERVED (0x0040u) /* LCD_C RESERVED */
\r
3123 #define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */
\r
3124 #define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */
\r
3125 #define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */
\r
3126 #define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */
\r
3127 #define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */
\r
3128 #define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */
\r
3129 #define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */
\r
3130 #define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */
\r
3132 #define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */
\r
3133 #define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */
\r
3134 #define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */
\r
3135 #define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */
\r
3136 #define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */
\r
3137 #define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */
\r
3138 #define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */
\r
3139 #define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */
\r
3140 #define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */
\r
3141 #define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */
\r
3142 #define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */
\r
3143 #define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */
\r
3145 #define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */
\r
3146 #define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */
\r
3147 #define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */
\r
3148 #define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */
\r
3149 #define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */
\r
3150 #define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */
\r
3151 #define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */
\r
3152 #define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */
\r
3153 #define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */
\r
3154 #define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */
\r
3155 #define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */
\r
3156 #define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */
\r
3157 #define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */
\r
3158 #define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */
\r
3159 #define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */
\r
3160 #define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */
\r
3161 #define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */
\r
3162 #define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */
\r
3163 #define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */
\r
3164 #define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */
\r
3165 #define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */
\r
3166 #define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */
\r
3167 #define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */
\r
3168 #define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */
\r
3169 #define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */
\r
3170 #define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */
\r
3171 #define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */
\r
3172 #define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */
\r
3173 #define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */
\r
3174 #define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */
\r
3175 #define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */
\r
3176 #define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */
\r
3177 #define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */
\r
3178 #define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */
\r
3179 #define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */
\r
3180 #define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */
\r
3181 #define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */
\r
3182 #define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */
\r
3183 #define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */
\r
3184 #define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */
\r
3185 #define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */
\r
3186 #define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */
\r
3187 #define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */
\r
3188 #define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */
\r
3189 #define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */
\r
3190 #define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */
\r
3191 #define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */
\r
3192 #define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */
\r
3193 #define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */
\r
3194 #define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */
\r
3195 #define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */
\r
3196 #define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */
\r
3197 #define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */
\r
3198 #define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */
\r
3199 #define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */
\r
3200 #define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */
\r
3201 #define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */
\r
3202 #define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */
\r
3203 #define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */
\r
3204 #define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */
\r
3205 #define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */
\r
3206 #define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */
\r
3207 #define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */
\r
3208 #define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */
\r
3210 /* Display modes coded with Bits 2-4 */
\r
3211 #define LCDSTATIC (LCDSON)
\r
3212 #define LCD2MUX (LCDMX0+LCDSON)
\r
3213 #define LCD3MUX (LCDMX1+LCDSON)
\r
3214 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
\r
3215 #define LCD5MUX (LCDMX2+LCDSON)
\r
3216 #define LCD6MUX (LCDMX2+LCDMX0+LCDSON)
\r
3217 #define LCD7MUX (LCDMX2+LCDMX1+LCDSON)
\r
3218 #define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)
\r
3221 #define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */
\r
3222 #define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */
\r
3223 #define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */
\r
3224 #define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */
\r
3225 #define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */
\r
3226 #define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */
\r
3227 #define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */
\r
3228 #define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */
\r
3231 #define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */
\r
3232 #define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */
\r
3233 #define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */
\r
3234 #define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */
\r
3237 #define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */
\r
3238 #define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */
\r
3239 #define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */
\r
3240 #define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */
\r
3243 #define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */
\r
3244 #define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */
\r
3245 #define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
\r
3246 #define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
\r
3247 #define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
\r
3248 #define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */
\r
3249 #define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */
\r
3250 #define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */
\r
3253 #define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */
\r
3254 #define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */
\r
3255 #define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
\r
3256 #define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
\r
3257 #define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
\r
3258 #define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */
\r
3259 #define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */
\r
3260 #define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */
\r
3262 #define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */
\r
3263 #define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */
\r
3264 #define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */
\r
3265 #define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */
\r
3268 #define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */
\r
3269 #define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */
\r
3270 #define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */
\r
3273 #define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */
\r
3274 #define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */
\r
3275 #define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */
\r
3278 #define LCD2B (0x0001u) /* Selects 1/2 bias. */
\r
3279 #define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */
\r
3280 #define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */
\r
3281 #define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */
\r
3282 #define VLCDEXT (0x0010u) /* Select external source for VLCD. */
\r
3283 #define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */
\r
3284 #define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */
\r
3285 #define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */
\r
3286 #define VLCD0 (0x0200u) /* VLCD select: 0 */
\r
3287 #define VLCD1 (0x0400u) /* VLCD select: 1 */
\r
3288 #define VLCD2 (0x0800u) /* VLCD select: 2 */
\r
3289 #define VLCD3 (0x1000u) /* VLCD select: 3 */
\r
3290 #define VLCD4 (0x2000u) /* VLCD select: 4 */
\r
3291 #define VLCD5 (0x4000u) /* VLCD select: 5 */
\r
3294 #define LCD2B_L (0x0001u) /* Selects 1/2 bias. */
\r
3295 #define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */
\r
3296 #define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */
\r
3297 #define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */
\r
3298 #define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */
\r
3299 #define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */
\r
3300 #define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */
\r
3301 #define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */
\r
3304 #define VLCD0_H (0x0002u) /* VLCD select: 0 */
\r
3305 #define VLCD1_H (0x0004u) /* VLCD select: 1 */
\r
3306 #define VLCD2_H (0x0008u) /* VLCD select: 2 */
\r
3307 #define VLCD3_H (0x0010u) /* VLCD select: 3 */
\r
3308 #define VLCD4_H (0x0020u) /* VLCD select: 4 */
\r
3309 #define VLCD5_H (0x0040u) /* VLCD select: 5 */
\r
3311 /* Reference voltage source select for the regulated charge pump */
\r
3312 #define VLCDREF_0 (0x0000u) /* Internal */
\r
3313 #define VLCDREF_1 (0x0002u) /* External */
\r
3314 #define VLCDREF_2 (0x0004u) /* Reserved */
\r
3315 #define VLCDREF_3 (0x0006u) /* Reserved */
\r
3317 /* Charge pump voltage selections */
\r
3318 #define VLCD_0 (0x0000u) /* Charge pump disabled */
\r
3319 #define VLCD_1 (0x0200u) /* VLCD = 2.60V */
\r
3320 #define VLCD_2 (0x0400u) /* VLCD = 2.66V */
\r
3321 #define VLCD_3 (0x0600u) /* VLCD = 2.72V */
\r
3322 #define VLCD_4 (0x0800u) /* VLCD = 2.78V */
\r
3323 #define VLCD_5 (0x0A00u) /* VLCD = 2.84V */
\r
3324 #define VLCD_6 (0x0C00u) /* VLCD = 2.90V */
\r
3325 #define VLCD_7 (0x0E00u) /* VLCD = 2.96V */
\r
3326 #define VLCD_8 (0x1000u) /* VLCD = 3.02V */
\r
3327 #define VLCD_9 (0x1200u) /* VLCD = 3.08V */
\r
3328 #define VLCD_10 (0x1400u) /* VLCD = 3.14V */
\r
3329 #define VLCD_11 (0x1600u) /* VLCD = 3.20V */
\r
3330 #define VLCD_12 (0x1800u) /* VLCD = 3.26V */
\r
3331 #define VLCD_13 (0x1A00u) /* VLCD = 3.32V */
\r
3332 #define VLCD_14 (0x1C00u) /* VLCD = 3.38V */
\r
3333 #define VLCD_15 (0x1E00u) /* VLCD = 3.44V */
\r
3335 #define VLCD_DISABLED (0x0000u) /* Charge pump disabled */
\r
3336 #define VLCD_2_60 (0x0200u) /* VLCD = 2.60V */
\r
3337 #define VLCD_2_66 (0x0400u) /* VLCD = 2.66V */
\r
3338 #define VLCD_2_72 (0x0600u) /* VLCD = 2.72V */
\r
3339 #define VLCD_2_78 (0x0800u) /* VLCD = 2.78V */
\r
3340 #define VLCD_2_84 (0x0A00u) /* VLCD = 2.84V */
\r
3341 #define VLCD_2_90 (0x0C00u) /* VLCD = 2.90V */
\r
3342 #define VLCD_2_96 (0x0E00u) /* VLCD = 2.96V */
\r
3343 #define VLCD_3_02 (0x1000u) /* VLCD = 3.02V */
\r
3344 #define VLCD_3_08 (0x1200u) /* VLCD = 3.08V */
\r
3345 #define VLCD_3_14 (0x1400u) /* VLCD = 3.14V */
\r
3346 #define VLCD_3_20 (0x1600u) /* VLCD = 3.20V */
\r
3347 #define VLCD_3_26 (0x1800u) /* VLCD = 3.26V */
\r
3348 #define VLCD_3_32 (0x1A00u) /* VLCD = 3.32V */
\r
3349 #define VLCD_3_38 (0x1C00u) /* VLCD = 3.38V */
\r
3350 #define VLCD_3_44 (0x1E00u) /* VLCD = 3.44V */
\r
3353 #define LCDS0 (0x0001u) /* LCD Segment 0 enable. */
\r
3354 #define LCDS1 (0x0002u) /* LCD Segment 1 enable. */
\r
3355 #define LCDS2 (0x0004u) /* LCD Segment 2 enable. */
\r
3356 #define LCDS3 (0x0008u) /* LCD Segment 3 enable. */
\r
3357 #define LCDS4 (0x0010u) /* LCD Segment 4 enable. */
\r
3358 #define LCDS5 (0x0020u) /* LCD Segment 5 enable. */
\r
3359 #define LCDS6 (0x0040u) /* LCD Segment 6 enable. */
\r
3360 #define LCDS7 (0x0080u) /* LCD Segment 7 enable. */
\r
3361 #define LCDS8 (0x0100u) /* LCD Segment 8 enable. */
\r
3362 #define LCDS9 (0x0200u) /* LCD Segment 9 enable. */
\r
3363 #define LCDS10 (0x0400u) /* LCD Segment 10 enable. */
\r
3364 #define LCDS11 (0x0800u) /* LCD Segment 11 enable. */
\r
3365 #define LCDS12 (0x1000u) /* LCD Segment 12 enable. */
\r
3366 #define LCDS13 (0x2000u) /* LCD Segment 13 enable. */
\r
3367 #define LCDS14 (0x4000u) /* LCD Segment 14 enable. */
\r
3368 #define LCDS15 (0x8000u) /* LCD Segment 15 enable. */
\r
3371 #define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */
\r
3372 #define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */
\r
3373 #define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */
\r
3374 #define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */
\r
3375 #define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */
\r
3376 #define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */
\r
3377 #define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */
\r
3378 #define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */
\r
3381 #define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */
\r
3382 #define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */
\r
3383 #define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */
\r
3384 #define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */
\r
3385 #define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */
\r
3386 #define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */
\r
3387 #define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */
\r
3388 #define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */
\r
3391 #define LCDS16 (0x0001u) /* LCD Segment 16 enable. */
\r
3392 #define LCDS17 (0x0002u) /* LCD Segment 17 enable. */
\r
3393 #define LCDS18 (0x0004u) /* LCD Segment 18 enable. */
\r
3394 #define LCDS19 (0x0008u) /* LCD Segment 19 enable. */
\r
3395 #define LCDS20 (0x0010u) /* LCD Segment 20 enable. */
\r
3396 #define LCDS21 (0x0020u) /* LCD Segment 21 enable. */
\r
3397 #define LCDS22 (0x0040u) /* LCD Segment 22 enable. */
\r
3398 #define LCDS23 (0x0080u) /* LCD Segment 23 enable. */
\r
3399 #define LCDS24 (0x0100u) /* LCD Segment 24 enable. */
\r
3400 #define LCDS25 (0x0200u) /* LCD Segment 25 enable. */
\r
3401 #define LCDS26 (0x0400u) /* LCD Segment 26 enable. */
\r
3402 #define LCDS27 (0x0800u) /* LCD Segment 27 enable. */
\r
3403 #define LCDS28 (0x1000u) /* LCD Segment 28 enable. */
\r
3404 #define LCDS29 (0x2000u) /* LCD Segment 29 enable. */
\r
3405 #define LCDS30 (0x4000u) /* LCD Segment 30 enable. */
\r
3406 #define LCDS31 (0x8000u) /* LCD Segment 31 enable. */
\r
3409 #define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */
\r
3410 #define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */
\r
3411 #define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */
\r
3412 #define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */
\r
3413 #define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */
\r
3414 #define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */
\r
3415 #define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */
\r
3416 #define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */
\r
3419 #define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */
\r
3420 #define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */
\r
3421 #define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */
\r
3422 #define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */
\r
3423 #define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */
\r
3424 #define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */
\r
3425 #define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */
\r
3426 #define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */
\r
3429 #define LCDS32 (0x0001u) /* LCD Segment 32 enable. */
\r
3430 #define LCDS33 (0x0002u) /* LCD Segment 33 enable. */
\r
3431 #define LCDS34 (0x0004u) /* LCD Segment 34 enable. */
\r
3432 #define LCDS35 (0x0008u) /* LCD Segment 35 enable. */
\r
3433 #define LCDS36 (0x0010u) /* LCD Segment 36 enable. */
\r
3434 #define LCDS37 (0x0020u) /* LCD Segment 37 enable. */
\r
3435 #define LCDS38 (0x0040u) /* LCD Segment 38 enable. */
\r
3436 #define LCDS39 (0x0080u) /* LCD Segment 39 enable. */
\r
3437 #define LCDS40 (0x0100u) /* LCD Segment 40 enable. */
\r
3438 #define LCDS41 (0x0200u) /* LCD Segment 41 enable. */
\r
3439 #define LCDS42 (0x0400u) /* LCD Segment 42 enable. */
\r
3440 #define LCDS43 (0x0800u) /* LCD Segment 43 enable. */
\r
3441 #define LCDS44 (0x1000u) /* LCD Segment 44 enable. */
\r
3442 #define LCDS45 (0x2000u) /* LCD Segment 45 enable. */
\r
3443 #define LCDS46 (0x4000u) /* LCD Segment 46 enable. */
\r
3444 #define LCDS47 (0x8000u) /* LCD Segment 47 enable. */
\r
3447 #define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */
\r
3448 #define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */
\r
3449 #define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */
\r
3450 #define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */
\r
3451 #define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */
\r
3452 #define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */
\r
3453 #define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */
\r
3454 #define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */
\r
3457 #define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */
\r
3458 #define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */
\r
3459 #define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */
\r
3460 #define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */
\r
3461 #define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */
\r
3462 #define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */
\r
3463 #define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */
\r
3464 #define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */
\r
3467 #define LCDS48 (0x0001u) /* LCD Segment 48 enable. */
\r
3468 #define LCDS49 (0x0002u) /* LCD Segment 49 enable. */
\r
3469 #define LCDS50 (0x0004u) /* LCD Segment 50 enable. */
\r
3470 #define LCDS51 (0x0008u) /* LCD Segment 51 enable. */
\r
3471 #define LCDS52 (0x0010u) /* LCD Segment 52 enable. */
\r
3472 #define LCDS53 (0x0020u) /* LCD Segment 53 enable. */
\r
3475 #define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */
\r
3476 #define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */
\r
3477 #define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */
\r
3478 #define LCDS51_L (0x0008u) /* LCD Segment 51 enable. */
\r
3479 #define LCDS52_L (0x0010u) /* LCD Segment 52 enable. */
\r
3480 #define LCDS53_L (0x0020u) /* LCD Segment 53 enable. */
\r
3483 #define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */
\r
3484 #define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */
\r
3485 #define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */
\r
3486 #define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */
\r
3487 #define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */
\r
3488 #define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */
\r
3489 #define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */
\r
3490 #define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */
\r
3491 #define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */
\r
3494 #define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */
\r
3495 #define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */
\r
3496 #define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */
\r
3497 #define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */
\r
3498 #define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */
\r
3499 #define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */
\r
3500 #define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */
\r
3501 #define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */
\r
3504 #define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */
\r
3506 #define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */
\r
3507 #define LCDMEM_ LCDM1 /* LCD Memory */
\r
3508 #ifndef __IAR_SYSTEMS_ICC__
\r
3509 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */
\r
3511 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
\r
3513 #define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */
\r
3514 #define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */
\r
3515 #define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */
\r
3516 #define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */
\r
3517 #define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */
\r
3518 #define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */
\r
3519 #define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */
\r
3520 #define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */
\r
3521 #define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */
\r
3522 #define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */
\r
3523 #define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */
\r
3524 #define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */
\r
3525 #define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */
\r
3526 #define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */
\r
3527 #define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */
\r
3528 #define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */
\r
3529 #define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */
\r
3530 #define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */
\r
3531 #define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */
\r
3532 #define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */
\r
3533 #define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */
\r
3534 #define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */
\r
3535 #define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */
\r
3536 #define OFS_LCDM25 (0x0038u) /* LCD Memory 25 */
\r
3537 #define OFS_LCDM26 (0x0039u) /* LCD Memory 26 */
\r
3538 #define OFS_LCDM27 (0x003Au) /* LCD Memory 27 */
\r
3539 #define OFS_LCDM28 (0x003Bu) /* LCD Memory 28 */
\r
3540 #define OFS_LCDM29 (0x003Cu) /* LCD Memory 29 */
\r
3541 #define OFS_LCDM30 (0x003Du) /* LCD Memory 30 */
\r
3542 #define OFS_LCDM31 (0x003Eu) /* LCD Memory 31 */
\r
3543 #define OFS_LCDM32 (0x003Fu) /* LCD Memory 32 */
\r
3544 #define OFS_LCDM33 (0x0040u) /* LCD Memory 33 */
\r
3545 #define OFS_LCDM34 (0x0041u) /* LCD Memory 34 */
\r
3546 #define OFS_LCDM35 (0x0042u) /* LCD Memory 35 */
\r
3547 #define OFS_LCDM36 (0x0043u) /* LCD Memory 36 */
\r
3548 #define OFS_LCDM37 (0x0044u) /* LCD Memory 37 */
\r
3549 #define OFS_LCDM38 (0x0045u) /* LCD Memory 38 */
\r
3550 #define OFS_LCDM39 (0x0046u) /* LCD Memory 39 */
\r
3551 #define OFS_LCDM40 (0x0047u) /* LCD Memory 40 */
\r
3553 #define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */
\r
3554 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
\r
3555 #ifndef __IAR_SYSTEMS_ICC__
\r
3556 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
\r
3558 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
\r
3560 #define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */
\r
3561 #define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */
\r
3562 #define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */
\r
3563 #define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */
\r
3564 #define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */
\r
3565 #define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */
\r
3566 #define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */
\r
3567 #define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */
\r
3568 #define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */
\r
3569 #define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */
\r
3570 #define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */
\r
3571 #define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */
\r
3572 #define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */
\r
3573 #define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */
\r
3574 #define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */
\r
3575 #define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */
\r
3576 #define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */
\r
3577 #define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */
\r
3578 #define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */
\r
3580 /* LCDCIV Definitions */
\r
3581 #define LCDCIV_NONE (0x0000u) /* No Interrupt pending */
\r
3582 #define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */
\r
3583 #define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */
\r
3584 #define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */
\r
3585 #define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */
\r
3588 /************************************************************
\r
3589 * Memory Protection Unit
\r
3590 ************************************************************/
\r
3591 #ifdef __MSP430_HAS_MPU__ /* Definition to show that Module is available */
\r
3593 #define OFS_MPUCTL0 (0x0000u) /* MPU Control Register 0 */
\r
3594 #define OFS_MPUCTL0_L OFS_MPUCTL0
\r
3595 #define OFS_MPUCTL0_H OFS_MPUCTL0+1
\r
3596 #define OFS_MPUCTL1 (0x0002u) /* MPU Control Register 1 */
\r
3597 #define OFS_MPUCTL1_L OFS_MPUCTL1
\r
3598 #define OFS_MPUCTL1_H OFS_MPUCTL1+1
\r
3599 #define OFS_MPUSEGB2 (0x0004u) /* MPU Segmentation Border 2 Register */
\r
3600 #define OFS_MPUSEGB2_L OFS_MPUSEGB2
\r
3601 #define OFS_MPUSEGB2_H OFS_MPUSEGB2+1
\r
3602 #define OFS_MPUSEGB1 (0x0006u) /* MPU Segmentation Border 1 Register */
\r
3603 #define OFS_MPUSEGB1_L OFS_MPUSEGB1
\r
3604 #define OFS_MPUSEGB1_H OFS_MPUSEGB1+1
\r
3605 #define OFS_MPUSAM (0x0008u) /* MPU Access Management Register */
\r
3606 #define OFS_MPUSAM_L OFS_MPUSAM
\r
3607 #define OFS_MPUSAM_H OFS_MPUSAM+1
\r
3608 #define OFS_MPUIPC0 (0x000Au) /* MPU IP Control 0 Register */
\r
3609 #define OFS_MPUIPC0_L OFS_MPUIPC0
\r
3610 #define OFS_MPUIPC0_H OFS_MPUIPC0+1
\r
3611 #define OFS_MPUIPSEGB2 (0x000Cu) /* MPU IP Segment Border 2 Register */
\r
3612 #define OFS_MPUIPSEGB2_L OFS_MPUIPSEGB2
\r
3613 #define OFS_MPUIPSEGB2_H OFS_MPUIPSEGB2+1
\r
3614 #define OFS_MPUIPSEGB1 (0x000Eu) /* MPU IP Segment Border 1 Register */
\r
3615 #define OFS_MPUIPSEGB1_L OFS_MPUIPSEGB1
\r
3616 #define OFS_MPUIPSEGB1_H OFS_MPUIPSEGB1+1
\r
3618 /* MPUCTL0 Control Bits */
\r
3619 #define MPUENA (0x0001u) /* MPU Enable */
\r
3620 #define MPULOCK (0x0002u) /* MPU Lock */
\r
3621 #define MPUSEGIE (0x0010u) /* MPU Enable NMI on Segment violation */
\r
3623 /* MPUCTL0 Control Bits */
\r
3624 #define MPUENA_L (0x0001u) /* MPU Enable */
\r
3625 #define MPULOCK_L (0x0002u) /* MPU Lock */
\r
3626 #define MPUSEGIE_L (0x0010u) /* MPU Enable NMI on Segment violation */
\r
3628 #define MPUPW (0xA500u) /* MPU Access Password */
\r
3629 #define MPUPW_H (0xA5) /* MPU Access Password */
\r
3631 /* MPUCTL1 Control Bits */
\r
3632 #define MPUSEG1IFG (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */
\r
3633 #define MPUSEG2IFG (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */
\r
3634 #define MPUSEG3IFG (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */
\r
3635 #define MPUSEGIIFG (0x0008u) /* MPU Info Memory Segment violation interupt flag */
\r
3636 #define MPUSEGIPIFG (0x0010u) /* MPU IP Memory Segment violation interupt flag */
\r
3638 /* MPUCTL1 Control Bits */
\r
3639 #define MPUSEG1IFG_L (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */
\r
3640 #define MPUSEG2IFG_L (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */
\r
3641 #define MPUSEG3IFG_L (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */
\r
3642 #define MPUSEGIIFG_L (0x0008u) /* MPU Info Memory Segment violation interupt flag */
\r
3643 #define MPUSEGIPIFG_L (0x0010u) /* MPU IP Memory Segment violation interupt flag */
\r
3645 /* MPUSEGB2 Control Bits */
\r
3647 /* MPUSEGB2 Control Bits */
\r
3649 /* MPUSEGB2 Control Bits */
\r
3651 /* MPUSEGB1 Control Bits */
\r
3653 /* MPUSEGB1 Control Bits */
\r
3655 /* MPUSEGB1 Control Bits */
\r
3657 /* MPUSAM Control Bits */
\r
3658 #define MPUSEG1RE (0x0001u) /* MPU Main memory Segment 1 Read enable */
\r
3659 #define MPUSEG1WE (0x0002u) /* MPU Main memory Segment 1 Write enable */
\r
3660 #define MPUSEG1XE (0x0004u) /* MPU Main memory Segment 1 Execute enable */
\r
3661 #define MPUSEG1VS (0x0008u) /* MPU Main memory Segment 1 Violation select */
\r
3662 #define MPUSEG2RE (0x0010u) /* MPU Main memory Segment 2 Read enable */
\r
3663 #define MPUSEG2WE (0x0020u) /* MPU Main memory Segment 2 Write enable */
\r
3664 #define MPUSEG2XE (0x0040u) /* MPU Main memory Segment 2 Execute enable */
\r
3665 #define MPUSEG2VS (0x0080u) /* MPU Main memory Segment 2 Violation select */
\r
3666 #define MPUSEG3RE (0x0100u) /* MPU Main memory Segment 3 Read enable */
\r
3667 #define MPUSEG3WE (0x0200u) /* MPU Main memory Segment 3 Write enable */
\r
3668 #define MPUSEG3XE (0x0400u) /* MPU Main memory Segment 3 Execute enable */
\r
3669 #define MPUSEG3VS (0x0800u) /* MPU Main memory Segment 3 Violation select */
\r
3670 #define MPUSEGIRE (0x1000u) /* MPU Info memory Segment Read enable */
\r
3671 #define MPUSEGIWE (0x2000u) /* MPU Info memory Segment Write enable */
\r
3672 #define MPUSEGIXE (0x4000u) /* MPU Info memory Segment Execute enable */
\r
3673 #define MPUSEGIVS (0x8000u) /* MPU Info memory Segment Violation select */
\r
3675 /* MPUSAM Control Bits */
\r
3676 #define MPUSEG1RE_L (0x0001u) /* MPU Main memory Segment 1 Read enable */
\r
3677 #define MPUSEG1WE_L (0x0002u) /* MPU Main memory Segment 1 Write enable */
\r
3678 #define MPUSEG1XE_L (0x0004u) /* MPU Main memory Segment 1 Execute enable */
\r
3679 #define MPUSEG1VS_L (0x0008u) /* MPU Main memory Segment 1 Violation select */
\r
3680 #define MPUSEG2RE_L (0x0010u) /* MPU Main memory Segment 2 Read enable */
\r
3681 #define MPUSEG2WE_L (0x0020u) /* MPU Main memory Segment 2 Write enable */
\r
3682 #define MPUSEG2XE_L (0x0040u) /* MPU Main memory Segment 2 Execute enable */
\r
3683 #define MPUSEG2VS_L (0x0080u) /* MPU Main memory Segment 2 Violation select */
\r
3685 /* MPUSAM Control Bits */
\r
3686 #define MPUSEG3RE_H (0x0001u) /* MPU Main memory Segment 3 Read enable */
\r
3687 #define MPUSEG3WE_H (0x0002u) /* MPU Main memory Segment 3 Write enable */
\r
3688 #define MPUSEG3XE_H (0x0004u) /* MPU Main memory Segment 3 Execute enable */
\r
3689 #define MPUSEG3VS_H (0x0008u) /* MPU Main memory Segment 3 Violation select */
\r
3690 #define MPUSEGIRE_H (0x0010u) /* MPU Info memory Segment Read enable */
\r
3691 #define MPUSEGIWE_H (0x0020u) /* MPU Info memory Segment Write enable */
\r
3692 #define MPUSEGIXE_H (0x0040u) /* MPU Info memory Segment Execute enable */
\r
3693 #define MPUSEGIVS_H (0x0080u) /* MPU Info memory Segment Violation select */
\r
3695 /* MPUIPC0 Control Bits */
\r
3696 #define MPUIPVS (0x0020u) /* MPU MPU IP protection segment Violation Select */
\r
3697 #define MPUIPENA (0x0040u) /* MPU MPU IP Protection Enable */
\r
3698 #define MPUIPLOCK (0x0080u) /* MPU IP Protection Lock */
\r
3700 /* MPUIPC0 Control Bits */
\r
3701 #define MPUIPVS_L (0x0020u) /* MPU MPU IP protection segment Violation Select */
\r
3702 #define MPUIPENA_L (0x0040u) /* MPU MPU IP Protection Enable */
\r
3703 #define MPUIPLOCK_L (0x0080u) /* MPU IP Protection Lock */
\r
3705 /* MPUIPSEGB2 Control Bits */
\r
3707 /* MPUIPSEGB2 Control Bits */
\r
3709 /* MPUIPSEGB2 Control Bits */
\r
3711 /* MPUIPSEGB1 Control Bits */
\r
3713 /* MPUIPSEGB1 Control Bits */
\r
3715 /* MPUIPSEGB1 Control Bits */
\r
3718 /************************************************************
\r
3719 * HARDWARE MULTIPLIER 32Bit
\r
3720 ************************************************************/
\r
3721 #ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
\r
3723 #define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */
\r
3724 #define OFS_MPY_L OFS_MPY
\r
3725 #define OFS_MPY_H OFS_MPY+1
\r
3726 #define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */
\r
3727 #define OFS_MPYS_L OFS_MPYS
\r
3728 #define OFS_MPYS_H OFS_MPYS+1
\r
3729 #define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */
\r
3730 #define OFS_MAC_L OFS_MAC
\r
3731 #define OFS_MAC_H OFS_MAC+1
\r
3732 #define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */
\r
3733 #define OFS_MACS_L OFS_MACS
\r
3734 #define OFS_MACS_H OFS_MACS+1
\r
3735 #define OFS_OP2 (0x0008u) /* Operand 2 */
\r
3736 #define OFS_OP2_L OFS_OP2
\r
3737 #define OFS_OP2_H OFS_OP2+1
\r
3738 #define OFS_RESLO (0x000Au) /* Result Low Word */
\r
3739 #define OFS_RESLO_L OFS_RESLO
\r
3740 #define OFS_RESLO_H OFS_RESLO+1
\r
3741 #define OFS_RESHI (0x000Cu) /* Result High Word */
\r
3742 #define OFS_RESHI_L OFS_RESHI
\r
3743 #define OFS_RESHI_H OFS_RESHI+1
\r
3744 #define OFS_SUMEXT (0x000Eu) /* Sum Extend */
\r
3745 #define OFS_SUMEXT_L OFS_SUMEXT
\r
3746 #define OFS_SUMEXT_H OFS_SUMEXT+1
\r
3747 #define OFS_MPY32CTL0 (0x002Cu)
\r
3748 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
\r
3749 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
\r
3751 #define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */
\r
3752 #define OFS_MPY32L_L OFS_MPY32L
\r
3753 #define OFS_MPY32L_H OFS_MPY32L+1
\r
3754 #define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */
\r
3755 #define OFS_MPY32H_L OFS_MPY32H
\r
3756 #define OFS_MPY32H_H OFS_MPY32H+1
\r
3757 #define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */
\r
3758 #define OFS_MPYS32L_L OFS_MPYS32L
\r
3759 #define OFS_MPYS32L_H OFS_MPYS32L+1
\r
3760 #define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */
\r
3761 #define OFS_MPYS32H_L OFS_MPYS32H
\r
3762 #define OFS_MPYS32H_H OFS_MPYS32H+1
\r
3763 #define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */
\r
3764 #define OFS_MAC32L_L OFS_MAC32L
\r
3765 #define OFS_MAC32L_H OFS_MAC32L+1
\r
3766 #define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */
\r
3767 #define OFS_MAC32H_L OFS_MAC32H
\r
3768 #define OFS_MAC32H_H OFS_MAC32H+1
\r
3769 #define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */
\r
3770 #define OFS_MACS32L_L OFS_MACS32L
\r
3771 #define OFS_MACS32L_H OFS_MACS32L+1
\r
3772 #define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */
\r
3773 #define OFS_MACS32H_L OFS_MACS32H
\r
3774 #define OFS_MACS32H_H OFS_MACS32H+1
\r
3775 #define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */
\r
3776 #define OFS_OP2L_L OFS_OP2L
\r
3777 #define OFS_OP2L_H OFS_OP2L+1
\r
3778 #define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */
\r
3779 #define OFS_OP2H_L OFS_OP2H
\r
3780 #define OFS_OP2H_H OFS_OP2H+1
\r
3781 #define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */
\r
3782 #define OFS_RES0_L OFS_RES0
\r
3783 #define OFS_RES0_H OFS_RES0+1
\r
3784 #define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */
\r
3785 #define OFS_RES1_L OFS_RES1
\r
3786 #define OFS_RES1_H OFS_RES1+1
\r
3787 #define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */
\r
3788 #define OFS_RES2_L OFS_RES2
\r
3789 #define OFS_RES2_H OFS_RES2+1
\r
3790 #define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */
\r
3791 #define OFS_RES3_L OFS_RES3
\r
3792 #define OFS_RES3_H OFS_RES3+1
\r
3793 #define OFS_SUMEXT (0x000Eu)
\r
3794 #define OFS_SUMEXT_L OFS_SUMEXT
\r
3795 #define OFS_SUMEXT_H OFS_SUMEXT+1
\r
3796 #define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */
\r
3797 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
\r
3798 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
\r
3800 #define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
\r
3801 #define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
\r
3802 #define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
\r
3803 #define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
\r
3804 #define OP2_B OP2_L /* Operand 2 (Byte Access) */
\r
3805 #define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
\r
3806 #define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
\r
3807 #define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
\r
3808 #define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
\r
3809 #define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
\r
3810 #define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
\r
3811 #define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
\r
3812 #define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
\r
3813 #define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
\r
3814 #define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
\r
3816 /* MPY32CTL0 Control Bits */
\r
3817 #define MPYC (0x0001u) /* Carry of the multiplier */
\r
3818 //#define RESERVED (0x0002u) /* Reserved */
\r
3819 #define MPYFRAC (0x0004u) /* Fractional mode */
\r
3820 #define MPYSAT (0x0008u) /* Saturation mode */
\r
3821 #define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */
\r
3822 #define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */
\r
3823 #define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
\r
3824 #define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
\r
3825 #define MPYDLYWRTEN (0x0100u) /* Delayed write enable */
\r
3826 #define MPYDLY32 (0x0200u) /* Delayed write mode */
\r
3828 /* MPY32CTL0 Control Bits */
\r
3829 #define MPYC_L (0x0001u) /* Carry of the multiplier */
\r
3830 //#define RESERVED (0x0002u) /* Reserved */
\r
3831 #define MPYFRAC_L (0x0004u) /* Fractional mode */
\r
3832 #define MPYSAT_L (0x0008u) /* Saturation mode */
\r
3833 #define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */
\r
3834 #define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */
\r
3835 #define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
\r
3836 #define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
\r
3838 /* MPY32CTL0 Control Bits */
\r
3839 //#define RESERVED (0x0002u) /* Reserved */
\r
3840 #define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */
\r
3841 #define MPYDLY32_H (0x0002u) /* Delayed write mode */
\r
3843 #define MPYM_0 (0x0000u) /* Multiplier mode: MPY */
\r
3844 #define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */
\r
3845 #define MPYM_2 (0x0020u) /* Multiplier mode: MAC */
\r
3846 #define MPYM_3 (0x0030u) /* Multiplier mode: MACS */
\r
3847 #define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */
\r
3848 #define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */
\r
3849 #define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */
\r
3850 #define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */
\r
3853 /************************************************************
\r
3854 * PMM - Power Management System for FRAM
\r
3855 ************************************************************/
\r
3856 #ifdef __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */
\r
3858 #define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */
\r
3859 #define OFS_PMMCTL0_L OFS_PMMCTL0
\r
3860 #define OFS_PMMCTL0_H OFS_PMMCTL0+1
\r
3861 #define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */
\r
3862 #define OFS_PMMIFG (0x000Au) /* PMM Interrupt Flag */
\r
3863 #define OFS_PMMIFG_L OFS_PMMIFG
\r
3864 #define OFS_PMMIFG_H OFS_PMMIFG+1
\r
3865 #define OFS_PM5CTL0 (0x0010u) /* PMM Power Mode 5 Control Register 0 */
\r
3866 #define OFS_PM5CTL0_L OFS_PM5CTL0
\r
3867 #define OFS_PM5CTL0_H OFS_PM5CTL0+1
\r
3869 #define PMMPW (0xA500u) /* PMM Register Write Password */
\r
3870 #define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
\r
3872 /* PMMCTL0 Control Bits */
\r
3873 #define PMMSWBOR (0x0004u) /* PMM Software BOR */
\r
3874 #define PMMSWPOR (0x0008u) /* PMM Software POR */
\r
3875 #define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */
\r
3876 #define SVSHE (0x0040u) /* SVS high side enable */
\r
3877 #define PMMLPRST (0x0080u) /* PMM Low-Power Reset Enable */
\r
3879 /* PMMCTL0 Control Bits */
\r
3880 #define PMMSWBOR_L (0x0004u) /* PMM Software BOR */
\r
3881 #define PMMSWPOR_L (0x0008u) /* PMM Software POR */
\r
3882 #define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */
\r
3883 #define SVSHE_L (0x0040u) /* SVS high side enable */
\r
3884 #define PMMLPRST_L (0x0080u) /* PMM Low-Power Reset Enable */
\r
3886 /* PMMCTL1 Control Bits */
\r
3887 #define PMMLPSVEN (0x0002u) /* PMM Low-Power Supervision Enable */
\r
3888 #define PMMLPRNG0 (0x0004u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 0 */
\r
3889 #define PMMLPRNG1 (0x0008u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 1 */
\r
3890 #define PMMAMRNG0 (0x0010u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 0 */
\r
3891 #define PMMAMRNG1 (0x0020u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 1 */
\r
3892 #define PMMAMRNG2 (0x0040u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 2 */
\r
3893 #define PMMAMRNG3 (0x0080u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 3 */
\r
3894 #define PMMCTL1KEY (0xCC00u) /* PMM PMMCTL1 Register Write Password */
\r
3896 /* PMMIFG Control Bits */
\r
3897 #define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */
\r
3898 #define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */
\r
3899 #define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */
\r
3900 #define SVSHIFG (0x2000u) /* SVS low side interrupt flag */
\r
3901 #define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */
\r
3903 /* PMMIFG Control Bits */
\r
3904 #define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */
\r
3905 #define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */
\r
3906 #define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */
\r
3907 #define SVSHIFG_H (0x0020u) /* SVS low side interrupt flag */
\r
3908 #define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */
\r
3910 /* PM5CTL0 Power Mode 5 Control Bits */
\r
3911 #define LOCKLPM5 (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
\r
3913 /* PM5CTL0 Power Mode 5 Control Bits */
\r
3914 #define LOCKLPM5_L (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
\r
3918 /************************************************************
\r
3919 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors
\r
3920 ************************************************************/
\r
3921 #ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
\r
3922 #ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
\r
3923 #ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
\r
3925 #define OFS_PAIN (0x0000u) /* Port A Input */
\r
3926 #define OFS_PAIN_L OFS_PAIN
\r
3927 #define OFS_PAIN_H OFS_PAIN+1
\r
3928 #define OFS_PAOUT (0x0002u) /* Port A Output */
\r
3929 #define OFS_PAOUT_L OFS_PAOUT
\r
3930 #define OFS_PAOUT_H OFS_PAOUT+1
\r
3931 #define OFS_PADIR (0x0004u) /* Port A Direction */
\r
3932 #define OFS_PADIR_L OFS_PADIR
\r
3933 #define OFS_PADIR_H OFS_PADIR+1
\r
3934 #define OFS_PAREN (0x0006u) /* Port A Resistor Enable */
\r
3935 #define OFS_PAREN_L OFS_PAREN
\r
3936 #define OFS_PAREN_H OFS_PAREN+1
\r
3937 #define OFS_PASEL0 (0x000Au) /* Port A Selection 0 */
\r
3938 #define OFS_PASEL0_L OFS_PASEL0
\r
3939 #define OFS_PASEL0_H OFS_PASEL0+1
\r
3940 #define OFS_PASEL1 (0x000Cu) /* Port A Selection 1 */
\r
3941 #define OFS_PASEL1_L OFS_PASEL1
\r
3942 #define OFS_PASEL1_H OFS_PASEL1+1
\r
3943 #define OFS_PASELC (0x0016u) /* Port A Complement Selection */
\r
3944 #define OFS_PASELC_L OFS_PASELC
\r
3945 #define OFS_PASELC_H OFS_PASELC+1
\r
3946 #define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */
\r
3947 #define OFS_PAIES_L OFS_PAIES
\r
3948 #define OFS_PAIES_H OFS_PAIES+1
\r
3949 #define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */
\r
3950 #define OFS_PAIE_L OFS_PAIE
\r
3951 #define OFS_PAIE_H OFS_PAIE+1
\r
3952 #define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */
\r
3953 #define OFS_PAIFG_L OFS_PAIFG
\r
3954 #define OFS_PAIFG_H OFS_PAIFG+1
\r
3957 #define OFS_P1IN (0x0000u)
\r
3958 #define OFS_P1OUT (0x0002u)
\r
3959 #define OFS_P1DIR (0x0004u)
\r
3960 #define OFS_P1REN (0x0006u)
\r
3961 #define OFS_P1SEL0 (0x000Au)
\r
3962 #define OFS_P1SEL1 (0x000Cu)
\r
3963 #define OFS_P1SELC (0x0016u)
\r
3964 #define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */
\r
3965 #define OFS_P1IES (0x0018u)
\r
3966 #define OFS_P1IE (0x001Au)
\r
3967 #define OFS_P1IFG (0x001Cu)
\r
3968 #define OFS_P2IN (0x0001u)
\r
3969 #define OFS_P2OUT (0x0003u)
\r
3970 #define OFS_P2DIR (0x0005u)
\r
3971 #define OFS_P2REN (0x0007u)
\r
3972 #define OFS_P2SEL0 (0x000Bu)
\r
3973 #define OFS_P2SEL1 (0x000Du)
\r
3974 #define OFS_P2SELC (0x0017u)
\r
3975 #define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */
\r
3976 #define OFS_P2IES (0x0019u)
\r
3977 #define OFS_P2IE (0x001Bu)
\r
3978 #define OFS_P2IFG (0x001du)
\r
3979 #define P1IN (PAIN_L) /* Port 1 Input */
\r
3980 #define P1OUT (PAOUT_L) /* Port 1 Output */
\r
3981 #define P1DIR (PADIR_L) /* Port 1 Direction */
\r
3982 #define P1REN (PAREN_L) /* Port 1 Resistor Enable */
\r
3983 #define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */
\r
3984 #define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */
\r
3985 #define P1SELC (PASELC_L) /* Port 1 Complement Selection */
\r
3986 #define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
\r
3987 #define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
\r
3988 #define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
\r
3990 //Definitions for P1IV
\r
3991 #define P1IV_NONE (0x0000u) /* No Interrupt pending */
\r
3992 #define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */
\r
3993 #define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */
\r
3994 #define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */
\r
3995 #define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */
\r
3996 #define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */
\r
3997 #define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */
\r
3998 #define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */
\r
3999 #define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */
\r
4001 #define P2IN (PAIN_H) /* Port 2 Input */
\r
4002 #define P2OUT (PAOUT_H) /* Port 2 Output */
\r
4003 #define P2DIR (PADIR_H) /* Port 2 Direction */
\r
4004 #define P2REN (PAREN_H) /* Port 2 Resistor Enable */
\r
4005 #define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */
\r
4006 #define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */
\r
4007 #define P2SELC (PASELC_H) /* Port 2 Complement Selection */
\r
4008 #define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
\r
4009 #define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
\r
4010 #define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
\r
4012 //Definitions for P2IV
\r
4013 #define P2IV_NONE (0x0000u) /* No Interrupt pending */
\r
4014 #define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */
\r
4015 #define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */
\r
4016 #define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */
\r
4017 #define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */
\r
4018 #define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */
\r
4019 #define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */
\r
4020 #define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */
\r
4021 #define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */
\r
4027 /************************************************************
\r
4028 * DIGITAL I/O Port3/4 Pull up / Pull down Resistors
\r
4029 ************************************************************/
\r
4030 #ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
\r
4031 #ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
\r
4032 #ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
\r
4034 #define OFS_PBIN (0x0000u) /* Port B Input */
\r
4035 #define OFS_PBIN_L OFS_PBIN
\r
4036 #define OFS_PBIN_H OFS_PBIN+1
\r
4037 #define OFS_PBOUT (0x0002u) /* Port B Output */
\r
4038 #define OFS_PBOUT_L OFS_PBOUT
\r
4039 #define OFS_PBOUT_H OFS_PBOUT+1
\r
4040 #define OFS_PBDIR (0x0004u) /* Port B Direction */
\r
4041 #define OFS_PBDIR_L OFS_PBDIR
\r
4042 #define OFS_PBDIR_H OFS_PBDIR+1
\r
4043 #define OFS_PBREN (0x0006u) /* Port B Resistor Enable */
\r
4044 #define OFS_PBREN_L OFS_PBREN
\r
4045 #define OFS_PBREN_H OFS_PBREN+1
\r
4046 #define OFS_PBSEL0 (0x000Au) /* Port B Selection 0 */
\r
4047 #define OFS_PBSEL0_L OFS_PBSEL0
\r
4048 #define OFS_PBSEL0_H OFS_PBSEL0+1
\r
4049 #define OFS_PBSEL1 (0x000Cu) /* Port B Selection 1 */
\r
4050 #define OFS_PBSEL1_L OFS_PBSEL1
\r
4051 #define OFS_PBSEL1_H OFS_PBSEL1+1
\r
4052 #define OFS_PBSELC (0x0016u) /* Port B Complement Selection */
\r
4053 #define OFS_PBSELC_L OFS_PBSELC
\r
4054 #define OFS_PBSELC_H OFS_PBSELC+1
\r
4055 #define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */
\r
4056 #define OFS_PBIES_L OFS_PBIES
\r
4057 #define OFS_PBIES_H OFS_PBIES+1
\r
4058 #define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */
\r
4059 #define OFS_PBIE_L OFS_PBIE
\r
4060 #define OFS_PBIE_H OFS_PBIE+1
\r
4061 #define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */
\r
4062 #define OFS_PBIFG_L OFS_PBIFG
\r
4063 #define OFS_PBIFG_H OFS_PBIFG+1
\r
4066 #define OFS_P3IN (0x0000u)
\r
4067 #define OFS_P3OUT (0x0002u)
\r
4068 #define OFS_P3DIR (0x0004u)
\r
4069 #define OFS_P3REN (0x0006u)
\r
4070 #define OFS_P3SEL0 (0x000Au)
\r
4071 #define OFS_P3SEL1 (0x000Cu)
\r
4072 #define OFS_P3SELC (0x0016u)
\r
4073 #define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */
\r
4074 #define OFS_P3IES (0x0018u)
\r
4075 #define OFS_P3IE (0x001Au)
\r
4076 #define OFS_P3IFG (0x001Cu)
\r
4077 #define OFS_P4IN (0x0001u)
\r
4078 #define OFS_P4OUT (0x0003u)
\r
4079 #define OFS_P4DIR (0x0005u)
\r
4080 #define OFS_P4REN (0x0007u)
\r
4081 #define OFS_P4SEL0 (0x000Bu)
\r
4082 #define OFS_P4SEL1 (0x000Du)
\r
4083 #define OFS_P4SELC (0x0017u)
\r
4084 #define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */
\r
4085 #define OFS_P4IES (0x0019u)
\r
4086 #define OFS_P4IE (0x001Bu)
\r
4087 #define OFS_P4IFG (0x001du)
\r
4088 #define P3IN (PBIN_L) /* Port 3 Input */
\r
4089 #define P3OUT (PBOUT_L) /* Port 3 Output */
\r
4090 #define P3DIR (PBDIR_L) /* Port 3 Direction */
\r
4091 #define P3REN (PBREN_L) /* Port 3 Resistor Enable */
\r
4092 #define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */
\r
4093 #define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */
\r
4094 #define P3SELC (PBSELC_L) /* Port 3 Complement Selection */
\r
4095 #define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
\r
4096 #define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
\r
4097 #define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
\r
4099 //Definitions for P3IV
\r
4100 #define P3IV_NONE (0x0000u) /* No Interrupt pending */
\r
4101 #define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */
\r
4102 #define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */
\r
4103 #define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */
\r
4104 #define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */
\r
4105 #define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */
\r
4106 #define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */
\r
4107 #define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */
\r
4108 #define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */
\r
4110 #define P4IN (PBIN_H) /* Port 4 Input */
\r
4111 #define P4OUT (PBOUT_H) /* Port 4 Output */
\r
4112 #define P4DIR (PBDIR_H) /* Port 4 Direction */
\r
4113 #define P4REN (PBREN_H) /* Port 4 Resistor Enable */
\r
4114 #define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */
\r
4115 #define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */
\r
4116 #define P4SELC (PBSELC_H) /* Port 4 Complement Selection */
\r
4117 #define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
\r
4118 #define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
\r
4119 #define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
\r
4121 //Definitions for P4IV
\r
4122 #define P4IV_NONE (0x0000u) /* No Interrupt pending */
\r
4123 #define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */
\r
4124 #define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */
\r
4125 #define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */
\r
4126 #define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */
\r
4127 #define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */
\r
4128 #define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */
\r
4129 #define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */
\r
4130 #define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */
\r
4136 /************************************************************
\r
4137 * DIGITAL I/O Port5/6 Pull up / Pull down Resistors
\r
4138 ************************************************************/
\r
4139 #ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
\r
4140 #ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */
\r
4141 #ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */
\r
4143 #define OFS_PCIN (0x0000u) /* Port C Input */
\r
4144 #define OFS_PCIN_L OFS_PCIN
\r
4145 #define OFS_PCIN_H OFS_PCIN+1
\r
4146 #define OFS_PCOUT (0x0002u) /* Port C Output */
\r
4147 #define OFS_PCOUT_L OFS_PCOUT
\r
4148 #define OFS_PCOUT_H OFS_PCOUT+1
\r
4149 #define OFS_PCDIR (0x0004u) /* Port C Direction */
\r
4150 #define OFS_PCDIR_L OFS_PCDIR
\r
4151 #define OFS_PCDIR_H OFS_PCDIR+1
\r
4152 #define OFS_PCREN (0x0006u) /* Port C Resistor Enable */
\r
4153 #define OFS_PCREN_L OFS_PCREN
\r
4154 #define OFS_PCREN_H OFS_PCREN+1
\r
4155 #define OFS_PCSEL0 (0x000Au) /* Port C Selection 0 */
\r
4156 #define OFS_PCSEL0_L OFS_PCSEL0
\r
4157 #define OFS_PCSEL0_H OFS_PCSEL0+1
\r
4158 #define OFS_PCSEL1 (0x000Cu) /* Port C Selection 1 */
\r
4159 #define OFS_PCSEL1_L OFS_PCSEL1
\r
4160 #define OFS_PCSEL1_H OFS_PCSEL1+1
\r
4161 #define OFS_PCSELC (0x0016u) /* Port C Complement Selection */
\r
4162 #define OFS_PCSELC_L OFS_PCSELC
\r
4163 #define OFS_PCSELC_H OFS_PCSELC+1
\r
4164 #define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */
\r
4165 #define OFS_PCIES_L OFS_PCIES
\r
4166 #define OFS_PCIES_H OFS_PCIES+1
\r
4167 #define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */
\r
4168 #define OFS_PCIE_L OFS_PCIE
\r
4169 #define OFS_PCIE_H OFS_PCIE+1
\r
4170 #define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */
\r
4171 #define OFS_PCIFG_L OFS_PCIFG
\r
4172 #define OFS_PCIFG_H OFS_PCIFG+1
\r
4175 #define OFS_P5IN (0x0000u)
\r
4176 #define OFS_P5OUT (0x0002u)
\r
4177 #define OFS_P5DIR (0x0004u)
\r
4178 #define OFS_P5REN (0x0006u)
\r
4179 #define OFS_P5SEL0 (0x000Au)
\r
4180 #define OFS_P5SEL1 (0x000Cu)
\r
4181 #define OFS_P5SELC (0x0016u)
\r
4182 #define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */
\r
4183 #define OFS_P5IES (0x0018u)
\r
4184 #define OFS_P5IE (0x001Au)
\r
4185 #define OFS_P5IFG (0x001Cu)
\r
4186 #define OFS_P6IN (0x0001u)
\r
4187 #define OFS_P6OUT (0x0003u)
\r
4188 #define OFS_P6DIR (0x0005u)
\r
4189 #define OFS_P6REN (0x0007u)
\r
4190 #define OFS_P6SEL0 (0x000Bu)
\r
4191 #define OFS_P6SEL1 (0x000Du)
\r
4192 #define OFS_P6SELC (0x0017u)
\r
4193 #define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */
\r
4194 #define OFS_P6IES (0x0019u)
\r
4195 #define OFS_P6IE (0x001Bu)
\r
4196 #define OFS_P6IFG (0x001du)
\r
4197 #define P5IN (PCIN_L) /* Port 5 Input */
\r
4198 #define P5OUT (PCOUT_L) /* Port 5 Output */
\r
4199 #define P5DIR (PCDIR_L) /* Port 5 Direction */
\r
4200 #define P5REN (PCREN_L) /* Port 5 Resistor Enable */
\r
4201 #define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */
\r
4202 #define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */
\r
4203 #define P5SELC (PCSELC_L) /* Port 5 Complement Selection */
\r
4204 #define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */
\r
4205 #define P5IE (PCIE_L) /* Port 5 Interrupt Enable */
\r
4206 #define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */
\r
4208 //Definitions for P5IV
\r
4209 #define P5IV_NONE (0x0000u) /* No Interrupt pending */
\r
4210 #define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */
\r
4211 #define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */
\r
4212 #define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */
\r
4213 #define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */
\r
4214 #define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */
\r
4215 #define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */
\r
4216 #define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */
\r
4217 #define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */
\r
4219 #define P6IN (PCIN_H) /* Port 6 Input */
\r
4220 #define P6OUT (PCOUT_H) /* Port 6 Output */
\r
4221 #define P6DIR (PCDIR_H) /* Port 6 Direction */
\r
4222 #define P6REN (PCREN_H) /* Port 6 Resistor Enable */
\r
4223 #define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */
\r
4224 #define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */
\r
4225 #define P6SELC (PCSELC_H) /* Port 6 Complement Selection */
\r
4226 #define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */
\r
4227 #define P6IE (PCIE_H) /* Port 6 Interrupt Enable */
\r
4228 #define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */
\r
4230 //Definitions for P6IV
\r
4231 #define P6IV_NONE (0x0000u) /* No Interrupt pending */
\r
4232 #define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */
\r
4233 #define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */
\r
4234 #define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */
\r
4235 #define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */
\r
4236 #define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */
\r
4237 #define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */
\r
4238 #define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */
\r
4239 #define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */
\r
4245 /************************************************************
\r
4246 * DIGITAL I/O Port7/8 Pull up / Pull down Resistors
\r
4247 ************************************************************/
\r
4248 #ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
\r
4249 #ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
\r
4250 #ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */
\r
4252 #define OFS_PDIN (0x0000u) /* Port D Input */
\r
4253 #define OFS_PDIN_L OFS_PDIN
\r
4254 #define OFS_PDIN_H OFS_PDIN+1
\r
4255 #define OFS_PDOUT (0x0002u) /* Port D Output */
\r
4256 #define OFS_PDOUT_L OFS_PDOUT
\r
4257 #define OFS_PDOUT_H OFS_PDOUT+1
\r
4258 #define OFS_PDDIR (0x0004u) /* Port D Direction */
\r
4259 #define OFS_PDDIR_L OFS_PDDIR
\r
4260 #define OFS_PDDIR_H OFS_PDDIR+1
\r
4261 #define OFS_PDREN (0x0006u) /* Port D Resistor Enable */
\r
4262 #define OFS_PDREN_L OFS_PDREN
\r
4263 #define OFS_PDREN_H OFS_PDREN+1
\r
4264 #define OFS_PDSEL0 (0x000Au) /* Port D Selection 0 */
\r
4265 #define OFS_PDSEL0_L OFS_PDSEL0
\r
4266 #define OFS_PDSEL0_H OFS_PDSEL0+1
\r
4267 #define OFS_PDSEL1 (0x000Cu) /* Port D Selection 1 */
\r
4268 #define OFS_PDSEL1_L OFS_PDSEL1
\r
4269 #define OFS_PDSEL1_H OFS_PDSEL1+1
\r
4270 #define OFS_PDSELC (0x0016u) /* Port D Complement Selection */
\r
4271 #define OFS_PDSELC_L OFS_PDSELC
\r
4272 #define OFS_PDSELC_H OFS_PDSELC+1
\r
4273 #define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */
\r
4274 #define OFS_PDIES_L OFS_PDIES
\r
4275 #define OFS_PDIES_H OFS_PDIES+1
\r
4276 #define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */
\r
4277 #define OFS_PDIE_L OFS_PDIE
\r
4278 #define OFS_PDIE_H OFS_PDIE+1
\r
4279 #define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */
\r
4280 #define OFS_PDIFG_L OFS_PDIFG
\r
4281 #define OFS_PDIFG_H OFS_PDIFG+1
\r
4284 #define OFS_P7IN (0x0000u)
\r
4285 #define OFS_P7OUT (0x0002u)
\r
4286 #define OFS_P7DIR (0x0004u)
\r
4287 #define OFS_P7REN (0x0006u)
\r
4288 #define OFS_P7SEL0 (0x000Au)
\r
4289 #define OFS_P7SEL1 (0x000Cu)
\r
4290 #define OFS_P7SELC (0x0016u)
\r
4291 #define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */
\r
4292 #define OFS_P7IES (0x0018u)
\r
4293 #define OFS_P7IE (0x001Au)
\r
4294 #define OFS_P7IFG (0x001Cu)
\r
4295 #define OFS_P8IN (0x0001u)
\r
4296 #define OFS_P8OUT (0x0003u)
\r
4297 #define OFS_P8DIR (0x0005u)
\r
4298 #define OFS_P8REN (0x0007u)
\r
4299 #define OFS_P8SEL0 (0x000Bu)
\r
4300 #define OFS_P8SEL1 (0x000Du)
\r
4301 #define OFS_P8SELC (0x0017u)
\r
4302 #define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */
\r
4303 #define OFS_P8IES (0x0019u)
\r
4304 #define OFS_P8IE (0x001Bu)
\r
4305 #define OFS_P8IFG (0x001du)
\r
4306 #define P7IN (PDIN_L) /* Port 7 Input */
\r
4307 #define P7OUT (PDOUT_L) /* Port 7 Output */
\r
4308 #define P7DIR (PDDIR_L) /* Port 7 Direction */
\r
4309 #define P7REN (PDREN_L) /* Port 7 Resistor Enable */
\r
4310 #define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */
\r
4311 #define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */
\r
4312 #define P7SELC (PDSELC_L) /* Port 7 Complement Selection */
\r
4313 #define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */
\r
4314 #define P7IE (PDIE_L) /* Port 7 Interrupt Enable */
\r
4315 #define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */
\r
4317 //Definitions for P7IV
\r
4318 #define P7IV_NONE (0x0000u) /* No Interrupt pending */
\r
4319 #define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */
\r
4320 #define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */
\r
4321 #define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */
\r
4322 #define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */
\r
4323 #define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */
\r
4324 #define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */
\r
4325 #define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */
\r
4326 #define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */
\r
4328 #define P8IN (PDIN_H) /* Port 8 Input */
\r
4329 #define P8OUT (PDOUT_H) /* Port 8 Output */
\r
4330 #define P8DIR (PDDIR_H) /* Port 8 Direction */
\r
4331 #define P8REN (PDREN_H) /* Port 8 Resistor Enable */
\r
4332 #define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */
\r
4333 #define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */
\r
4334 #define P8SELC (PDSELC_H) /* Port 8 Complement Selection */
\r
4335 #define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */
\r
4336 #define P8IE (PDIE_H) /* Port 8 Interrupt Enable */
\r
4337 #define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */
\r
4339 //Definitions for P8IV
\r
4340 #define P8IV_NONE (0x0000u) /* No Interrupt pending */
\r
4341 #define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */
\r
4342 #define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */
\r
4343 #define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */
\r
4344 #define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */
\r
4345 #define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */
\r
4346 #define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */
\r
4347 #define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */
\r
4348 #define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */
\r
4354 /************************************************************
\r
4355 * DIGITAL I/O Port9/10 Pull up / Pull down Resistors
\r
4356 ************************************************************/
\r
4357 #ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
\r
4358 #ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */
\r
4359 #ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */
\r
4361 #define OFS_PEIN (0x0000u) /* Port E Input */
\r
4362 #define OFS_PEIN_L OFS_PEIN
\r
4363 #define OFS_PEIN_H OFS_PEIN+1
\r
4364 #define OFS_PEOUT (0x0002u) /* Port E Output */
\r
4365 #define OFS_PEOUT_L OFS_PEOUT
\r
4366 #define OFS_PEOUT_H OFS_PEOUT+1
\r
4367 #define OFS_PEDIR (0x0004u) /* Port E Direction */
\r
4368 #define OFS_PEDIR_L OFS_PEDIR
\r
4369 #define OFS_PEDIR_H OFS_PEDIR+1
\r
4370 #define OFS_PEREN (0x0006u) /* Port E Resistor Enable */
\r
4371 #define OFS_PEREN_L OFS_PEREN
\r
4372 #define OFS_PEREN_H OFS_PEREN+1
\r
4373 #define OFS_PESEL0 (0x000Au) /* Port E Selection 0 */
\r
4374 #define OFS_PESEL0_L OFS_PESEL0
\r
4375 #define OFS_PESEL0_H OFS_PESEL0+1
\r
4376 #define OFS_PESEL1 (0x000Cu) /* Port E Selection 1 */
\r
4377 #define OFS_PESEL1_L OFS_PESEL1
\r
4378 #define OFS_PESEL1_H OFS_PESEL1+1
\r
4379 #define OFS_PESELC (0x0016u) /* Port E Complement Selection */
\r
4380 #define OFS_PESELC_L OFS_PESELC
\r
4381 #define OFS_PESELC_H OFS_PESELC+1
\r
4382 #define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */
\r
4383 #define OFS_PEIES_L OFS_PEIES
\r
4384 #define OFS_PEIES_H OFS_PEIES+1
\r
4385 #define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */
\r
4386 #define OFS_PEIE_L OFS_PEIE
\r
4387 #define OFS_PEIE_H OFS_PEIE+1
\r
4388 #define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */
\r
4389 #define OFS_PEIFG_L OFS_PEIFG
\r
4390 #define OFS_PEIFG_H OFS_PEIFG+1
\r
4393 #define OFS_P9IN (0x0000u)
\r
4394 #define OFS_P9OUT (0x0002u)
\r
4395 #define OFS_P9DIR (0x0004u)
\r
4396 #define OFS_P9REN (0x0006u)
\r
4397 #define OFS_P9SEL0 (0x000Au)
\r
4398 #define OFS_P9SEL1 (0x000Cu)
\r
4399 #define OFS_P9SELC (0x0016u)
\r
4400 #define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */
\r
4401 #define OFS_P9IES (0x0018u)
\r
4402 #define OFS_P9IE (0x001Au)
\r
4403 #define OFS_P9IFG (0x001Cu)
\r
4404 #define OFS_P10IN (0x0001u)
\r
4405 #define OFS_P10OUT (0x0003u)
\r
4406 #define OFS_P10DIR (0x0005u)
\r
4407 #define OFS_P10REN (0x0007u)
\r
4408 #define OFS_P10SEL0 (0x000Bu)
\r
4409 #define OFS_P10SEL1 (0x000Du)
\r
4410 #define OFS_P10SELC (0x0017u)
\r
4411 #define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */
\r
4412 #define OFS_P10IES (0x0019u)
\r
4413 #define OFS_P10IE (0x001Bu)
\r
4414 #define OFS_P10IFG (0x001du)
\r
4415 #define P9IN (PEIN_L) /* Port 9 Input */
\r
4416 #define P9OUT (PEOUT_L) /* Port 9 Output */
\r
4417 #define P9DIR (PEDIR_L) /* Port 9 Direction */
\r
4418 #define P9REN (PEREN_L) /* Port 9 Resistor Enable */
\r
4419 #define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */
\r
4420 #define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */
\r
4421 #define P9SELC (PESELC_L) /* Port 9 Complement Selection */
\r
4422 #define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */
\r
4423 #define P9IE (PEIE_L) /* Port 9 Interrupt Enable */
\r
4424 #define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */
\r
4426 //Definitions for P9IV
\r
4427 #define P9IV_NONE (0x0000u) /* No Interrupt pending */
\r
4428 #define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */
\r
4429 #define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */
\r
4430 #define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */
\r
4431 #define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */
\r
4432 #define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */
\r
4433 #define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */
\r
4434 #define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */
\r
4435 #define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */
\r
4437 #define P10IN (PEIN_H) /* Port 10 Input */
\r
4438 #define P10OUT (PEOUT_H) /* Port 10 Output */
\r
4439 #define P10DIR (PEDIR_H) /* Port 10 Direction */
\r
4440 #define P10REN (PEREN_H) /* Port 10 Resistor Enable */
\r
4441 #define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */
\r
4442 #define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */
\r
4443 #define P10SELC (PESELC_H) /* Port 10 Complement Selection */
\r
4444 #define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */
\r
4445 #define P10IE (PEIE_H) /* Port 10 Interrupt Enable */
\r
4446 #define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */
\r
4448 //Definitions for P10IV
\r
4449 #define P10IV_NONE (0x0000u) /* No Interrupt pending */
\r
4450 #define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */
\r
4451 #define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */
\r
4452 #define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */
\r
4453 #define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */
\r
4454 #define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */
\r
4455 #define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */
\r
4456 #define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */
\r
4457 #define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */
\r
4463 /************************************************************
\r
4464 * DIGITAL I/O Port11 Pull up / Pull down Resistors
\r
4465 ************************************************************/
\r
4466 #ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */
\r
4467 #ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */
\r
4469 #define OFS_PFIN (0x0000u) /* Port F Input */
\r
4470 #define OFS_PFIN_L OFS_PFIN
\r
4471 #define OFS_PFIN_H OFS_PFIN+1
\r
4472 #define OFS_PFOUT (0x0002u) /* Port F Output */
\r
4473 #define OFS_PFOUT_L OFS_PFOUT
\r
4474 #define OFS_PFOUT_H OFS_PFOUT+1
\r
4475 #define OFS_PFDIR (0x0004u) /* Port F Direction */
\r
4476 #define OFS_PFDIR_L OFS_PFDIR
\r
4477 #define OFS_PFDIR_H OFS_PFDIR+1
\r
4478 #define OFS_PFREN (0x0006u) /* Port F Resistor Enable */
\r
4479 #define OFS_PFREN_L OFS_PFREN
\r
4480 #define OFS_PFREN_H OFS_PFREN+1
\r
4481 #define OFS_PFSEL0 (0x000Au) /* Port F Selection 0 */
\r
4482 #define OFS_PFSEL0_L OFS_PFSEL0
\r
4483 #define OFS_PFSEL0_H OFS_PFSEL0+1
\r
4484 #define OFS_PFSEL1 (0x000Cu) /* Port F Selection 1 */
\r
4485 #define OFS_PFSEL1_L OFS_PFSEL1
\r
4486 #define OFS_PFSEL1_H OFS_PFSEL1+1
\r
4487 #define OFS_PFSELC (0x0016u) /* Port F Complement Selection */
\r
4488 #define OFS_PFSELC_L OFS_PFSELC
\r
4489 #define OFS_PFSELC_H OFS_PFSELC+1
\r
4490 #define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */
\r
4491 #define OFS_PFIES_L OFS_PFIES
\r
4492 #define OFS_PFIES_H OFS_PFIES+1
\r
4493 #define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */
\r
4494 #define OFS_PFIE_L OFS_PFIE
\r
4495 #define OFS_PFIE_H OFS_PFIE+1
\r
4496 #define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */
\r
4497 #define OFS_PFIFG_L OFS_PFIFG
\r
4498 #define OFS_PFIFG_H OFS_PFIFG+1
\r
4501 #define OFS_P11IN (0x0000u)
\r
4502 #define OFS_P11OUT (0x0002u)
\r
4503 #define OFS_P11DIR (0x0004u)
\r
4504 #define OFS_P11REN (0x0006u)
\r
4505 #define OFS_P11SEL0 (0x000Au)
\r
4506 #define OFS_P11SEL1 (0x000Cu)
\r
4507 #define OFS_P11SELC (0x0016u)
\r
4508 #define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */
\r
4509 #define OFS_P11IES (0x0018u)
\r
4510 #define OFS_P11IE (0x001Au)
\r
4511 #define OFS_P11IFG (0x001Cu)
\r
4512 #define P11IN (PFIN_L) /* Port 11 Input */
\r
4513 #define P11OUT (PFOUT_L) /* Port 11 Output */
\r
4514 #define P11DIR (PFDIR_L) /* Port 11 Direction */
\r
4515 #define P11REN (PFREN_L) /* Port 11 Resistor Enable */
\r
4516 #define P11SEL0 (PFSEL0_L) /* Port 11 Selection0 */
\r
4517 #define P11SEL1 (PFSEL1_L) /* Port 11 Selection1 */
\r
4518 #define OFS_P11SELC (0x0017u)
\r
4520 #define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */
\r
4521 #define P11IE (PFIE_L) /* Port 11 Interrupt Enable */
\r
4522 #define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */
\r
4524 //Definitions for P11IV
\r
4525 #define P11IV_NONE (0x0000u) /* No Interrupt pending */
\r
4526 #define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */
\r
4527 #define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */
\r
4528 #define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */
\r
4529 #define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */
\r
4530 #define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */
\r
4531 #define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */
\r
4532 #define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */
\r
4533 #define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */
\r
4538 /************************************************************
\r
4539 * DIGITAL I/O PortJ Pull up / Pull down Resistors
\r
4540 ************************************************************/
\r
4541 #ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
\r
4543 #define OFS_PJIN (0x0000u) /* Port J Input */
\r
4544 #define OFS_PJIN_L OFS_PJIN
\r
4545 #define OFS_PJIN_H OFS_PJIN+1
\r
4546 #define OFS_PJOUT (0x0002u) /* Port J Output */
\r
4547 #define OFS_PJOUT_L OFS_PJOUT
\r
4548 #define OFS_PJOUT_H OFS_PJOUT+1
\r
4549 #define OFS_PJDIR (0x0004u) /* Port J Direction */
\r
4550 #define OFS_PJDIR_L OFS_PJDIR
\r
4551 #define OFS_PJDIR_H OFS_PJDIR+1
\r
4552 #define OFS_PJREN (0x0006u) /* Port J Resistor Enable */
\r
4553 #define OFS_PJREN_L OFS_PJREN
\r
4554 #define OFS_PJREN_H OFS_PJREN+1
\r
4555 #define OFS_PJSEL0 (0x000Au) /* Port J Selection 0 */
\r
4556 #define OFS_PJSEL0_L OFS_PJSEL0
\r
4557 #define OFS_PJSEL0_H OFS_PJSEL0+1
\r
4558 #define OFS_PJSEL1 (0x000Cu) /* Port J Selection 1 */
\r
4559 #define OFS_PJSEL1_L OFS_PJSEL1
\r
4560 #define OFS_PJSEL1_H OFS_PJSEL1+1
\r
4561 #define OFS_PJSELC (0x0016u) /* Port J Complement Selection */
\r
4562 #define OFS_PJSELC_L OFS_PJSELC
\r
4563 #define OFS_PJSELC_H OFS_PJSELC+1
\r
4566 /*************************************************************
\r
4567 * RAM Control Module for FRAM
\r
4568 *************************************************************/
\r
4569 #ifdef __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */
\r
4571 #define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */
\r
4572 #define OFS_RCCTL0_L OFS_RCCTL0
\r
4573 #define OFS_RCCTL0_H OFS_RCCTL0+1
\r
4575 /* RCCTL0 Control Bits */
\r
4576 #define RCRS0OFF0 (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */
\r
4577 #define RCRS0OFF1 (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */
\r
4578 #define RCRS4OFF0 (0x0100u) /* RAM Controller RAM Sector 4 Off Bit: 0 */
\r
4579 #define RCRS4OFF1 (0x0200u) /* RAM Controller RAM Sector 4 Off Bit: 1 */
\r
4580 #define RCRS5OFF0 (0x0400u) /* RAM Controller RAM Sector 5 Off Bit: 0 */
\r
4581 #define RCRS5OFF1 (0x0800u) /* RAM Controller RAM Sector 5 Off Bit: 1 */
\r
4582 #define RCRS6OFF0 (0x1000u) /* RAM Controller RAM Sector 6 Off Bit: 0 */
\r
4583 #define RCRS6OFF1 (0x2000u) /* RAM Controller RAM Sector 6 Off Bit: 1 */
\r
4584 #define RCRS7OFF0 (0x4000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */
\r
4585 #define RCRS7OFF1 (0x8000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */
\r
4587 /* RCCTL0 Control Bits */
\r
4588 #define RCRS0OFF0_L (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */
\r
4589 #define RCRS0OFF1_L (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */
\r
4591 /* RCCTL0 Control Bits */
\r
4592 #define RCRS4OFF0_H (0x0001u) /* RAM Controller RAM Sector 4 Off Bit: 0 */
\r
4593 #define RCRS4OFF1_H (0x0002u) /* RAM Controller RAM Sector 4 Off Bit: 1 */
\r
4594 #define RCRS5OFF0_H (0x0004u) /* RAM Controller RAM Sector 5 Off Bit: 0 */
\r
4595 #define RCRS5OFF1_H (0x0008u) /* RAM Controller RAM Sector 5 Off Bit: 1 */
\r
4596 #define RCRS6OFF0_H (0x0010u) /* RAM Controller RAM Sector 6 Off Bit: 0 */
\r
4597 #define RCRS6OFF1_H (0x0020u) /* RAM Controller RAM Sector 6 Off Bit: 1 */
\r
4598 #define RCRS7OFF0_H (0x0040u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */
\r
4599 #define RCRS7OFF1_H (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */
\r
4601 #define RCKEY (0x5A00u)
\r
4603 #define RCRS0OFF_0 (0x0000u) /* RAM Controller RAM Sector 0 Off : 0 */
\r
4604 #define RCRS0OFF_1 (0x0001u) /* RAM Controller RAM Sector 0 Off : 1 */
\r
4605 #define RCRS0OFF_2 (0x0002u) /* RAM Controller RAM Sector 0 Off : 2 */
\r
4606 #define RCRS0OFF_3 (0x0003u) /* RAM Controller RAM Sector 0 Off : 3 */
\r
4607 #define RCRS4OFF_0 (0x0000u) /* RAM Controller RAM Sector 4 Off : 0 */
\r
4608 #define RCRS4OFF_2 (0x0100u) /* RAM Controller RAM Sector 4 Off : 1 */
\r
4609 #define RCRS4OFF_3 (0x0200u) /* RAM Controller RAM Sector 4 Off : 2 */
\r
4610 #define RCRS4OFF_4 (0x0300u) /* RAM Controller RAM Sector 4 Off : 3 */
\r
4611 #define RCRS5OFF_0 (0x0000u) /* RAM Controller RAM Sector 5 Off : 0 */
\r
4612 #define RCRS5OFF_1 (0x0400u) /* RAM Controller RAM Sector 5 Off : 1 */
\r
4613 #define RCRS5OFF_2 (0x0800u) /* RAM Controller RAM Sector 5 Off : 2 */
\r
4614 #define RCRS5OFF_3 (0x0C00u) /* RAM Controller RAM Sector 5 Off : 3 */
\r
4615 #define RCRS6OFF_0 (0x0000u) /* RAM Controller RAM Sector 6 Off : 0 */
\r
4616 #define RCRS6OFF_1 (0x0100u) /* RAM Controller RAM Sector 6 Off : 1 */
\r
4617 #define RCRS6OFF_2 (0x0200u) /* RAM Controller RAM Sector 6 Off : 2 */
\r
4618 #define RCRS6OFF_3 (0x0300u) /* RAM Controller RAM Sector 6 Off : 3 */
\r
4619 #define RCRS7OFF_0 (0x0000u) /* RAM Controller RAM Sector 7 Off : 0 */
\r
4620 #define RCRS7OFF_1 (0x4000u) /* RAM Controller RAM Sector 7 Off : 1 */
\r
4621 #define RCRS7OFF_2 (0x8000u) /* RAM Controller RAM Sector 7 Off : 2*/
\r
4622 #define RCRS7OFF_3 (0xC000u) /* RAM Controller RAM Sector 7 Off : 3*/
\r
4625 /************************************************************
\r
4626 * Shared Reference
\r
4627 ************************************************************/
\r
4628 #ifdef __MSP430_HAS_REF_A__ /* Definition to show that Module is available */
\r
4630 #define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */
\r
4631 #define OFS_REFCTL0_L OFS_REFCTL0
\r
4632 #define OFS_REFCTL0_H OFS_REFCTL0+1
\r
4634 /* REFCTL0 Control Bits */
\r
4635 #define REFON (0x0001u) /* REF Reference On */
\r
4636 #define REFOUT (0x0002u) /* REF Reference output Buffer On */
\r
4637 //#define RESERVED (0x0004u) /* Reserved */
\r
4638 #define REFTCOFF (0x0008u) /* REF Temp.Sensor off */
\r
4639 #define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
\r
4640 #define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
\r
4641 #define REFGENOT (0x0040u) /* REF Reference generator one-time trigger */
\r
4642 #define REFBGOT (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */
\r
4643 #define REFGENACT (0x0100u) /* REF Reference generator active */
\r
4644 #define REFBGACT (0x0200u) /* REF Reference bandgap active */
\r
4645 #define REFGENBUSY (0x0400u) /* REF Reference generator busy */
\r
4646 #define BGMODE (0x0800u) /* REF Bandgap mode */
\r
4647 #define REFGENRDY (0x1000u) /* REF Reference generator ready */
\r
4648 #define REFBGRDY (0x2000u) /* REF Reference bandgap ready */
\r
4649 //#define RESERVED (0x4000u) /* Reserved */
\r
4650 //#define RESERVED (0x8000u) /* Reserved */
\r
4652 /* REFCTL0 Control Bits */
\r
4653 #define REFON_L (0x0001u) /* REF Reference On */
\r
4654 #define REFOUT_L (0x0002u) /* REF Reference output Buffer On */
\r
4655 //#define RESERVED (0x0004u) /* Reserved */
\r
4656 #define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */
\r
4657 #define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
\r
4658 #define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
\r
4659 #define REFGENOT_L (0x0040u) /* REF Reference generator one-time trigger */
\r
4660 #define REFBGOT_L (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */
\r
4661 //#define RESERVED (0x4000u) /* Reserved */
\r
4662 //#define RESERVED (0x8000u) /* Reserved */
\r
4664 /* REFCTL0 Control Bits */
\r
4665 //#define RESERVED (0x0004u) /* Reserved */
\r
4666 #define REFGENACT_H (0x0001u) /* REF Reference generator active */
\r
4667 #define REFBGACT_H (0x0002u) /* REF Reference bandgap active */
\r
4668 #define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */
\r
4669 #define BGMODE_H (0x0008u) /* REF Bandgap mode */
\r
4670 #define REFGENRDY_H (0x0010u) /* REF Reference generator ready */
\r
4671 #define REFBGRDY_H (0x0020u) /* REF Reference bandgap ready */
\r
4672 //#define RESERVED (0x4000u) /* Reserved */
\r
4673 //#define RESERVED (0x8000u) /* Reserved */
\r
4675 #define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.2V */
\r
4676 #define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */
\r
4677 #define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */
\r
4678 #define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */
\r
4681 /************************************************************
\r
4683 ************************************************************/
\r
4684 #ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */
\r
4686 #define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */
\r
4687 #define OFS_RTCCTL01_L OFS_RTCCTL01
\r
4688 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
\r
4689 #define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */
\r
4690 #define OFS_RTCCTL23_L OFS_RTCCTL23
\r
4691 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
\r
4692 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */
\r
4693 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
\r
4694 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
\r
4695 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */
\r
4696 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
\r
4697 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
\r
4698 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */
\r
4699 #define OFS_RTCPS_L OFS_RTCPS
\r
4700 #define OFS_RTCPS_H OFS_RTCPS+1
\r
4701 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */
\r
4702 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */
\r
4703 #define OFS_RTCTIM0_L OFS_RTCTIM0
\r
4704 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
\r
4705 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */
\r
4706 #define OFS_RTCTIM1_L OFS_RTCTIM1
\r
4707 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
\r
4708 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */
\r
4709 #define OFS_RTCDATE_L OFS_RTCDATE
\r
4710 #define OFS_RTCDATE_H OFS_RTCDATE+1
\r
4711 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */
\r
4712 #define OFS_RTCYEAR_L OFS_RTCYEAR
\r
4713 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
\r
4714 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */
\r
4715 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
\r
4716 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
\r
4717 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */
\r
4718 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
\r
4719 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
\r
4720 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */
\r
4721 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */
\r
4722 #define OFS_RTCSEC (0x0010u)
\r
4723 #define OFS_RTCMIN (0x0011u)
\r
4724 #define OFS_RTCHOUR (0x0012u)
\r
4725 #define OFS_RTCDOW (0x0013u)
\r
4726 #define OFS_RTCDAY (0x0014u)
\r
4727 #define OFS_RTCMON (0x0015u)
\r
4728 #define OFS_RTCAMIN (0x0018u)
\r
4729 #define OFS_RTCAHOUR (0x0019u)
\r
4730 #define OFS_RTCADOW (0x001Au)
\r
4731 #define OFS_RTCADAY (0x001Bu)
\r
4733 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
\r
4734 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
\r
4735 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
\r
4736 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
\r
4737 #define RTCNT12 RTCTIM0
\r
4738 #define RTCNT34 RTCTIM1
\r
4739 #define RTCNT1 RTCTIM0_L
\r
4740 #define RTCNT2 RTCTIM0_H
\r
4741 #define RTCNT3 RTCTIM1_L
\r
4742 #define RTCNT4 RTCTIM1_H
\r
4743 #define RTCSEC RTCTIM0_L
\r
4744 #define RTCMIN RTCTIM0_H
\r
4745 #define RTCHOUR RTCTIM1_L
\r
4746 #define RTCDOW RTCTIM1_H
\r
4747 #define RTCDAY RTCDATE_L
\r
4748 #define RTCMON RTCDATE_H
\r
4749 #define RTCYEARL RTCYEAR_L
\r
4750 #define RTCYEARH RTCYEAR_H
\r
4751 #define RT0PS RTCPS_L
\r
4752 #define RT1PS RTCPS_H
\r
4753 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
\r
4754 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
\r
4755 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
\r
4756 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
\r
4758 /* RTCCTL01 Control Bits */
\r
4759 #define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */
\r
4760 #define RTCHOLD (0x4000u) /* RTC Hold */
\r
4761 //#define RESERVED (0x2000u) /* RESERVED */
\r
4762 #define RTCRDY (0x1000u) /* RTC Ready */
\r
4763 //#define RESERVED (0x0800u) /* RESERVED */
\r
4764 //#define RESERVED (0x0400u) /* RESERVED */
\r
4765 #define RTCTEV1 (0x0200u) /* RTC Time Event 1 */
\r
4766 #define RTCTEV0 (0x0100u) /* RTC Time Event 0 */
\r
4767 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
\r
4768 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
\r
4769 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
\r
4770 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
\r
4771 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
\r
4772 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
\r
4773 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
\r
4774 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */
\r
4776 /* RTCCTL01 Control Bits */
\r
4777 //#define RESERVED (0x2000u) /* RESERVED */
\r
4778 //#define RESERVED (0x0800u) /* RESERVED */
\r
4779 //#define RESERVED (0x0400u) /* RESERVED */
\r
4780 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
\r
4781 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
\r
4782 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
\r
4783 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
\r
4784 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
\r
4785 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
\r
4786 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
\r
4787 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */
\r
4789 /* RTCCTL01 Control Bits */
\r
4790 #define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
\r
4791 #define RTCHOLD_H (0x0040u) /* RTC Hold */
\r
4792 //#define RESERVED (0x2000u) /* RESERVED */
\r
4793 #define RTCRDY_H (0x0010u) /* RTC Ready */
\r
4794 //#define RESERVED (0x0800u) /* RESERVED */
\r
4795 //#define RESERVED (0x0400u) /* RESERVED */
\r
4796 #define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */
\r
4797 #define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */
\r
4799 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
\r
4800 #define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */
\r
4801 #define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */
\r
4802 #define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */
\r
4803 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
\r
4804 #define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */
\r
4805 #define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */
\r
4806 #define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */
\r
4808 /* RTCCTL23 Control Bits */
\r
4809 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
\r
4810 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
\r
4811 #define RTCCALS (0x0080u) /* RTC Calibration Sign */
\r
4812 //#define Reserved (0x0040u)
\r
4813 #define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */
\r
4814 #define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */
\r
4815 #define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */
\r
4816 #define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */
\r
4817 #define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */
\r
4818 #define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */
\r
4820 /* RTCCTL23 Control Bits */
\r
4821 #define RTCCALS_L (0x0080u) /* RTC Calibration Sign */
\r
4822 //#define Reserved (0x0040u)
\r
4823 #define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */
\r
4824 #define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */
\r
4825 #define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */
\r
4826 #define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */
\r
4827 #define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */
\r
4828 #define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */
\r
4830 /* RTCCTL23 Control Bits */
\r
4831 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
\r
4832 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */
\r
4833 //#define Reserved (0x0040u)
\r
4835 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
\r
4836 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
\r
4837 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
\r
4838 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */
\r
4840 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
\r
4842 /* RTCPS0CTL Control Bits */
\r
4843 //#define Reserved (0x0080u)
\r
4844 //#define Reserved (0x0040u)
\r
4845 //#define Reserved (0x0020u)
\r
4846 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
\r
4847 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
\r
4848 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
\r
4849 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
\r
4850 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
\r
4852 /* RTCPS0CTL Control Bits */
\r
4853 //#define Reserved (0x0080u)
\r
4854 //#define Reserved (0x0040u)
\r
4855 //#define Reserved (0x0020u)
\r
4856 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
\r
4857 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
\r
4858 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
\r
4859 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
\r
4860 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
\r
4862 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
\r
4863 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
\r
4864 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
\r
4865 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
\r
4866 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
\r
4867 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
\r
4868 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
\r
4869 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
\r
4871 #define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
\r
4872 #define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
\r
4873 #define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
\r
4874 #define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
\r
4875 #define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
\r
4876 #define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
\r
4877 #define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
\r
4878 #define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
\r
4880 /* RTCPS1CTL Control Bits */
\r
4881 //#define Reserved (0x0080u)
\r
4882 //#define Reserved (0x0040u)
\r
4883 //#define Reserved (0x0020u)
\r
4884 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
\r
4885 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
\r
4886 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
\r
4887 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
\r
4888 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
\r
4890 /* RTCPS1CTL Control Bits */
\r
4891 //#define Reserved (0x0080u)
\r
4892 //#define Reserved (0x0040u)
\r
4893 //#define Reserved (0x0020u)
\r
4894 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
\r
4895 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
\r
4896 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
\r
4897 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
\r
4898 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
\r
4900 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
\r
4901 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
\r
4902 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
\r
4903 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
\r
4904 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
\r
4905 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
\r
4906 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
\r
4907 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
\r
4909 #define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
\r
4910 #define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
\r
4911 #define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
\r
4912 #define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
\r
4913 #define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
\r
4914 #define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
\r
4915 #define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
\r
4916 #define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
\r
4918 /* RTC Definitions */
\r
4919 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */
\r
4920 #define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */
\r
4921 #define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */
\r
4922 #define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */
\r
4923 #define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */
\r
4924 #define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */
\r
4925 #define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */
\r
4927 /* Legacy Definitions */
\r
4928 #define RTC_NONE (0x0000u) /* No Interrupt pending */
\r
4929 #define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */
\r
4930 #define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */
\r
4931 #define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */
\r
4932 #define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */
\r
4933 #define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */
\r
4934 #define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */
\r
4937 /************************************************************
\r
4939 ************************************************************/
\r
4940 #ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */
\r
4942 #define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */
\r
4943 #define OFS_RTCCTL0_L OFS_RTCCTL0
\r
4944 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
\r
4945 #define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */
\r
4946 #define OFS_RTCCTL13_L OFS_RTCCTL13
\r
4947 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
\r
4948 #define RTCCTL1 RTCCTL13_L
\r
4949 #define RTCCTL3 RTCCTL13_H
\r
4950 #define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */
\r
4951 #define OFS_RTCOCAL_L OFS_RTCOCAL
\r
4952 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
\r
4953 #define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */
\r
4954 #define OFS_RTCTCMP_L OFS_RTCTCMP
\r
4955 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
\r
4956 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */
\r
4957 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
\r
4958 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
\r
4959 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */
\r
4960 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
\r
4961 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
\r
4962 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */
\r
4963 #define OFS_RTCPS_L OFS_RTCPS
\r
4964 #define OFS_RTCPS_H OFS_RTCPS+1
\r
4965 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */
\r
4966 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */
\r
4967 #define OFS_RTCTIM0_L OFS_RTCTIM0
\r
4968 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
\r
4969 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */
\r
4970 #define OFS_RTCTIM1_L OFS_RTCTIM1
\r
4971 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
\r
4972 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */
\r
4973 #define OFS_RTCDATE_L OFS_RTCDATE
\r
4974 #define OFS_RTCDATE_H OFS_RTCDATE+1
\r
4975 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */
\r
4976 #define OFS_RTCYEAR_L OFS_RTCYEAR
\r
4977 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
\r
4978 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */
\r
4979 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
\r
4980 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
\r
4981 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */
\r
4982 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
\r
4983 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
\r
4984 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */
\r
4985 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */
\r
4986 #define OFS_RTCSEC (0x0010u)
\r
4987 #define OFS_RTCMIN (0x0011u)
\r
4988 #define OFS_RTCHOUR (0x0012u)
\r
4989 #define OFS_RTCDOW (0x0013u)
\r
4990 #define OFS_RTCDAY (0x0014u)
\r
4991 #define OFS_RTCMON (0x0015u)
\r
4992 #define OFS_RTCAMIN (0x0018u)
\r
4993 #define OFS_RTCAHOUR (0x0019u)
\r
4994 #define OFS_RTCADOW (0x001Au)
\r
4995 #define OFS_RTCADAY (0x001Bu)
\r
4997 #define RTCSEC RTCTIM0_L
\r
4998 #define RTCMIN RTCTIM0_H
\r
4999 #define RTCHOUR RTCTIM1_L
\r
5000 #define RTCDOW RTCTIM1_H
\r
5001 #define RTCDAY RTCDATE_L
\r
5002 #define RTCMON RTCDATE_H
\r
5003 #define RTCYEARL RTCYEAR_L
\r
5004 #define RT0PS RTCPS_L
\r
5005 #define RT1PS RTCPS_H
\r
5006 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
\r
5007 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
\r
5008 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
\r
5009 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
\r
5011 /* RTCCTL0 Control Bits */
\r
5012 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
\r
5013 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
\r
5014 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
\r
5015 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
\r
5016 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
\r
5017 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
\r
5018 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
\r
5019 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */
\r
5021 /* RTCCTL0 Control Bits */
\r
5022 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
\r
5023 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
\r
5024 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
\r
5025 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
\r
5026 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
\r
5027 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
\r
5028 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
\r
5029 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */
\r
5031 #define RTCKEY (0xA500u) /* RTC Key for RTC write access */
\r
5032 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
\r
5034 /* RTCCTL13 Control Bits */
\r
5035 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
\r
5036 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
\r
5037 #define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
\r
5038 #define RTCHOLD (0x0040u) /* RTC Hold */
\r
5039 #define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
\r
5040 #define RTCRDY (0x0010u) /* RTC Ready */
\r
5041 #define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */
\r
5042 #define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */
\r
5043 #define RTCTEV1 (0x0002u) /* RTC Time Event 1 */
\r
5044 #define RTCTEV0 (0x0001u) /* RTC Time Event 0 */
\r
5046 /* RTCCTL13 Control Bits */
\r
5047 #define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
\r
5048 #define RTCHOLD_L (0x0040u) /* RTC Hold */
\r
5049 #define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
\r
5050 #define RTCRDY_L (0x0010u) /* RTC Ready */
\r
5051 #define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */
\r
5052 #define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */
\r
5053 #define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */
\r
5054 #define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */
\r
5056 /* RTCCTL13 Control Bits */
\r
5057 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
\r
5058 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */
\r
5060 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */
\r
5061 #define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */
\r
5062 #define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */
\r
5063 #define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */
\r
5064 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */
\r
5065 #define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */
\r
5066 #define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */
\r
5068 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
\r
5069 #define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */
\r
5070 #define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */
\r
5071 #define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */
\r
5072 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
\r
5073 #define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */
\r
5074 #define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */
\r
5075 #define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */
\r
5077 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
\r
5078 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
\r
5079 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
\r
5080 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */
\r
5082 /* RTCOCAL Control Bits */
\r
5083 #define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */
\r
5084 #define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */
\r
5085 #define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */
\r
5086 #define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */
\r
5087 #define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */
\r
5088 #define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */
\r
5089 #define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */
\r
5090 #define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */
\r
5091 #define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */
\r
5093 /* RTCOCAL Control Bits */
\r
5094 #define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */
\r
5095 #define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */
\r
5096 #define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */
\r
5097 #define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */
\r
5098 #define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */
\r
5099 #define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */
\r
5100 #define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */
\r
5101 #define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */
\r
5103 /* RTCOCAL Control Bits */
\r
5104 #define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */
\r
5106 /* RTCTCMP Control Bits */
\r
5107 #define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */
\r
5108 #define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */
\r
5109 #define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */
\r
5110 #define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */
\r
5111 #define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */
\r
5112 #define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */
\r
5113 #define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */
\r
5114 #define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */
\r
5115 #define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */
\r
5116 #define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */
\r
5117 #define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */
\r
5119 /* RTCTCMP Control Bits */
\r
5120 #define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */
\r
5121 #define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */
\r
5122 #define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */
\r
5123 #define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */
\r
5124 #define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */
\r
5125 #define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */
\r
5126 #define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */
\r
5127 #define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */
\r
5129 /* RTCTCMP Control Bits */
\r
5130 #define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */
\r
5131 #define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */
\r
5132 #define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */
\r
5134 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
\r
5136 /* RTCPS0CTL Control Bits */
\r
5137 //#define Reserved (0x8000u)
\r
5138 //#define Reserved (0x4000u)
\r
5139 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
\r
5140 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
\r
5141 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
\r
5142 //#define Reserved (0x0400u)
\r
5143 //#define Reserved (0x0200u)
\r
5144 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */
\r
5145 //#define Reserved (0x0080u)
\r
5146 //#define Reserved (0x0040u)
\r
5147 //#define Reserved (0x0020u)
\r
5148 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
\r
5149 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
\r
5150 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
\r
5151 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
\r
5152 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
\r
5154 /* RTCPS0CTL Control Bits */
\r
5155 //#define Reserved (0x8000u)
\r
5156 //#define Reserved (0x4000u)
\r
5157 //#define Reserved (0x0400u)
\r
5158 //#define Reserved (0x0200u)
\r
5159 //#define Reserved (0x0080u)
\r
5160 //#define Reserved (0x0040u)
\r
5161 //#define Reserved (0x0020u)
\r
5162 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
\r
5163 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
\r
5164 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
\r
5165 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
\r
5166 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
\r
5168 /* RTCPS0CTL Control Bits */
\r
5169 //#define Reserved (0x8000u)
\r
5170 //#define Reserved (0x4000u)
\r
5171 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
\r
5172 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
\r
5173 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
\r
5174 //#define Reserved (0x0400u)
\r
5175 //#define Reserved (0x0200u)
\r
5176 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */
\r
5177 //#define Reserved (0x0080u)
\r
5178 //#define Reserved (0x0040u)
\r
5179 //#define Reserved (0x0020u)
\r
5181 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
\r
5182 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
\r
5183 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
\r
5184 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
\r
5185 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
\r
5186 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
\r
5187 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
\r
5188 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
\r
5190 /* RTCPS1CTL Control Bits */
\r
5191 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */
\r
5192 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */
\r
5193 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
\r
5194 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
\r
5195 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
\r
5196 //#define Reserved (0x0400u)
\r
5197 //#define Reserved (0x0200u)
\r
5198 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */
\r
5199 //#define Reserved (0x0080u)
\r
5200 //#define Reserved (0x0040u)
\r
5201 //#define Reserved (0x0020u)
\r
5202 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
\r
5203 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
\r
5204 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
\r
5205 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
\r
5206 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
\r
5208 /* RTCPS1CTL Control Bits */
\r
5209 //#define Reserved (0x0400u)
\r
5210 //#define Reserved (0x0200u)
\r
5211 //#define Reserved (0x0080u)
\r
5212 //#define Reserved (0x0040u)
\r
5213 //#define Reserved (0x0020u)
\r
5214 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
\r
5215 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
\r
5216 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
\r
5217 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
\r
5218 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
\r
5220 /* RTCPS1CTL Control Bits */
\r
5221 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */
\r
5222 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */
\r
5223 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
\r
5224 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
\r
5225 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
\r
5226 //#define Reserved (0x0400u)
\r
5227 //#define Reserved (0x0200u)
\r
5228 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */
\r
5229 //#define Reserved (0x0080u)
\r
5230 //#define Reserved (0x0040u)
\r
5231 //#define Reserved (0x0020u)
\r
5233 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
\r
5234 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
\r
5235 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
\r
5236 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
\r
5237 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
\r
5238 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
\r
5239 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
\r
5240 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
\r
5242 /* RTC Definitions */
\r
5243 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */
\r
5244 #define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
\r
5245 #define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */
\r
5246 #define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */
\r
5247 #define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */
\r
5248 #define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */
\r
5249 #define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */
\r
5251 /* Legacy Definitions */
\r
5252 #define RTC_NONE (0x0000u) /* No Interrupt pending */
\r
5253 #define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
\r
5254 #define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */
\r
5255 #define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */
\r
5256 #define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */
\r
5257 #define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */
\r
5258 #define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */
\r
5261 /************************************************************
\r
5262 * SFR - Special Function Register Module
\r
5263 ************************************************************/
\r
5264 #ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */
\r
5266 #define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */
\r
5267 #define OFS_SFRIE1_L OFS_SFRIE1
\r
5268 #define OFS_SFRIE1_H OFS_SFRIE1+1
\r
5270 /* SFRIE1 Control Bits */
\r
5271 #define WDTIE (0x0001u) /* WDT Interrupt Enable */
\r
5272 #define OFIE (0x0002u) /* Osc Fault Enable */
\r
5273 //#define Reserved (0x0004u)
\r
5274 #define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */
\r
5275 #define NMIIE (0x0010u) /* NMI Interrupt Enable */
\r
5276 #define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */
\r
5277 #define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */
\r
5279 #define WDTIE_L (0x0001u) /* WDT Interrupt Enable */
\r
5280 #define OFIE_L (0x0002u) /* Osc Fault Enable */
\r
5281 //#define Reserved (0x0004u)
\r
5282 #define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */
\r
5283 #define NMIIE_L (0x0010u) /* NMI Interrupt Enable */
\r
5284 #define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */
\r
5285 #define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */
\r
5287 #define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */
\r
5288 #define OFS_SFRIFG1_L OFS_SFRIFG1
\r
5289 #define OFS_SFRIFG1_H OFS_SFRIFG1+1
\r
5290 /* SFRIFG1 Control Bits */
\r
5291 #define WDTIFG (0x0001u) /* WDT Interrupt Flag */
\r
5292 #define OFIFG (0x0002u) /* Osc Fault Flag */
\r
5293 //#define Reserved (0x0004u)
\r
5294 #define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */
\r
5295 #define NMIIFG (0x0010u) /* NMI Interrupt Flag */
\r
5296 //#define Reserved (0x0020u)
\r
5297 #define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */
\r
5298 #define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */
\r
5300 #define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */
\r
5301 #define OFIFG_L (0x0002u) /* Osc Fault Flag */
\r
5302 //#define Reserved (0x0004u)
\r
5303 #define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */
\r
5304 #define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */
\r
5305 //#define Reserved (0x0020u)
\r
5306 #define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */
\r
5307 #define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */
\r
5309 #define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */
\r
5310 #define OFS_SFRRPCR_L OFS_SFRRPCR
\r
5311 #define OFS_SFRRPCR_H OFS_SFRRPCR+1
\r
5312 /* SFRRPCR Control Bits */
\r
5313 #define SYSNMI (0x0001u) /* NMI select */
\r
5314 #define SYSNMIIES (0x0002u) /* NMI edge select */
\r
5315 #define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */
\r
5316 #define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */
\r
5318 #define SYSNMI_L (0x0001u) /* NMI select */
\r
5319 #define SYSNMIIES_L (0x0002u) /* NMI edge select */
\r
5320 #define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */
\r
5321 #define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */
\r
5324 /************************************************************
\r
5325 * SYS - System Module
\r
5326 ************************************************************/
\r
5327 #ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */
\r
5329 #define OFS_SYSCTL (0x0000u) /* System control */
\r
5330 #define OFS_SYSCTL_L OFS_SYSCTL
\r
5331 #define OFS_SYSCTL_H OFS_SYSCTL+1
\r
5332 #define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */
\r
5333 #define OFS_SYSBSLC_L OFS_SYSBSLC
\r
5334 #define OFS_SYSBSLC_H OFS_SYSBSLC+1
\r
5335 #define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */
\r
5336 #define OFS_SYSJMBC_L OFS_SYSJMBC
\r
5337 #define OFS_SYSJMBC_H OFS_SYSJMBC+1
\r
5338 #define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */
\r
5339 #define OFS_SYSJMBI0_L OFS_SYSJMBI0
\r
5340 #define OFS_SYSJMBI0_H OFS_SYSJMBI0+1
\r
5341 #define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */
\r
5342 #define OFS_SYSJMBI1_L OFS_SYSJMBI1
\r
5343 #define OFS_SYSJMBI1_H OFS_SYSJMBI1+1
\r
5344 #define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */
\r
5345 #define OFS_SYSJMBO0_L OFS_SYSJMBO0
\r
5346 #define OFS_SYSJMBO0_H OFS_SYSJMBO0+1
\r
5347 #define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */
\r
5348 #define OFS_SYSJMBO1_L OFS_SYSJMBO1
\r
5349 #define OFS_SYSJMBO1_H OFS_SYSJMBO1+1
\r
5351 #define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */
\r
5352 #define OFS_SYSBERRIV_L OFS_SYSBERRIV
\r
5353 #define OFS_SYSBERRIV_H OFS_SYSBERRIV+1
\r
5354 #define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */
\r
5355 #define OFS_SYSUNIV_L OFS_SYSUNIV
\r
5356 #define OFS_SYSUNIV_H OFS_SYSUNIV+1
\r
5357 #define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */
\r
5358 #define OFS_SYSSNIV_L OFS_SYSSNIV
\r
5359 #define OFS_SYSSNIV_H OFS_SYSSNIV+1
\r
5360 #define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */
\r
5361 #define OFS_SYSRSTIV_L OFS_SYSRSTIV
\r
5362 #define OFS_SYSRSTIV_H OFS_SYSRSTIV+1
\r
5364 /* SYSCTL Control Bits */
\r
5365 #define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */
\r
5366 //#define RESERVED (0x0002u) /* SYS - Reserved */
\r
5367 #define SYSPMMPE (0x0004u) /* SYS - PMM access protect */
\r
5368 //#define RESERVED (0x0008u) /* SYS - Reserved */
\r
5369 #define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */
\r
5370 #define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */
\r
5371 //#define RESERVED (0x0040u) /* SYS - Reserved */
\r
5372 //#define RESERVED (0x0080u) /* SYS - Reserved */
\r
5373 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5374 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5375 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5376 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5377 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5378 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5379 //#define RESERVED (0x4000u) /* SYS - Reserved */
\r
5380 //#define RESERVED (0x8000u) /* SYS - Reserved */
\r
5382 /* SYSCTL Control Bits */
\r
5383 #define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */
\r
5384 //#define RESERVED (0x0002u) /* SYS - Reserved */
\r
5385 #define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */
\r
5386 //#define RESERVED (0x0008u) /* SYS - Reserved */
\r
5387 #define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */
\r
5388 #define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */
\r
5389 //#define RESERVED (0x0040u) /* SYS - Reserved */
\r
5390 //#define RESERVED (0x0080u) /* SYS - Reserved */
\r
5391 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5392 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5393 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5394 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5395 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5396 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5397 //#define RESERVED (0x4000u) /* SYS - Reserved */
\r
5398 //#define RESERVED (0x8000u) /* SYS - Reserved */
\r
5400 /* SYSBSLC Control Bits */
\r
5401 #define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */
\r
5402 #define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */
\r
5403 #define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */
\r
5404 //#define RESERVED (0x0008u) /* SYS - Reserved */
\r
5405 //#define RESERVED (0x0010u) /* SYS - Reserved */
\r
5406 //#define RESERVED (0x0020u) /* SYS - Reserved */
\r
5407 //#define RESERVED (0x0040u) /* SYS - Reserved */
\r
5408 //#define RESERVED (0x0080u) /* SYS - Reserved */
\r
5409 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5410 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5411 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5412 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5413 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5414 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5415 #define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */
\r
5416 #define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */
\r
5418 /* SYSBSLC Control Bits */
\r
5419 #define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */
\r
5420 #define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */
\r
5421 #define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */
\r
5422 //#define RESERVED (0x0008u) /* SYS - Reserved */
\r
5423 //#define RESERVED (0x0010u) /* SYS - Reserved */
\r
5424 //#define RESERVED (0x0020u) /* SYS - Reserved */
\r
5425 //#define RESERVED (0x0040u) /* SYS - Reserved */
\r
5426 //#define RESERVED (0x0080u) /* SYS - Reserved */
\r
5427 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5428 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5429 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5430 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5431 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5432 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5434 /* SYSBSLC Control Bits */
\r
5435 //#define RESERVED (0x0008u) /* SYS - Reserved */
\r
5436 //#define RESERVED (0x0010u) /* SYS - Reserved */
\r
5437 //#define RESERVED (0x0020u) /* SYS - Reserved */
\r
5438 //#define RESERVED (0x0040u) /* SYS - Reserved */
\r
5439 //#define RESERVED (0x0080u) /* SYS - Reserved */
\r
5440 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5441 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5442 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5443 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5444 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5445 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5446 #define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */
\r
5447 #define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */
\r
5449 /* SYSJMBC Control Bits */
\r
5450 #define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */
\r
5451 #define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */
\r
5452 #define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */
\r
5453 #define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */
\r
5454 #define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */
\r
5455 //#define RESERVED (0x0020u) /* SYS - Reserved */
\r
5456 #define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
\r
5457 #define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
\r
5458 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5459 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5460 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5461 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5462 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5463 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5464 //#define RESERVED (0x4000u) /* SYS - Reserved */
\r
5465 //#define RESERVED (0x8000u) /* SYS - Reserved */
\r
5467 /* SYSJMBC Control Bits */
\r
5468 #define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */
\r
5469 #define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */
\r
5470 #define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */
\r
5471 #define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */
\r
5472 #define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */
\r
5473 //#define RESERVED (0x0020u) /* SYS - Reserved */
\r
5474 #define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
\r
5475 #define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
\r
5476 //#define RESERVED (0x0100u) /* SYS - Reserved */
\r
5477 //#define RESERVED (0x0200u) /* SYS - Reserved */
\r
5478 //#define RESERVED (0x0400u) /* SYS - Reserved */
\r
5479 //#define RESERVED (0x0800u) /* SYS - Reserved */
\r
5480 //#define RESERVED (0x1000u) /* SYS - Reserved */
\r
5481 //#define RESERVED (0x2000u) /* SYS - Reserved */
\r
5482 //#define RESERVED (0x4000u) /* SYS - Reserved */
\r
5483 //#define RESERVED (0x8000u) /* SYS - Reserved */
\r
5487 /************************************************************
\r
5489 ************************************************************/
\r
5490 #ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */
\r
5492 #define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */
\r
5493 #define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */
\r
5494 #define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */
\r
5495 #define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */
\r
5496 #define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */
\r
5497 #define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */
\r
5498 #define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */
\r
5499 #define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */
\r
5500 #define OFS_TAxR (0x0010u) /* Timerx_A7 */
\r
5501 #define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */
\r
5502 #define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */
\r
5503 #define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */
\r
5504 #define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */
\r
5505 #define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */
\r
5506 #define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */
\r
5507 #define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */
\r
5508 #define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */
\r
5509 #define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */
\r
5511 /* Bits are already defined within the Timer0_Ax */
\r
5513 /* TAxIV Definitions */
\r
5514 #define TAxIV_NONE (0x0000u) /* No Interrupt pending */
\r
5515 #define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */
\r
5516 #define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */
\r
5517 #define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */
\r
5518 #define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */
\r
5519 #define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */
\r
5520 #define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */
\r
5521 #define TAxIV_TAIFG (0x000Eu) /* TAxIFG */
\r
5523 /* Legacy Defines */
\r
5524 #define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */
\r
5525 #define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */
\r
5526 #define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */
\r
5527 #define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */
\r
5528 #define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */
\r
5529 #define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */
\r
5530 #define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */
\r
5532 /* TAxCTL Control Bits */
\r
5533 #define TASSEL1 (0x0200u) /* Timer A clock source select 1 */
\r
5534 #define TASSEL0 (0x0100u) /* Timer A clock source select 0 */
\r
5535 #define ID1 (0x0080u) /* Timer A clock input divider 1 */
\r
5536 #define ID0 (0x0040u) /* Timer A clock input divider 0 */
\r
5537 #define MC1 (0x0020u) /* Timer A mode control 1 */
\r
5538 #define MC0 (0x0010u) /* Timer A mode control 0 */
\r
5539 #define TACLR (0x0004u) /* Timer A counter clear */
\r
5540 #define TAIE (0x0002u) /* Timer A counter interrupt enable */
\r
5541 #define TAIFG (0x0001u) /* Timer A counter interrupt flag */
\r
5543 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
\r
5544 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
\r
5545 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */
\r
5546 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
\r
5547 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
\r
5548 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
\r
5549 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
\r
5550 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
\r
5551 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
\r
5552 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
\r
5553 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
\r
5554 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
\r
5555 #define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
\r
5556 #define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
\r
5557 #define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */
\r
5558 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
\r
5559 #define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
\r
5560 #define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
\r
5561 #define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
\r
5562 #define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
\r
5563 #define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
\r
5564 #define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
\r
5565 #define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
\r
5566 #define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
\r
5567 #define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */
\r
5569 /* TAxCCTLx Control Bits */
\r
5570 #define CM1 (0x8000u) /* Capture mode 1 */
\r
5571 #define CM0 (0x4000u) /* Capture mode 0 */
\r
5572 #define CCIS1 (0x2000u) /* Capture input select 1 */
\r
5573 #define CCIS0 (0x1000u) /* Capture input select 0 */
\r
5574 #define SCS (0x0800u) /* Capture sychronize */
\r
5575 #define SCCI (0x0400u) /* Latched capture signal (read) */
\r
5576 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
\r
5577 #define OUTMOD2 (0x0080u) /* Output mode 2 */
\r
5578 #define OUTMOD1 (0x0040u) /* Output mode 1 */
\r
5579 #define OUTMOD0 (0x0020u) /* Output mode 0 */
\r
5580 #define CCIE (0x0010u) /* Capture/compare interrupt enable */
\r
5581 #define CCI (0x0008u) /* Capture input signal (read) */
\r
5582 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */
\r
5583 #define COV (0x0002u) /* Capture/compare overflow flag */
\r
5584 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */
\r
5586 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
\r
5587 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
\r
5588 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
\r
5589 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
\r
5590 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
\r
5591 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
\r
5592 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
\r
5593 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
\r
5594 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
\r
5595 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
\r
5596 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
\r
5597 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
\r
5598 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
\r
5599 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
\r
5600 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
\r
5601 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
\r
5603 /* TAxEX0 Control Bits */
\r
5604 #define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */
\r
5605 #define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */
\r
5606 #define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */
\r
5608 #define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
\r
5609 #define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
\r
5610 #define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
\r
5611 #define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
\r
5612 #define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
\r
5613 #define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
\r
5614 #define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
\r
5615 #define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */
\r
5618 /************************************************************
\r
5620 ************************************************************/
\r
5621 #ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */
\r
5623 #define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */
\r
5624 #define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */
\r
5625 #define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */
\r
5626 #define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */
\r
5627 #define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */
\r
5628 #define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */
\r
5629 #define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */
\r
5630 #define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */
\r
5631 #define OFS_TBxR (0x0010u) /* Timerx_B7 */
\r
5632 #define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */
\r
5633 #define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */
\r
5634 #define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */
\r
5635 #define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */
\r
5636 #define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */
\r
5637 #define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */
\r
5638 #define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */
\r
5639 #define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */
\r
5640 #define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */
\r
5642 /* Bits are already defined within the Timer0_Ax */
\r
5644 /* TBxIV Definitions */
\r
5645 #define TBxIV_NONE (0x0000u) /* No Interrupt pending */
\r
5646 #define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */
\r
5647 #define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */
\r
5648 #define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */
\r
5649 #define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */
\r
5650 #define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */
\r
5651 #define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */
\r
5652 #define TBxIV_TBIFG (0x000Eu) /* TBxIFG */
\r
5654 /* Legacy Defines */
\r
5655 #define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */
\r
5656 #define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */
\r
5657 #define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */
\r
5658 #define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */
\r
5659 #define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */
\r
5660 #define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */
\r
5661 #define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */
\r
5663 /* TBxCTL Control Bits */
\r
5664 #define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */
\r
5665 #define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */
\r
5666 #define CNTL1 (0x1000u) /* Counter lenght 1 */
\r
5667 #define CNTL0 (0x0800u) /* Counter lenght 0 */
\r
5668 #define TBSSEL1 (0x0200u) /* Clock source 1 */
\r
5669 #define TBSSEL0 (0x0100u) /* Clock source 0 */
\r
5670 #define TBCLR (0x0004u) /* Timer_B7 counter clear */
\r
5671 #define TBIE (0x0002u) /* Timer_B7 interrupt enable */
\r
5672 #define TBIFG (0x0001u) /* Timer_B7 interrupt flag */
\r
5674 #define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */
\r
5675 #define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */
\r
5677 #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
\r
5678 #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
\r
5679 #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
\r
5680 #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
\r
5681 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
\r
5682 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
\r
5683 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
\r
5684 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
\r
5685 #define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
\r
5686 #define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
\r
5687 #define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
\r
5688 #define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
\r
5689 #define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
\r
5690 #define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
\r
5691 #define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
\r
5692 #define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
\r
5693 #define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */
\r
5694 #define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
\r
5695 #define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */
\r
5696 #define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */
\r
5697 #define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */
\r
5698 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
\r
5699 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
\r
5700 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
\r
5701 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
\r
5703 /* Additional Timer B Control Register bits are defined in Timer A */
\r
5704 /* TBxCCTLx Control Bits */
\r
5705 #define CLLD1 (0x0400u) /* Compare latch load source 1 */
\r
5706 #define CLLD0 (0x0200u) /* Compare latch load source 0 */
\r
5708 #define SLSHR1 (0x0400u) /* Compare latch load source 1 */
\r
5709 #define SLSHR0 (0x0200u) /* Compare latch load source 0 */
\r
5711 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
\r
5712 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
\r
5713 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
\r
5714 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
\r
5716 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
\r
5717 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
\r
5718 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
\r
5719 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
\r
5721 /* TBxEX0 Control Bits */
\r
5722 #define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */
\r
5723 #define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */
\r
5724 #define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */
\r
5726 #define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
\r
5727 #define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
\r
5728 #define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
\r
5729 #define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
\r
5730 #define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
\r
5731 #define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
\r
5732 #define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
\r
5733 #define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
\r
5734 #define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
\r
5735 #define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
\r
5736 #define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
\r
5737 #define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
\r
5738 #define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
\r
5739 #define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
\r
5740 #define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
\r
5741 #define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
\r
5744 #define ID1 (0x0080u) /* Timer B clock input divider 1 */
\r
5745 #define ID0 (0x0040u) /* Timer B clock input divider 0 */
\r
5746 #define MC1 (0x0020u) /* Timer B mode control 1 */
\r
5747 #define MC0 (0x0010u) /* Timer B mode control 0 */
\r
5748 #define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */
\r
5749 #define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
\r
5750 #define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */
\r
5751 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
\r
5752 #define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */
\r
5753 #define CM1 (0x8000u) /* Capture mode 1 */
\r
5754 #define CM0 (0x4000u) /* Capture mode 0 */
\r
5755 #define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */
\r
5756 #define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
\r
5757 #define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */
\r
5758 #define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */
\r
5759 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
\r
5760 #define CCIE (0x0010u) /* Capture/compare interrupt enable */
\r
5761 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */
\r
5762 #define CCIS_0 (0*0x1000u)
\r
5763 #define CCIS_1 (1*0x1000u)
\r
5764 #define CCIS_2 (2*0x1000u)
\r
5765 #define CCIS_3 (3*0x1000u)
\r
5766 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
\r
5767 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
\r
5768 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
\r
5769 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
\r
5770 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */
\r
5771 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
\r
5772 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
\r
5773 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
\r
5774 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
\r
5775 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
\r
5776 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
\r
5777 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
\r
5778 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
\r
5779 #define SCCI (0x0400u) /* Latched capture signal (read) */
\r
5780 #define SCS (0x0800u) /* Capture sychronize */
\r
5781 #define CCI (0x0008u) /* Capture input signal (read) */
\r
5782 #define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */
\r
5783 #define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */
\r
5784 #define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */
\r
5785 #define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */
\r
5786 #define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */
\r
5787 #define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */
\r
5788 #define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */
\r
5789 #define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */
\r
5792 /************************************************************
\r
5794 ************************************************************/
\r
5795 #ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */
\r
5797 #define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */
\r
5798 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
\r
5799 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
\r
5800 #define OFS_UCAxCTL0 (0x0001u)
\r
5801 #define OFS_UCAxCTL1 (0x0000u)
\r
5802 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
\r
5803 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
\r
5804 #define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */
\r
5805 #define OFS_UCAxCTLW1_L OFS_UCAxCTLW1
\r
5806 #define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1
\r
5807 #define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */
\r
5808 #define OFS_UCAxBRW_L OFS_UCAxBRW
\r
5809 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
\r
5810 #define OFS_UCAxBR0 (0x0006u)
\r
5811 #define OFS_UCAxBR1 (0x0007u)
\r
5812 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
\r
5813 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
\r
5814 #define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */
\r
5815 #define OFS_UCAxMCTLW_L OFS_UCAxMCTLW
\r
5816 #define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1
\r
5817 #define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */
\r
5818 #define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */
\r
5819 #define OFS_UCAxRXBUF_L OFS_UCAxRXBUF
\r
5820 #define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1
\r
5821 #define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */
\r
5822 #define OFS_UCAxTXBUF_L OFS_UCAxTXBUF
\r
5823 #define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1
\r
5824 #define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */
\r
5825 #define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */
\r
5826 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
\r
5827 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
\r
5828 #define OFS_UCAxIRTCTL (0x0012u)
\r
5829 #define OFS_UCAxIRRCTL (0x0013u)
\r
5830 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
\r
5831 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
\r
5832 #define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */
\r
5833 #define OFS_UCAxIE_L OFS_UCAxIE
\r
5834 #define OFS_UCAxIE_H OFS_UCAxIE+1
\r
5835 #define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */
\r
5836 #define OFS_UCAxIFG_L OFS_UCAxIFG
\r
5837 #define OFS_UCAxIFG_H OFS_UCAxIFG+1
\r
5838 #define OFS_UCAxIE__UART (0x001Au)
\r
5839 #define OFS_UCAxIE__UART_L OFS_UCAxIE__UART
\r
5840 #define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1
\r
5841 #define OFS_UCAxIFG__UART (0x001Cu)
\r
5842 #define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART
\r
5843 #define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1
\r
5844 #define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */
\r
5846 #define OFS_UCAxCTLW0__SPI (0x0000u)
\r
5847 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
\r
5848 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
\r
5849 #define OFS_UCAxCTL0__SPI (0x0001u)
\r
5850 #define OFS_UCAxCTL1__SPI (0x0000u)
\r
5851 #define OFS_UCAxBRW__SPI (0x0006u)
\r
5852 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
\r
5853 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
\r
5854 #define OFS_UCAxBR0__SPI (0x0006u)
\r
5855 #define OFS_UCAxBR1__SPI (0x0007u)
\r
5856 #define OFS_UCAxSTATW__SPI (0x000Au)
\r
5857 #define OFS_UCAxRXBUF__SPI (0x000Cu)
\r
5858 #define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI
\r
5859 #define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1
\r
5860 #define OFS_UCAxTXBUF__SPI (0x000Eu)
\r
5861 #define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI
\r
5862 #define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1
\r
5863 #define OFS_UCAxIE__SPI (0x001Au)
\r
5864 #define OFS_UCAxIFG__SPI (0x001Cu)
\r
5865 #define OFS_UCAxIV__SPI (0x001Eu)
\r
5868 /************************************************************
\r
5870 ************************************************************/
\r
5871 #ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */
\r
5873 #define OFS_UCBxCTLW0__SPI (0x0000u)
\r
5874 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
\r
5875 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
\r
5876 #define OFS_UCBxCTL0__SPI (0x0001u)
\r
5877 #define OFS_UCBxCTL1__SPI (0x0000u)
\r
5878 #define OFS_UCBxBRW__SPI (0x0006u)
\r
5879 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
\r
5880 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
\r
5881 #define OFS_UCBxBR0__SPI (0x0006u)
\r
5882 #define OFS_UCBxBR1__SPI (0x0007u)
\r
5883 #define OFS_UCBxSTATW__SPI (0x0008u)
\r
5884 #define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI
\r
5885 #define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1
\r
5886 #define OFS_UCBxRXBUF__SPI (0x000Cu)
\r
5887 #define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI
\r
5888 #define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1
\r
5889 #define OFS_UCBxTXBUF__SPI (0x000Eu)
\r
5890 #define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI
\r
5891 #define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1
\r
5892 #define OFS_UCBxIE__SPI (0x002Au)
\r
5893 #define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI
\r
5894 #define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1
\r
5895 #define OFS_UCBxIFG__SPI (0x002Cu)
\r
5896 #define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI
\r
5897 #define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1
\r
5898 #define OFS_UCBxIV__SPI (0x002Eu)
\r
5900 #define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */
\r
5901 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
\r
5902 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
\r
5903 #define OFS_UCBxCTL0 (0x0001u)
\r
5904 #define OFS_UCBxCTL1 (0x0000u)
\r
5905 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
\r
5906 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
\r
5907 #define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */
\r
5908 #define OFS_UCBxCTLW1_L OFS_UCBxCTLW1
\r
5909 #define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1
\r
5910 #define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */
\r
5911 #define OFS_UCBxBRW_L OFS_UCBxBRW
\r
5912 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
\r
5913 #define OFS_UCBxBR0 (0x0006u)
\r
5914 #define OFS_UCBxBR1 (0x0007u)
\r
5915 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
\r
5916 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
\r
5917 #define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */
\r
5918 #define OFS_UCBxSTATW_L OFS_UCBxSTATW
\r
5919 #define OFS_UCBxSTATW_H OFS_UCBxSTATW+1
\r
5920 #define OFS_UCBxSTATW__I2C (0x0008u)
\r
5921 #define OFS_UCBxSTAT__I2C (0x0008u)
\r
5922 #define OFS_UCBxBCNT__I2C (0x0009u)
\r
5923 #define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */
\r
5924 #define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */
\r
5925 #define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */
\r
5926 #define OFS_UCBxTBCNT_L OFS_UCBxTBCNT
\r
5927 #define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1
\r
5928 #define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */
\r
5929 #define OFS_UCBxRXBUF_L OFS_UCBxRXBUF
\r
5930 #define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1
\r
5931 #define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */
\r
5932 #define OFS_UCBxTXBUF_L OFS_UCBxTXBUF
\r
5933 #define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1
\r
5934 #define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */
\r
5935 #define OFS_UCBxI2COA0_L OFS_UCBxI2COA0
\r
5936 #define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1
\r
5937 #define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */
\r
5938 #define OFS_UCBxI2COA1_L OFS_UCBxI2COA1
\r
5939 #define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1
\r
5940 #define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */
\r
5941 #define OFS_UCBxI2COA2_L OFS_UCBxI2COA2
\r
5942 #define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1
\r
5943 #define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */
\r
5944 #define OFS_UCBxI2COA3_L OFS_UCBxI2COA3
\r
5945 #define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1
\r
5946 #define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */
\r
5947 #define OFS_UCBxADDRX_L OFS_UCBxADDRX
\r
5948 #define OFS_UCBxADDRX_H OFS_UCBxADDRX+1
\r
5949 #define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */
\r
5950 #define OFS_UCBxADDMASK_L OFS_UCBxADDMASK
\r
5951 #define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1
\r
5952 #define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */
\r
5953 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
\r
5954 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
\r
5955 #define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */
\r
5956 #define OFS_UCBxIE_L OFS_UCBxIE
\r
5957 #define OFS_UCBxIE_H OFS_UCBxIE+1
\r
5958 #define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */
\r
5959 #define OFS_UCBxIFG_L OFS_UCBxIFG
\r
5960 #define OFS_UCBxIFG_H OFS_UCBxIFG+1
\r
5961 #define OFS_UCBxIE__I2C (0x002Au)
\r
5962 #define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C
\r
5963 #define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1
\r
5964 #define OFS_UCBxIFG__I2C (0x002Cu)
\r
5965 #define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C
\r
5966 #define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1
\r
5967 #define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */
\r
5970 #if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))
\r
5972 // UCAxCTLW0 UART-Mode Control Bits
\r
5973 #define UCPEN (0x8000u) /* Async. Mode: Parity enable */
\r
5974 #define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */
\r
5975 #define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */
\r
5976 #define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
\r
5977 #define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */
\r
5978 #define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */
\r
5979 #define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */
\r
5980 #define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
\r
5981 #define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */
\r
5982 #define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */
\r
5983 #define UCRXEIE (0x0020u) /* RX Error interrupt enable */
\r
5984 #define UCBRKIE (0x0010u) /* Break interrupt enable */
\r
5985 #define UCDORM (0x0008u) /* Dormant (Sleep) Mode */
\r
5986 #define UCTXADDR (0x0004u) /* Send next Data as Address */
\r
5987 #define UCTXBRK (0x0002u) /* Send next Data as Break */
\r
5988 #define UCSWRST (0x0001u) /* USCI Software Reset */
\r
5990 // UCAxCTLW0 UART-Mode Control Bits
\r
5991 #define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */
\r
5992 #define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */
\r
5993 #define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */
\r
5994 #define UCBRKIE_L (0x0010u) /* Break interrupt enable */
\r
5995 #define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */
\r
5996 #define UCTXADDR_L (0x0004u) /* Send next Data as Address */
\r
5997 #define UCTXBRK_L (0x0002u) /* Send next Data as Break */
\r
5998 #define UCSWRST_L (0x0001u) /* USCI Software Reset */
\r
6000 // UCAxCTLW0 UART-Mode Control Bits
\r
6001 #define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */
\r
6002 #define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */
\r
6003 #define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */
\r
6004 #define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
\r
6005 #define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */
\r
6006 #define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */
\r
6007 #define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */
\r
6008 #define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
\r
6010 // UCxxCTLW0 SPI-Mode Control Bits
\r
6011 #define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */
\r
6012 #define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */
\r
6013 #define UCMST (0x0800u) /* Sync. Mode: Master Select */
\r
6014 //#define res (0x0020u) /* reserved */
\r
6015 //#define res (0x0010u) /* reserved */
\r
6016 //#define res (0x0008u) /* reserved */
\r
6017 //#define res (0x0004u) /* reserved */
\r
6018 #define UCSTEM (0x0002u) /* USCI STE Mode */
\r
6020 // UCBxCTLW0 I2C-Mode Control Bits
\r
6021 #define UCA10 (0x8000u) /* 10-bit Address Mode */
\r
6022 #define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */
\r
6023 #define UCMM (0x2000u) /* Multi-Master Environment */
\r
6024 //#define res (0x1000u) /* reserved */
\r
6025 //#define res (0x0100u) /* reserved */
\r
6026 #define UCTXACK (0x0020u) /* Transmit ACK */
\r
6027 #define UCTR (0x0010u) /* Transmit/Receive Select/Flag */
\r
6028 #define UCTXNACK (0x0008u) /* Transmit NACK */
\r
6029 #define UCTXSTP (0x0004u) /* Transmit STOP */
\r
6030 #define UCTXSTT (0x0002u) /* Transmit START */
\r
6032 // UCBxCTLW0 I2C-Mode Control Bits
\r
6033 //#define res (0x1000u) /* reserved */
\r
6034 //#define res (0x0100u) /* reserved */
\r
6035 #define UCTXACK_L (0x0020u) /* Transmit ACK */
\r
6036 #define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */
\r
6037 #define UCTXNACK_L (0x0008u) /* Transmit NACK */
\r
6038 #define UCTXSTP_L (0x0004u) /* Transmit STOP */
\r
6039 #define UCTXSTT_L (0x0002u) /* Transmit START */
\r
6041 // UCBxCTLW0 I2C-Mode Control Bits
\r
6042 #define UCA10_H (0x0080u) /* 10-bit Address Mode */
\r
6043 #define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */
\r
6044 #define UCMM_H (0x0020u) /* Multi-Master Environment */
\r
6045 //#define res (0x1000u) /* reserved */
\r
6046 //#define res (0x0100u) /* reserved */
\r
6048 #define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */
\r
6049 #define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */
\r
6050 #define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */
\r
6051 #define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */
\r
6053 #define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */
\r
6054 #define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */
\r
6055 #define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */
\r
6056 #define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */
\r
6057 #define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */
\r
6058 #define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */
\r
6059 #define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */
\r
6061 // UCAxCTLW1 UART-Mode Control Bits
\r
6062 #define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */
\r
6063 #define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */
\r
6065 // UCAxCTLW1 UART-Mode Control Bits
\r
6066 #define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */
\r
6067 #define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */
\r
6069 // UCBxCTLW1 I2C-Mode Control Bits
\r
6070 #define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */
\r
6071 #define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */
\r
6072 #define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */
\r
6073 #define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */
\r
6074 #define UCSWACK (0x0010u) /* USCI Software controlled ACK */
\r
6075 #define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */
\r
6076 #define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */
\r
6077 #define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */
\r
6078 #define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */
\r
6080 // UCBxCTLW1 I2C-Mode Control Bits
\r
6081 #define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */
\r
6082 #define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */
\r
6083 #define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */
\r
6084 #define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */
\r
6085 #define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */
\r
6086 #define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */
\r
6087 #define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */
\r
6088 #define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */
\r
6090 // UCBxCTLW1 I2C-Mode Control Bits
\r
6091 #define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */
\r
6093 #define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */
\r
6094 #define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */
\r
6095 #define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */
\r
6096 #define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */
\r
6098 #define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */
\r
6099 #define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */
\r
6100 #define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */
\r
6101 #define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */
\r
6103 #define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */
\r
6104 #define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */
\r
6105 #define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */
\r
6106 #define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */
\r
6108 /* UCAxMCTLW Control Bits */
\r
6109 #define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */
\r
6110 #define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */
\r
6111 #define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */
\r
6112 #define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */
\r
6113 #define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */
\r
6114 #define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */
\r
6115 #define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */
\r
6116 #define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */
\r
6117 #define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */
\r
6118 #define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */
\r
6119 #define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */
\r
6120 #define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */
\r
6121 #define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */
\r
6123 /* UCAxMCTLW Control Bits */
\r
6124 #define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */
\r
6125 #define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */
\r
6126 #define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */
\r
6127 #define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */
\r
6128 #define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */
\r
6130 /* UCAxMCTLW Control Bits */
\r
6131 #define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */
\r
6132 #define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */
\r
6133 #define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */
\r
6134 #define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */
\r
6135 #define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */
\r
6136 #define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */
\r
6137 #define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */
\r
6138 #define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */
\r
6140 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
\r
6141 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
\r
6142 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
\r
6143 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
\r
6144 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
\r
6145 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
\r
6146 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
\r
6147 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
\r
6148 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
\r
6149 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
\r
6150 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
\r
6151 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
\r
6152 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
\r
6153 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
\r
6154 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
\r
6155 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
\r
6157 /* UCAxSTATW Control Bits */
\r
6158 #define UCLISTEN (0x0080u) /* USCI Listen mode */
\r
6159 #define UCFE (0x0040u) /* USCI Frame Error Flag */
\r
6160 #define UCOE (0x0020u) /* USCI Overrun Error Flag */
\r
6161 #define UCPE (0x0010u) /* USCI Parity Error Flag */
\r
6162 #define UCBRK (0x0008u) /* USCI Break received */
\r
6163 #define UCRXERR (0x0004u) /* USCI RX Error Flag */
\r
6164 #define UCADDR (0x0002u) /* USCI Address received Flag */
\r
6165 #define UCBUSY (0x0001u) /* USCI Busy Flag */
\r
6166 #define UCIDLE (0x0002u) /* USCI Idle line detected Flag */
\r
6168 /* UCBxSTATW I2C Control Bits */
\r
6169 #define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */
\r
6170 #define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */
\r
6171 #define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */
\r
6172 #define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */
\r
6173 #define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */
\r
6174 #define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */
\r
6175 #define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */
\r
6176 #define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */
\r
6177 #define UCSCLLOW (0x0040u) /* SCL low */
\r
6178 #define UCGC (0x0020u) /* General Call address received Flag */
\r
6179 #define UCBBUSY (0x0010u) /* Bus Busy Flag */
\r
6181 /* UCBxTBCNT I2C Control Bits */
\r
6182 #define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */
\r
6183 #define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */
\r
6184 #define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */
\r
6185 #define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */
\r
6186 #define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */
\r
6187 #define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */
\r
6188 #define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */
\r
6189 #define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */
\r
6191 /* UCAxIRCTL Control Bits */
\r
6192 #define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */
\r
6193 #define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */
\r
6194 #define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */
\r
6195 #define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */
\r
6196 #define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */
\r
6197 #define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */
\r
6198 #define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */
\r
6199 #define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */
\r
6200 #define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */
\r
6201 #define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */
\r
6202 #define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */
\r
6203 #define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */
\r
6204 #define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */
\r
6205 #define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */
\r
6206 #define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */
\r
6207 #define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */
\r
6209 /* UCAxIRCTL Control Bits */
\r
6210 #define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */
\r
6211 #define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */
\r
6212 #define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */
\r
6213 #define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */
\r
6214 #define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */
\r
6215 #define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */
\r
6216 #define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */
\r
6217 #define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */
\r
6219 /* UCAxIRCTL Control Bits */
\r
6220 #define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */
\r
6221 #define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */
\r
6222 #define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */
\r
6223 #define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */
\r
6224 #define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */
\r
6225 #define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */
\r
6226 #define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */
\r
6227 #define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */
\r
6229 /* UCAxABCTL Control Bits */
\r
6230 //#define res (0x80) /* reserved */
\r
6231 //#define res (0x40) /* reserved */
\r
6232 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
\r
6233 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
\r
6234 #define UCSTOE (0x08) /* Sync-Field Timeout error */
\r
6235 #define UCBTOE (0x04) /* Break Timeout error */
\r
6236 //#define res (0x02) /* reserved */
\r
6237 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
\r
6239 /* UCBxI2COA0 Control Bits */
\r
6240 #define UCGCEN (0x8000u) /* I2C General Call enable */
\r
6241 #define UCOAEN (0x0400u) /* I2C Own Address enable */
\r
6242 #define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */
\r
6243 #define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */
\r
6244 #define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */
\r
6245 #define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */
\r
6246 #define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */
\r
6247 #define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */
\r
6248 #define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */
\r
6249 #define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */
\r
6250 #define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */
\r
6251 #define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */
\r
6253 /* UCBxI2COA0 Control Bits */
\r
6254 #define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */
\r
6255 #define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */
\r
6256 #define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */
\r
6257 #define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */
\r
6258 #define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */
\r
6259 #define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */
\r
6260 #define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */
\r
6261 #define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */
\r
6263 /* UCBxI2COA0 Control Bits */
\r
6264 #define UCGCEN_H (0x0080u) /* I2C General Call enable */
\r
6265 #define UCOAEN_H (0x0004u) /* I2C Own Address enable */
\r
6266 #define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */
\r
6267 #define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */
\r
6269 /* UCBxI2COAx Control Bits */
\r
6270 #define UCOAEN (0x0400u) /* I2C Own Address enable */
\r
6271 #define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */
\r
6272 #define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */
\r
6273 #define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */
\r
6274 #define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */
\r
6275 #define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */
\r
6276 #define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */
\r
6277 #define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */
\r
6278 #define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */
\r
6279 #define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */
\r
6280 #define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */
\r
6282 /* UCBxI2COAx Control Bits */
\r
6283 #define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */
\r
6284 #define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */
\r
6285 #define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */
\r
6286 #define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */
\r
6287 #define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */
\r
6288 #define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */
\r
6289 #define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */
\r
6290 #define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */
\r
6292 /* UCBxI2COAx Control Bits */
\r
6293 #define UCOAEN_H (0x0004u) /* I2C Own Address enable */
\r
6294 #define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */
\r
6295 #define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */
\r
6297 /* UCBxADDRX Control Bits */
\r
6298 #define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */
\r
6299 #define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */
\r
6300 #define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */
\r
6301 #define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */
\r
6302 #define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */
\r
6303 #define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */
\r
6304 #define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */
\r
6305 #define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */
\r
6306 #define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */
\r
6307 #define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */
\r
6309 /* UCBxADDRX Control Bits */
\r
6310 #define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */
\r
6311 #define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */
\r
6312 #define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */
\r
6313 #define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */
\r
6314 #define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */
\r
6315 #define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */
\r
6316 #define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */
\r
6317 #define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */
\r
6319 /* UCBxADDRX Control Bits */
\r
6320 #define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */
\r
6321 #define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */
\r
6323 /* UCBxADDMASK Control Bits */
\r
6324 #define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */
\r
6325 #define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */
\r
6326 #define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */
\r
6327 #define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */
\r
6328 #define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */
\r
6329 #define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */
\r
6330 #define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */
\r
6331 #define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */
\r
6332 #define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */
\r
6333 #define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */
\r
6335 /* UCBxADDMASK Control Bits */
\r
6336 #define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */
\r
6337 #define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */
\r
6338 #define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */
\r
6339 #define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */
\r
6340 #define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */
\r
6341 #define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */
\r
6342 #define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */
\r
6343 #define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */
\r
6345 /* UCBxADDMASK Control Bits */
\r
6346 #define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */
\r
6347 #define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */
\r
6349 /* UCBxI2CSA Control Bits */
\r
6350 #define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */
\r
6351 #define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */
\r
6352 #define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */
\r
6353 #define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */
\r
6354 #define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */
\r
6355 #define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */
\r
6356 #define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */
\r
6357 #define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */
\r
6358 #define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */
\r
6359 #define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */
\r
6361 /* UCBxI2CSA Control Bits */
\r
6362 #define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */
\r
6363 #define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */
\r
6364 #define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */
\r
6365 #define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */
\r
6366 #define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */
\r
6367 #define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */
\r
6368 #define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */
\r
6369 #define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */
\r
6371 /* UCBxI2CSA Control Bits */
\r
6372 #define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */
\r
6373 #define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */
\r
6375 /* UCAxIE UART Control Bits */
\r
6376 #define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */
\r
6377 #define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */
\r
6378 #define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */
\r
6379 #define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */
\r
6381 /* UCAxIE/UCBxIE SPI Control Bits */
\r
6383 /* UCBxIE I2C Control Bits */
\r
6384 #define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */
\r
6385 #define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */
\r
6386 #define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */
\r
6387 #define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */
\r
6388 #define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */
\r
6389 #define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */
\r
6390 #define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */
\r
6391 #define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */
\r
6392 #define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */
\r
6393 #define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */
\r
6394 #define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */
\r
6395 #define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */
\r
6396 #define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */
\r
6397 #define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */
\r
6398 #define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */
\r
6400 /* UCAxIFG UART Control Bits */
\r
6401 #define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */
\r
6402 #define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */
\r
6403 #define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */
\r
6404 #define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */
\r
6406 /* UCAxIFG/UCBxIFG SPI Control Bits */
\r
6407 #define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */
\r
6408 #define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */
\r
6410 /* UCBxIFG Control Bits */
\r
6411 #define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */
\r
6412 #define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */
\r
6413 #define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */
\r
6414 #define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */
\r
6415 #define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */
\r
6416 #define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */
\r
6417 #define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */
\r
6418 #define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */
\r
6419 #define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */
\r
6420 #define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */
\r
6421 #define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */
\r
6422 #define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */
\r
6423 #define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */
\r
6424 #define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */
\r
6425 #define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */
\r
6427 /* USCI UART Definitions */
\r
6428 #define USCI_NONE (0x0000u) /* No Interrupt pending */
\r
6429 #define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */
\r
6430 #define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */
\r
6431 #define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */
\r
6432 #define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */
\r
6434 /* USCI SPI Definitions */
\r
6435 #define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */
\r
6436 #define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */
\r
6438 /* USCI I2C Definitions */
\r
6439 #define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */
\r
6440 #define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */
\r
6441 #define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/
\r
6442 #define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/
\r
6443 #define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */
\r
6444 #define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */
\r
6445 #define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */
\r
6446 #define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */
\r
6447 #define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */
\r
6448 #define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */
\r
6449 #define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */
\r
6450 #define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */
\r
6451 #define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */
\r
6452 #define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */
\r
6453 #define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */
\r
6456 /************************************************************
\r
6457 * WATCHDOG TIMER A
\r
6458 ************************************************************/
\r
6459 #ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
\r
6461 #define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */
\r
6462 #define OFS_WDTCTL_L OFS_WDTCTL
\r
6463 #define OFS_WDTCTL_H OFS_WDTCTL+1
\r
6464 /* The bit names have been prefixed with "WDT" */
\r
6465 /* WDTCTL Control Bits */
\r
6466 #define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */
\r
6467 #define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */
\r
6468 #define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */
\r
6469 #define WDTCNTCL (0x0008u) /* WDT - Timer Clear */
\r
6470 #define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */
\r
6471 #define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */
\r
6472 #define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */
\r
6473 #define WDTHOLD (0x0080u) /* WDT - Timer hold */
\r
6475 /* WDTCTL Control Bits */
\r
6476 #define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */
\r
6477 #define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */
\r
6478 #define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */
\r
6479 #define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */
\r
6480 #define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */
\r
6481 #define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */
\r
6482 #define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */
\r
6483 #define WDTHOLD_L (0x0080u) /* WDT - Timer hold */
\r
6485 #define WDTPW (0x5A00u)
\r
6487 #define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
\r
6488 #define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
\r
6489 #define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
\r
6490 #define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
\r
6491 #define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
\r
6492 #define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
\r
6493 #define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
\r
6494 #define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
\r
6495 #define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
\r
6496 #define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
\r
6497 #define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
\r
6498 #define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
\r
6499 #define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
\r
6500 #define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
\r
6501 #define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
\r
6502 #define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
\r
6504 #define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
\r
6505 #define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
\r
6506 #define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
\r
6507 #define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
\r
6508 #define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
\r
6509 #define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
\r
6510 #define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
\r
6512 /* WDT-interval times [1ms] coded with Bits 0-2 */
\r
6513 /* WDT is clocked by fSMCLK (assumed 1MHz) */
\r
6514 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
\r
6515 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
\r
6516 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
\r
6517 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
\r
6518 /* WDT is clocked by fACLK (assumed 32KHz) */
\r
6519 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
\r
6520 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
\r
6521 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
\r
6522 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
\r
6523 /* Watchdog mode -> reset after expired time */
\r
6524 /* WDT is clocked by fSMCLK (assumed 1MHz) */
\r
6525 #define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
\r
6526 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
\r
6527 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
\r
6528 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
\r
6529 /* WDT is clocked by fACLK (assumed 32KHz) */
\r
6530 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
\r
6531 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
\r
6532 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
\r
6533 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
\r
6537 /************************************************************
\r
6539 ************************************************************/
\r
6540 #define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
\r
6541 #define TLV_BASE __MSP430_BASEADDRESS_TLV__
\r
6543 #define TLV_START (0x1A08u) /* Start Address of the TLV structure */
\r
6544 #define TLV_END (0x1AFFu) /* End Address of the TLV structure */
\r
6546 #define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
\r
6547 #define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
\r
6548 #define TLV_Reserved3 (0x03) /* Future usage */
\r
6549 #define TLV_Reserved4 (0x04) /* Future usage */
\r
6550 #define TLV_BLANK (0x05) /* Blank descriptor */
\r
6551 #define TLV_Reserved6 (0x06) /* Future usage */
\r
6552 #define TLV_Reserved7 (0x07) /* Serial Number */
\r
6553 #define TLV_DIERECORD (0x08) /* Die Record */
\r
6554 #define TLV_ADCCAL (0x11) /* ADC12 calibration */
\r
6555 #define TLV_ADC12CAL (0x11) /* ADC12 calibration */
\r
6556 #define TLV_REFCAL (0x12) /* REF calibration */
\r
6557 #define TLV_ADC10CAL (0x13) /* ADC10 calibration */
\r
6558 #define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */
\r
6559 #define TLV_TAGEXT (0xFE) /* Tag extender */
\r
6560 #define TLV_TAGEND (0xFF) /* Tag End of Table */
\r
6562 /************************************************************
\r
6563 * Interrupt Vectors (offset from 0xFF80)
\r
6564 ************************************************************/
\r
6567 /************************************************************
\r
6569 ************************************************************/
\r
6570 #pragma language=default
\r
6572 #endif /* #ifndef __msp430FR5XX_FR6XXGENERIC */
\r
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