1 /*******************************************************************************
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2 * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
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4 * SVN $Revision: 5258 $
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5 * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
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9 .global HW_set_32bit_reg
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10 .global HW_get_32bit_reg
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11 .global HW_set_32bit_reg_field
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12 .global HW_get_32bit_reg_field
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13 .global HW_set_16bit_reg
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14 .global HW_get_16bit_reg
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15 .global HW_set_16bit_reg_field
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16 .global HW_get_16bit_reg_field
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17 .global HW_set_8bit_reg
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18 .global HW_get_8bit_reg
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19 .global HW_set_8bit_reg_field
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20 .global HW_get_8bit_reg_field
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23 .type HW_set_32bit_reg, function
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24 .type HW_get_32bit_reg, function
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25 .type HW_set_32bit_reg_field, function
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26 .type HW_get_32bit_reg_field, function
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27 .type HW_set_16bit_reg, function
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28 .type HW_get_16bit_reg, function
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29 .type HW_set_16bit_reg_field, function
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30 .type HW_get_16bit_reg_field, function
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31 .type HW_set_8bit_reg, function
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32 .type HW_get_8bit_reg, function
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33 .type HW_set_8bit_reg_field, function
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34 .type HW_get_8bit_reg_field, function
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36 /*------------------------------------------------------------------------------
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37 * R0: addr_t reg_addr
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38 * R1: uint32_t value
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44 /*------------------------------------------------------------------------------
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45 * R0: addr_t reg_addr
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51 /*------------------------------------------------------------------------------
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52 * R0: addr_t reg_addr
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53 * R1: int_fast8_t shift
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55 * R3: uint32_t value
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57 HW_set_32bit_reg_field:
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68 /*------------------------------------------------------------------------------
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69 * R0: addr_t reg_addr
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70 * R1: int_fast8_t shift
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73 HW_get_32bit_reg_field:
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79 /*------------------------------------------------------------------------------
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80 * R0: addr_t reg_addr
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81 * R1: uint_fast16_t value
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87 /*------------------------------------------------------------------------------
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88 * R0: addr_t reg_addr
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94 /*------------------------------------------------------------------------------
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95 * R0: addr_t reg_addr
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96 * R1: int_fast8_t shift
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97 * R2: uint_fast16_t mask
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98 * R3: uint_fast16_t value
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100 HW_set_16bit_reg_field:
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111 /*------------------------------------------------------------------------------
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112 * R0: addr_t reg_addr
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113 * R1: int_fast8_t shift
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114 * R2: uint_fast16_t mask
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116 HW_get_16bit_reg_field:
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122 /*------------------------------------------------------------------------------
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123 * R0: addr_t reg_addr
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124 * R1: uint_fast8_t value
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130 /*------------------------------------------------------------------------------
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131 * R0: addr_t reg_addr
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137 /*------------------------------------------------------------------------------
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138 * R0: addr_t reg_addr,
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139 * R1: int_fast8_t shift
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140 * R2: uint_fast8_t mask
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141 * R3: uint_fast8_t value
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143 HW_set_8bit_reg_field:
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154 /*------------------------------------------------------------------------------
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155 * R0: addr_t reg_addr
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156 * R1: int_fast8_t shift
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157 * R2: uint_fast8_t mask
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159 HW_get_8bit_reg_field:
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