1 /**************************************************************************//**
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2 * @file efm32gg_uart.h
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3 * @brief EFM32GG_UART register and bit field definitions
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5 ******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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33 /**************************************************************************//**
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34 * @defgroup EFM32GG_UART_BitFields
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36 *****************************************************************************/
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38 /* Bit fields for UART CTRL */
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39 #define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */
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40 #define _UART_CTRL_MASK 0x7DFFFF7FUL /**< Mask for UART_CTRL */
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41 #define UART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
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42 #define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
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43 #define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
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44 #define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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45 #define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRL */
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46 #define UART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
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47 #define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
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48 #define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
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49 #define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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50 #define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRL */
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51 #define UART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
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52 #define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
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53 #define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
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54 #define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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55 #define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRL */
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56 #define UART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
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57 #define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
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58 #define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
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59 #define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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60 #define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRL */
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61 #define UART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
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62 #define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
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63 #define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
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64 #define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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65 #define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CTRL */
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66 #define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
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67 #define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
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68 #define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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69 #define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */
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70 #define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */
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71 #define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */
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72 #define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */
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73 #define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CTRL */
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74 #define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for UART_CTRL */
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75 #define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for UART_CTRL */
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76 #define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for UART_CTRL */
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77 #define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for UART_CTRL */
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78 #define UART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
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79 #define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
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80 #define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
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81 #define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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82 #define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */
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83 #define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */
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84 #define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CTRL */
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85 #define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for UART_CTRL */
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86 #define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */
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87 #define UART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
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88 #define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
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89 #define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
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90 #define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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91 #define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */
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92 #define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */
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93 #define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CTRL */
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94 #define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */
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95 #define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */
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96 #define UART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
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97 #define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
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98 #define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
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99 #define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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100 #define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CTRL */
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101 #define UART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
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102 #define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
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103 #define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
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104 #define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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105 #define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */
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106 #define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */
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107 #define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CTRL */
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108 #define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for UART_CTRL */
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109 #define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */
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110 #define UART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
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111 #define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
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112 #define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
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113 #define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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114 #define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */
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115 #define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */
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116 #define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_CTRL */
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117 #define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for UART_CTRL */
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118 #define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for UART_CTRL */
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119 #define UART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
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120 #define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
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121 #define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
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122 #define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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123 #define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_CTRL */
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124 #define UART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
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125 #define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
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126 #define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
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127 #define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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128 #define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_CTRL */
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129 #define UART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
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130 #define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
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131 #define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
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132 #define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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133 #define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_CTRL */
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134 #define UART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
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135 #define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
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136 #define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
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137 #define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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138 #define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_CTRL */
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139 #define UART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
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140 #define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
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141 #define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
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142 #define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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143 #define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for UART_CTRL */
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144 #define UART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
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145 #define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
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146 #define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
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147 #define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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148 #define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for UART_CTRL */
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149 #define UART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
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150 #define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
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151 #define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
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152 #define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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153 #define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for UART_CTRL */
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154 #define UART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
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155 #define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
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156 #define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
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157 #define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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158 #define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_CTRL */
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159 #define UART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
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160 #define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
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161 #define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
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162 #define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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163 #define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for UART_CTRL */
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164 #define UART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
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165 #define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
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166 #define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
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167 #define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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168 #define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for UART_CTRL */
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169 #define UART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
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170 #define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
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171 #define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
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172 #define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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173 #define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for UART_CTRL */
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174 #define UART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
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175 #define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
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176 #define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
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177 #define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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178 #define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_CTRL */
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179 #define _UART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */
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180 #define _UART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */
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181 #define _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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182 #define _UART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for UART_CTRL */
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183 #define _UART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for UART_CTRL */
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184 #define _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for UART_CTRL */
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185 #define _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for UART_CTRL */
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186 #define UART_CTRL_TXDELAY_DEFAULT (_UART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for UART_CTRL */
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187 #define UART_CTRL_TXDELAY_NONE (_UART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for UART_CTRL */
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188 #define UART_CTRL_TXDELAY_SINGLE (_UART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for UART_CTRL */
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189 #define UART_CTRL_TXDELAY_DOUBLE (_UART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for UART_CTRL */
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190 #define UART_CTRL_TXDELAY_TRIPLE (_UART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for UART_CTRL */
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191 #define UART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
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192 #define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
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193 #define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
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194 #define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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195 #define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_CTRL */
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196 #define UART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
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197 #define _UART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
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198 #define _UART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
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199 #define _UART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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200 #define UART_CTRL_AUTOTX_DEFAULT (_UART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_CTRL */
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201 #define UART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
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202 #define _UART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
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203 #define _UART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
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204 #define _UART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
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205 #define UART_CTRL_MVDIS_DEFAULT (_UART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_CTRL */
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207 /* Bit fields for UART FRAME */
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208 #define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */
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209 #define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */
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210 #define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
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211 #define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
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212 #define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */
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213 #define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */
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214 #define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */
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215 #define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */
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216 #define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */
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217 #define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */
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218 #define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */
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219 #define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */
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220 #define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */
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221 #define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */
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222 #define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */
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223 #define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */
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224 #define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */
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225 #define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */
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226 #define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for UART_FRAME */
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227 #define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for UART_FRAME */
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228 #define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for UART_FRAME */
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229 #define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for UART_FRAME */
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230 #define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_FRAME */
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231 #define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for UART_FRAME */
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232 #define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for UART_FRAME */
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233 #define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for UART_FRAME */
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234 #define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for UART_FRAME */
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235 #define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for UART_FRAME */
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236 #define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for UART_FRAME */
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237 #define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for UART_FRAME */
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238 #define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for UART_FRAME */
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239 #define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for UART_FRAME */
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240 #define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
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241 #define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
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242 #define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */
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243 #define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */
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244 #define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */
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245 #define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */
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246 #define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_FRAME */
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247 #define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for UART_FRAME */
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248 #define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for UART_FRAME */
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249 #define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for UART_FRAME */
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250 #define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
\r
251 #define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
\r
252 #define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */
\r
253 #define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */
\r
254 #define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */
\r
255 #define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */
\r
256 #define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */
\r
257 #define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for UART_FRAME */
\r
258 #define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_FRAME */
\r
259 #define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for UART_FRAME */
\r
260 #define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */
\r
261 #define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for UART_FRAME */
\r
263 /* Bit fields for UART TRIGCTRL */
\r
264 #define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */
\r
265 #define _UART_TRIGCTRL_MASK 0x00000077UL /**< Mask for UART_TRIGCTRL */
\r
266 #define _UART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */
\r
267 #define _UART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */
\r
268 #define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
\r
269 #define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */
\r
270 #define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */
\r
271 #define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */
\r
272 #define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */
\r
273 #define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */
\r
274 #define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */
\r
275 #define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */
\r
276 #define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */
\r
277 #define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
\r
278 #define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */
\r
279 #define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */
\r
280 #define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */
\r
281 #define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */
\r
282 #define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */
\r
283 #define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */
\r
284 #define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */
\r
285 #define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */
\r
286 #define UART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
\r
287 #define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
\r
288 #define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
\r
289 #define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
\r
290 #define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
\r
291 #define UART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
\r
292 #define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
\r
293 #define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
\r
294 #define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
\r
295 #define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
\r
296 #define UART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
\r
297 #define _UART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
\r
298 #define _UART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
\r
299 #define _UART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
\r
300 #define UART_TRIGCTRL_AUTOTXTEN_DEFAULT (_UART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
\r
302 /* Bit fields for UART CMD */
\r
303 #define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */
\r
304 #define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */
\r
305 #define UART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
\r
306 #define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
\r
307 #define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
\r
308 #define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
309 #define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CMD */
\r
310 #define UART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
\r
311 #define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
\r
312 #define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
\r
313 #define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
314 #define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CMD */
\r
315 #define UART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
\r
316 #define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
\r
317 #define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
\r
318 #define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
319 #define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CMD */
\r
320 #define UART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
\r
321 #define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
\r
322 #define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
\r
323 #define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
324 #define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CMD */
\r
325 #define UART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
\r
326 #define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
\r
327 #define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
\r
328 #define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
329 #define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CMD */
\r
330 #define UART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
\r
331 #define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
\r
332 #define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
\r
333 #define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
334 #define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CMD */
\r
335 #define UART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
\r
336 #define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
\r
337 #define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
\r
338 #define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
339 #define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CMD */
\r
340 #define UART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
\r
341 #define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
\r
342 #define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
\r
343 #define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
344 #define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_CMD */
\r
345 #define UART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
\r
346 #define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
\r
347 #define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
\r
348 #define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
349 #define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CMD */
\r
350 #define UART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
\r
351 #define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
\r
352 #define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
\r
353 #define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
354 #define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CMD */
\r
355 #define UART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
\r
356 #define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
\r
357 #define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
\r
358 #define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
359 #define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CMD */
\r
360 #define UART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
\r
361 #define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
\r
362 #define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
\r
363 #define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
\r
364 #define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CMD */
\r
366 /* Bit fields for UART STATUS */
\r
367 #define _UART_STATUS_RESETVALUE 0x00000040UL /**< Default value for UART_STATUS */
\r
368 #define _UART_STATUS_MASK 0x00001FFFUL /**< Mask for UART_STATUS */
\r
369 #define UART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
\r
370 #define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
\r
371 #define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
\r
372 #define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
373 #define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_STATUS */
\r
374 #define UART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
\r
375 #define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
\r
376 #define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
\r
377 #define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
378 #define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_STATUS */
\r
379 #define UART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
\r
380 #define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
\r
381 #define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
\r
382 #define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
383 #define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_STATUS */
\r
384 #define UART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
\r
385 #define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
\r
386 #define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
\r
387 #define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
388 #define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_STATUS */
\r
389 #define UART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
\r
390 #define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
\r
391 #define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
\r
392 #define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
393 #define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_STATUS */
\r
394 #define UART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
\r
395 #define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
\r
396 #define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
\r
397 #define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
398 #define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_STATUS */
\r
399 #define UART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
\r
400 #define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
\r
401 #define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
\r
402 #define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */
\r
403 #define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_STATUS */
\r
404 #define UART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
\r
405 #define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
\r
406 #define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
\r
407 #define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
408 #define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_STATUS */
\r
409 #define UART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
\r
410 #define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
\r
411 #define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
\r
412 #define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
413 #define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_STATUS */
\r
414 #define UART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
\r
415 #define _UART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
\r
416 #define _UART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
\r
417 #define _UART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
418 #define UART_STATUS_TXBDRIGHT_DEFAULT (_UART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_STATUS */
\r
419 #define UART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
\r
420 #define _UART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
\r
421 #define _UART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
\r
422 #define _UART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
423 #define UART_STATUS_TXBSRIGHT_DEFAULT (_UART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_STATUS */
\r
424 #define UART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
\r
425 #define _UART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
\r
426 #define _UART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
\r
427 #define _UART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
428 #define UART_STATUS_RXDATAVRIGHT_DEFAULT (_UART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_STATUS */
\r
429 #define UART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
\r
430 #define _UART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
\r
431 #define _UART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
\r
432 #define _UART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
\r
433 #define UART_STATUS_RXFULLRIGHT_DEFAULT (_UART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_STATUS */
\r
435 /* Bit fields for UART CLKDIV */
\r
436 #define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */
\r
437 #define _UART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for UART_CLKDIV */
\r
438 #define _UART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */
\r
439 #define _UART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */
\r
440 #define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */
\r
441 #define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CLKDIV */
\r
443 /* Bit fields for UART RXDATAX */
\r
444 #define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */
\r
445 #define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */
\r
446 #define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
\r
447 #define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
\r
448 #define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
\r
449 #define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */
\r
450 #define UART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
\r
451 #define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
\r
452 #define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
\r
453 #define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
\r
454 #define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */
\r
455 #define UART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
\r
456 #define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
\r
457 #define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
\r
458 #define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
\r
459 #define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */
\r
461 /* Bit fields for UART RXDATA */
\r
462 #define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */
\r
463 #define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */
\r
464 #define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
\r
465 #define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
\r
466 #define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */
\r
467 #define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATA */
\r
469 /* Bit fields for UART RXDOUBLEX */
\r
470 #define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */
\r
471 #define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */
\r
472 #define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
\r
473 #define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
\r
474 #define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
\r
475 #define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
\r
476 #define UART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
\r
477 #define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
\r
478 #define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
\r
479 #define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
\r
480 #define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
\r
481 #define UART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
\r
482 #define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
\r
483 #define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
\r
484 #define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
\r
485 #define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
\r
486 #define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
\r
487 #define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
\r
488 #define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
\r
489 #define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
\r
490 #define UART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
\r
491 #define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
\r
492 #define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
\r
493 #define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
\r
494 #define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
\r
495 #define UART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
\r
496 #define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
\r
497 #define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
\r
498 #define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
\r
499 #define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
\r
501 /* Bit fields for UART RXDOUBLE */
\r
502 #define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */
\r
503 #define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */
\r
504 #define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
\r
505 #define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
\r
506 #define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
\r
507 #define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
\r
508 #define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
\r
509 #define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
\r
510 #define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
\r
511 #define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
\r
513 /* Bit fields for UART RXDATAXP */
\r
514 #define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */
\r
515 #define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */
\r
516 #define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
\r
517 #define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
\r
518 #define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
\r
519 #define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */
\r
520 #define UART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
\r
521 #define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
\r
522 #define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
\r
523 #define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
\r
524 #define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */
\r
525 #define UART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
\r
526 #define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
\r
527 #define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
\r
528 #define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
\r
529 #define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */
\r
531 /* Bit fields for UART RXDOUBLEXP */
\r
532 #define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */
\r
533 #define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */
\r
534 #define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
\r
535 #define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
\r
536 #define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
\r
537 #define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
\r
538 #define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
\r
539 #define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
\r
540 #define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
\r
541 #define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
\r
542 #define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
\r
543 #define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
\r
544 #define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
\r
545 #define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
\r
546 #define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
\r
547 #define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
\r
548 #define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
\r
549 #define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
\r
550 #define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
\r
551 #define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
\r
552 #define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
\r
553 #define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
\r
554 #define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
\r
555 #define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
\r
556 #define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
\r
557 #define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
\r
558 #define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
\r
559 #define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
\r
560 #define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
\r
561 #define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
\r
563 /* Bit fields for UART TXDATAX */
\r
564 #define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */
\r
565 #define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */
\r
566 #define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
\r
567 #define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
\r
568 #define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
\r
569 #define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */
\r
570 #define UART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
\r
571 #define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
\r
572 #define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
\r
573 #define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
\r
574 #define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */
\r
575 #define UART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
\r
576 #define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
\r
577 #define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
\r
578 #define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
\r
579 #define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */
\r
580 #define UART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
\r
581 #define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
\r
582 #define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
\r
583 #define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
\r
584 #define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */
\r
585 #define UART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
\r
586 #define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
\r
587 #define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
\r
588 #define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
\r
589 #define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */
\r
590 #define UART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
\r
591 #define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
\r
592 #define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
\r
593 #define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
\r
594 #define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */
\r
596 /* Bit fields for UART TXDATA */
\r
597 #define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */
\r
598 #define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */
\r
599 #define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
\r
600 #define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
\r
601 #define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */
\r
602 #define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATA */
\r
604 /* Bit fields for UART TXDOUBLEX */
\r
605 #define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */
\r
606 #define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */
\r
607 #define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
\r
608 #define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
\r
609 #define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
610 #define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
611 #define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
\r
612 #define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
\r
613 #define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
\r
614 #define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
615 #define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
616 #define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
\r
617 #define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
\r
618 #define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
\r
619 #define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
620 #define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
621 #define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
\r
622 #define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
\r
623 #define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
\r
624 #define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
625 #define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
626 #define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
\r
627 #define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
\r
628 #define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
\r
629 #define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
630 #define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
631 #define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
\r
632 #define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
\r
633 #define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
\r
634 #define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
635 #define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
636 #define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
\r
637 #define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
\r
638 #define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
639 #define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
640 #define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
\r
641 #define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
\r
642 #define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
\r
643 #define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
644 #define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
645 #define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
\r
646 #define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
\r
647 #define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
\r
648 #define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
649 #define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
650 #define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
\r
651 #define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
\r
652 #define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
\r
653 #define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
654 #define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
655 #define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
\r
656 #define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
\r
657 #define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
\r
658 #define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
659 #define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
660 #define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
\r
661 #define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
\r
662 #define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
\r
663 #define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
\r
664 #define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
\r
666 /* Bit fields for UART TXDOUBLE */
\r
667 #define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */
\r
668 #define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */
\r
669 #define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
\r
670 #define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
\r
671 #define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
\r
672 #define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
\r
673 #define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
\r
674 #define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
\r
675 #define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
\r
676 #define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
\r
678 /* Bit fields for UART IF */
\r
679 #define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */
\r
680 #define _UART_IF_MASK 0x00001FFFUL /**< Mask for UART_IF */
\r
681 #define UART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
\r
682 #define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
\r
683 #define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
\r
684 #define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
685 #define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IF */
\r
686 #define UART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
\r
687 #define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
\r
688 #define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
\r
689 #define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */
\r
690 #define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IF */
\r
691 #define UART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
\r
692 #define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
\r
693 #define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
\r
694 #define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
695 #define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IF */
\r
696 #define UART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
\r
697 #define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
\r
698 #define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
\r
699 #define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
700 #define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IF */
\r
701 #define UART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
\r
702 #define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
\r
703 #define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
\r
704 #define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
705 #define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IF */
\r
706 #define UART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
\r
707 #define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
\r
708 #define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
\r
709 #define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
710 #define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IF */
\r
711 #define UART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
\r
712 #define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
\r
713 #define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
\r
714 #define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
715 #define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IF */
\r
716 #define UART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
\r
717 #define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
\r
718 #define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
\r
719 #define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
720 #define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IF */
\r
721 #define UART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
\r
722 #define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
\r
723 #define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
\r
724 #define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
725 #define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IF */
\r
726 #define UART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
\r
727 #define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
\r
728 #define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
\r
729 #define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
730 #define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IF */
\r
731 #define UART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
\r
732 #define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
\r
733 #define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
\r
734 #define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
735 #define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IF */
\r
736 #define UART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
\r
737 #define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
\r
738 #define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
\r
739 #define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
740 #define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IF */
\r
741 #define UART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
\r
742 #define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
\r
743 #define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
\r
744 #define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
\r
745 #define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IF */
\r
747 /* Bit fields for UART IFS */
\r
748 #define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */
\r
749 #define _UART_IFS_MASK 0x00001FF9UL /**< Mask for UART_IFS */
\r
750 #define UART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
\r
751 #define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
\r
752 #define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
\r
753 #define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
754 #define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFS */
\r
755 #define UART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */
\r
756 #define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
\r
757 #define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
\r
758 #define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
759 #define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFS */
\r
760 #define UART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */
\r
761 #define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
\r
762 #define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
\r
763 #define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
764 #define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFS */
\r
765 #define UART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */
\r
766 #define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
\r
767 #define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
\r
768 #define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
769 #define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFS */
\r
770 #define UART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */
\r
771 #define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
\r
772 #define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
\r
773 #define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
774 #define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFS */
\r
775 #define UART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */
\r
776 #define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
\r
777 #define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
\r
778 #define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
779 #define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFS */
\r
780 #define UART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */
\r
781 #define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
\r
782 #define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
\r
783 #define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
784 #define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFS */
\r
785 #define UART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */
\r
786 #define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
\r
787 #define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
\r
788 #define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
789 #define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFS */
\r
790 #define UART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */
\r
791 #define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
\r
792 #define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
\r
793 #define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
794 #define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFS */
\r
795 #define UART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */
\r
796 #define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
\r
797 #define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
\r
798 #define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
799 #define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFS */
\r
800 #define UART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */
\r
801 #define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
\r
802 #define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
\r
803 #define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
\r
804 #define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFS */
\r
806 /* Bit fields for UART IFC */
\r
807 #define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */
\r
808 #define _UART_IFC_MASK 0x00001FF9UL /**< Mask for UART_IFC */
\r
809 #define UART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
\r
810 #define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
\r
811 #define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
\r
812 #define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
813 #define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFC */
\r
814 #define UART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */
\r
815 #define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
\r
816 #define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
\r
817 #define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
818 #define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFC */
\r
819 #define UART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */
\r
820 #define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
\r
821 #define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
\r
822 #define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
823 #define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFC */
\r
824 #define UART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */
\r
825 #define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
\r
826 #define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
\r
827 #define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
828 #define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFC */
\r
829 #define UART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */
\r
830 #define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
\r
831 #define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
\r
832 #define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
833 #define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFC */
\r
834 #define UART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */
\r
835 #define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
\r
836 #define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
\r
837 #define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
838 #define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFC */
\r
839 #define UART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */
\r
840 #define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
\r
841 #define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
\r
842 #define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
843 #define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFC */
\r
844 #define UART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */
\r
845 #define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
\r
846 #define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
\r
847 #define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
848 #define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFC */
\r
849 #define UART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */
\r
850 #define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
\r
851 #define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
\r
852 #define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
853 #define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFC */
\r
854 #define UART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */
\r
855 #define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
\r
856 #define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
\r
857 #define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
858 #define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFC */
\r
859 #define UART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */
\r
860 #define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
\r
861 #define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
\r
862 #define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
\r
863 #define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFC */
\r
865 /* Bit fields for UART IEN */
\r
866 #define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */
\r
867 #define _UART_IEN_MASK 0x00001FFFUL /**< Mask for UART_IEN */
\r
868 #define UART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
\r
869 #define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
\r
870 #define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
\r
871 #define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
872 #define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IEN */
\r
873 #define UART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
\r
874 #define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
\r
875 #define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
\r
876 #define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
877 #define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IEN */
\r
878 #define UART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
\r
879 #define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
\r
880 #define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
\r
881 #define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
882 #define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IEN */
\r
883 #define UART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */
\r
884 #define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
\r
885 #define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
\r
886 #define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
887 #define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IEN */
\r
888 #define UART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */
\r
889 #define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
\r
890 #define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
\r
891 #define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
892 #define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IEN */
\r
893 #define UART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */
\r
894 #define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
\r
895 #define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
\r
896 #define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
897 #define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IEN */
\r
898 #define UART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */
\r
899 #define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
\r
900 #define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
\r
901 #define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
902 #define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IEN */
\r
903 #define UART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */
\r
904 #define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
\r
905 #define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
\r
906 #define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
907 #define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IEN */
\r
908 #define UART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */
\r
909 #define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
\r
910 #define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
\r
911 #define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
912 #define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IEN */
\r
913 #define UART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */
\r
914 #define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
\r
915 #define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
\r
916 #define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
917 #define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IEN */
\r
918 #define UART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */
\r
919 #define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
\r
920 #define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
\r
921 #define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
922 #define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IEN */
\r
923 #define UART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */
\r
924 #define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
\r
925 #define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
\r
926 #define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
927 #define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IEN */
\r
928 #define UART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */
\r
929 #define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
\r
930 #define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
\r
931 #define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
\r
932 #define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IEN */
\r
934 /* Bit fields for UART IRCTRL */
\r
935 #define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */
\r
936 #define _UART_IRCTRL_MASK 0x000000FFUL /**< Mask for UART_IRCTRL */
\r
937 #define UART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
\r
938 #define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
\r
939 #define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
\r
940 #define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
\r
941 #define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */
\r
942 #define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
\r
943 #define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
\r
944 #define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
\r
945 #define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */
\r
946 #define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */
\r
947 #define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */
\r
948 #define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */
\r
949 #define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */
\r
950 #define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for UART_IRCTRL */
\r
951 #define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for UART_IRCTRL */
\r
952 #define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for UART_IRCTRL */
\r
953 #define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for UART_IRCTRL */
\r
954 #define UART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
\r
955 #define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
\r
956 #define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
\r
957 #define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
\r
958 #define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */
\r
959 #define _UART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */
\r
960 #define _UART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */
\r
961 #define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
\r
962 #define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */
\r
963 #define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */
\r
964 #define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */
\r
965 #define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */
\r
966 #define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */
\r
967 #define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */
\r
968 #define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */
\r
969 #define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */
\r
970 #define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IRCTRL */
\r
971 #define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for UART_IRCTRL */
\r
972 #define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for UART_IRCTRL */
\r
973 #define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for UART_IRCTRL */
\r
974 #define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for UART_IRCTRL */
\r
975 #define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for UART_IRCTRL */
\r
976 #define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for UART_IRCTRL */
\r
977 #define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for UART_IRCTRL */
\r
978 #define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for UART_IRCTRL */
\r
979 #define UART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
\r
980 #define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
\r
981 #define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
\r
982 #define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
\r
983 #define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */
\r
985 /* Bit fields for UART ROUTE */
\r
986 #define _UART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTE */
\r
987 #define _UART_ROUTE_MASK 0x0000070FUL /**< Mask for UART_ROUTE */
\r
988 #define UART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
\r
989 #define _UART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
\r
990 #define _UART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
\r
991 #define _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
\r
992 #define UART_ROUTE_RXPEN_DEFAULT (_UART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTE */
\r
993 #define UART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
\r
994 #define _UART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
\r
995 #define _UART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
\r
996 #define _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
\r
997 #define UART_ROUTE_TXPEN_DEFAULT (_UART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_ROUTE */
\r
998 #define UART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */
\r
999 #define _UART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
\r
1000 #define _UART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
\r
1001 #define _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
\r
1002 #define UART_ROUTE_CSPEN_DEFAULT (_UART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_ROUTE */
\r
1003 #define UART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
\r
1004 #define _UART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
\r
1005 #define _UART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
\r
1006 #define _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
\r
1007 #define UART_ROUTE_CLKPEN_DEFAULT (_UART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_ROUTE */
\r
1008 #define _UART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */
\r
1009 #define _UART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for USART_LOCATION */
\r
1010 #define _UART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTE */
\r
1011 #define _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
\r
1012 #define _UART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTE */
\r
1013 #define _UART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTE */
\r
1014 #define _UART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTE */
\r
1015 #define _UART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTE */
\r
1016 #define _UART_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTE */
\r
1017 #define UART_ROUTE_LOCATION_LOC0 (_UART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTE */
\r
1018 #define UART_ROUTE_LOCATION_DEFAULT (_UART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTE */
\r
1019 #define UART_ROUTE_LOCATION_LOC1 (_UART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTE */
\r
1020 #define UART_ROUTE_LOCATION_LOC2 (_UART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTE */
\r
1021 #define UART_ROUTE_LOCATION_LOC3 (_UART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTE */
\r
1022 #define UART_ROUTE_LOCATION_LOC4 (_UART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTE */
\r
1023 #define UART_ROUTE_LOCATION_LOC5 (_UART_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTE */
\r
1025 /* Bit fields for UART INPUT */
\r
1026 #define _UART_INPUT_RESETVALUE 0x00000000UL /**< Default value for UART_INPUT */
\r
1027 #define _UART_INPUT_MASK 0x0000001FUL /**< Mask for UART_INPUT */
\r
1028 #define _UART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
\r
1029 #define _UART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
\r
1030 #define _UART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
\r
1031 #define _UART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */
\r
1032 #define _UART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */
\r
1033 #define _UART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */
\r
1034 #define _UART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */
\r
1035 #define _UART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */
\r
1036 #define _UART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */
\r
1037 #define _UART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */
\r
1038 #define _UART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */
\r
1039 #define _UART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */
\r
1040 #define _UART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */
\r
1041 #define _UART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */
\r
1042 #define _UART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */
\r
1043 #define UART_INPUT_RXPRSSEL_DEFAULT (_UART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_INPUT */
\r
1044 #define UART_INPUT_RXPRSSEL_PRSCH0 (_UART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_INPUT */
\r
1045 #define UART_INPUT_RXPRSSEL_PRSCH1 (_UART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_INPUT */
\r
1046 #define UART_INPUT_RXPRSSEL_PRSCH2 (_UART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_INPUT */
\r
1047 #define UART_INPUT_RXPRSSEL_PRSCH3 (_UART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_INPUT */
\r
1048 #define UART_INPUT_RXPRSSEL_PRSCH4 (_UART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_INPUT */
\r
1049 #define UART_INPUT_RXPRSSEL_PRSCH5 (_UART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_INPUT */
\r
1050 #define UART_INPUT_RXPRSSEL_PRSCH6 (_UART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_INPUT */
\r
1051 #define UART_INPUT_RXPRSSEL_PRSCH7 (_UART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_INPUT */
\r
1052 #define UART_INPUT_RXPRSSEL_PRSCH8 (_UART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for UART_INPUT */
\r
1053 #define UART_INPUT_RXPRSSEL_PRSCH9 (_UART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for UART_INPUT */
\r
1054 #define UART_INPUT_RXPRSSEL_PRSCH10 (_UART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for UART_INPUT */
\r
1055 #define UART_INPUT_RXPRSSEL_PRSCH11 (_UART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for UART_INPUT */
\r
1056 #define UART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
\r
1057 #define _UART_INPUT_RXPRS_SHIFT 4 /**< Shift value for USART_RXPRS */
\r
1058 #define _UART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for USART_RXPRS */
\r
1059 #define _UART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
\r
1060 #define UART_INPUT_RXPRS_DEFAULT (_UART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_INPUT */
\r
1062 /* Bit fields for UART I2SCTRL */
\r
1063 #define _UART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_I2SCTRL */
\r
1064 #define _UART_I2SCTRL_MASK 0x0000071FUL /**< Mask for UART_I2SCTRL */
\r
1065 #define UART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
\r
1066 #define _UART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
\r
1067 #define _UART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
\r
1068 #define _UART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
\r
1069 #define UART_I2SCTRL_EN_DEFAULT (_UART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_I2SCTRL */
\r
1070 #define UART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
\r
1071 #define _UART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
\r
1072 #define _UART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
\r
1073 #define _UART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
\r
1074 #define UART_I2SCTRL_MONO_DEFAULT (_UART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_I2SCTRL */
\r
1075 #define UART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
\r
1076 #define _UART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
\r
1077 #define _UART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
\r
1078 #define _UART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
\r
1079 #define _UART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for UART_I2SCTRL */
\r
1080 #define _UART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for UART_I2SCTRL */
\r
1081 #define UART_I2SCTRL_JUSTIFY_DEFAULT (_UART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_I2SCTRL */
\r
1082 #define UART_I2SCTRL_JUSTIFY_LEFT (_UART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for UART_I2SCTRL */
\r
1083 #define UART_I2SCTRL_JUSTIFY_RIGHT (_UART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for UART_I2SCTRL */
\r
1084 #define UART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
\r
1085 #define _UART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
\r
1086 #define _UART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
\r
1087 #define _UART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
\r
1088 #define UART_I2SCTRL_DMASPLIT_DEFAULT (_UART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_I2SCTRL */
\r
1089 #define UART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
\r
1090 #define _UART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
\r
1091 #define _UART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
\r
1092 #define _UART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
\r
1093 #define UART_I2SCTRL_DELAY_DEFAULT (_UART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_I2SCTRL */
\r
1094 #define _UART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
\r
1095 #define _UART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
\r
1096 #define _UART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
\r
1097 #define _UART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for UART_I2SCTRL */
\r
1098 #define _UART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for UART_I2SCTRL */
\r
1099 #define _UART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for UART_I2SCTRL */
\r
1100 #define _UART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for UART_I2SCTRL */
\r
1101 #define _UART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for UART_I2SCTRL */
\r
1102 #define _UART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for UART_I2SCTRL */
\r
1103 #define _UART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for UART_I2SCTRL */
\r
1104 #define _UART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for UART_I2SCTRL */
\r
1105 #define UART_I2SCTRL_FORMAT_DEFAULT (_UART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_I2SCTRL */
\r
1106 #define UART_I2SCTRL_FORMAT_W32D32 (_UART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for UART_I2SCTRL */
\r
1107 #define UART_I2SCTRL_FORMAT_W32D24M (_UART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for UART_I2SCTRL */
\r
1108 #define UART_I2SCTRL_FORMAT_W32D24 (_UART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for UART_I2SCTRL */
\r
1109 #define UART_I2SCTRL_FORMAT_W32D16 (_UART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for UART_I2SCTRL */
\r
1110 #define UART_I2SCTRL_FORMAT_W32D8 (_UART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for UART_I2SCTRL */
\r
1111 #define UART_I2SCTRL_FORMAT_W16D16 (_UART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for UART_I2SCTRL */
\r
1112 #define UART_I2SCTRL_FORMAT_W16D8 (_UART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for UART_I2SCTRL */
\r
1113 #define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */
\r
1115 /** @} End of group EFM32GG_UART */
\r
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