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32 /*****************************************************************************/
36 * This file contains CPU specific initialization. Invoked from main CRT
39 * MODIFICATION HISTORY:
41 * Ver Who Date Changes
42 * ----- ------- -------- ---------------------------------------------------
43 * 5.00 pkp 02/10/14 Initial version
51 ******************************************************************************/
58 /* Clear cp15 regs with unknown reset values */
60 mcr p15, 0, r0, c5, c0, 0 /* DFSR */
61 mcr p15, 0, r0, c5, c0, 1 /* IFSR */
62 mcr p15, 0, r0, c6, c0, 0 /* DFAR */
63 mcr p15, 0, r0, c6, c0, 2 /* IFAR */
64 mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
65 mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
66 mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
69 /* Reset and start Cycle Counter */
70 mov r2, #0x80000000 /* clear overflow */
71 mcr p15, 0, r2, c9, c12, 3
72 mov r2, #0xd /* D, C, E */
73 mcr p15, 0, r2, c9, c12, 0
74 mov r2, #0x80000000 /* enable cycle counter */
75 mcr p15, 0, r2, c9, c12, 1