1 /**********************************************************************
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2 * $Id$ lpc18xx_gpdma.h 2011-06-02
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4 * @file lpc18xx_gpdma.h
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5 * @brief Contains all macro definitions and function prototypes
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6 * support for GPDMA firmware library on LPC18xx
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8 * @date 02. June. 2011
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9 * @author NXP MCU SW Application Team
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11 * Copyright(C) 2011, NXP Semiconductor
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12 * All rights reserved.
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14 ***********************************************************************
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15 * Software that is described herein is for illustrative purposes only
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16 * which provides customers with programming information regarding the
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17 * products. This software is supplied "AS IS" without any warranties.
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18 * NXP Semiconductors assumes no responsibility or liability for the
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19 * use of the software, conveys no license or title under any patent,
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20 * copyright, or mask work right to the product. NXP Semiconductors
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21 * reserves the right to make changes in the software without
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22 * notification. NXP Semiconductors also make no representation or
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23 * warranty that such application will be suitable for the specified
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24 * use without further testing or modification.
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25 **********************************************************************/
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27 /* Peripheral group ----------------------------------------------------------- */
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28 /** @defgroup GPDMA GPDMA (General Purpose DMA)
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29 * @ingroup LPC1800CMSIS_FwLib_Drivers
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33 #ifndef LPC18XX_GPDMA_H_
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34 #define LPC18XX_GPDMA_H_
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36 /* Includes ------------------------------------------------------------------- */
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37 #include "LPC18xx.h"
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38 #include "lpc_types.h"
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46 /* Public Macros -------------------------------------------------------------- */
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47 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
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51 /** DMA Connection number definitions */
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52 #define GPDMA_CONN_SPIFI ((0UL)) /**< SPIFI */
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53 #define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */
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54 #define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */
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55 #define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */
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56 #define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */
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57 #define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */
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58 #define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */
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59 #define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */
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60 #define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */
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61 #define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */
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62 #define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */
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63 #define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */
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64 #define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */
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65 #define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */
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66 #define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
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67 #define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/
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68 #define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */
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69 #define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */
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70 #define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/
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71 #define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */
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72 #define GPDMA_CONN_I2S_Channel_0 ((20UL)) /**< I2S channel 0 */
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73 #define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */
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74 #define GPDMA_CONN_I2S_Channel_1 ((22UL)) /**< I2S channel 1 */
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75 #define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */
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76 #define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */
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77 #define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */
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78 #define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */
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79 #define GPDMA_CONN_DAC ((27UL)) /**< DAC */
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81 /** GPDMA Transfer type definitions */
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82 #define GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA ((0UL)) /**< Memory to memory - DMA control */
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83 #define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA ((1UL)) /**< Memory to peripheral - DMA control */
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84 #define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA ((2UL)) /**< Peripheral to memory - DMA control */
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85 #define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
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86 #define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL ((4UL)) /**< Source peripheral to destination peripheral - destination peripheral control */
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87 #define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL ((5UL)) /**< Memory to peripheral - peripheral control */
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88 #define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL ((6UL)) /**< Peripheral to memory - peripheral control */
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89 #define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL ((7UL)) /**< Source peripheral to destination peripheral - source peripheral control */
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91 /** Burst size in Source and Destination definitions */
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92 #define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
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93 #define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
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94 #define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
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95 #define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
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96 #define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
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97 #define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
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98 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
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99 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
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101 /** Width in Source transfer width and Destination transfer width definitions */
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102 #define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
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103 #define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
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104 #define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
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106 /** LPC_GPDMA base addresses */
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107 #define LPC_GPDMACH0_BASE 0x40002100
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108 #define LPC_GPDMACH1_BASE 0x40002120
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109 #define LPC_GPDMACH2_BASE 0x40002140
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110 #define LPC_GPDMACH3_BASE 0x40002160
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111 #define LPC_GPDMACH4_BASE 0x40002180
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112 #define LPC_GPDMACH5_BASE 0x400021A0
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113 #define LPC_GPDMACH6_BASE 0x400021C0
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114 #define LPC_GPDMACH7_BASE 0x400021E0
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116 /* LPC_GPDMA channels definitions */
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117 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
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118 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
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119 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
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120 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
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121 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
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122 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
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123 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
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124 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
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130 /* Private Macros ------------------------------------------------------------- */
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131 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
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135 /* --------------------- BIT DEFINITIONS -------------------------------------- */
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136 /*********************************************************************//**
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137 * Macro defines for DMA Interrupt Status register
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138 **********************************************************************/
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139 #define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
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140 #define GPDMA_DMACIntStat_BITMASK ((0xFF))
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142 /*********************************************************************//**
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143 * Macro defines for DMA Interrupt Terminal Count Request Status register
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144 **********************************************************************/
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145 #define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
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146 #define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
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148 /*********************************************************************//**
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149 * Macro defines for DMA Interrupt Terminal Count Request Clear register
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150 **********************************************************************/
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151 #define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
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152 #define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
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154 /*********************************************************************//**
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155 * Macro defines for DMA Interrupt Error Status register
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156 **********************************************************************/
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157 #define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
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158 #define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
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160 /*********************************************************************//**
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161 * Macro defines for DMA Interrupt Error Clear register
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162 **********************************************************************/
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163 #define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
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164 #define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
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166 /*********************************************************************//**
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167 * Macro defines for DMA Raw Interrupt Terminal Count Status register
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168 **********************************************************************/
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169 #define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
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170 #define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
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172 /*********************************************************************//**
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173 * Macro defines for DMA Raw Error Interrupt Status register
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174 **********************************************************************/
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175 #define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
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176 #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
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178 /*********************************************************************//**
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179 * Macro defines for DMA Enabled Channel register
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180 **********************************************************************/
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181 #define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
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182 #define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
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184 /*********************************************************************//**
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185 * Macro defines for DMA Software Burst Request register
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186 **********************************************************************/
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187 #define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
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188 #define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
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190 /*********************************************************************//**
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191 * Macro defines for DMA Software Single Request register
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192 **********************************************************************/
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193 #define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
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194 #define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
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196 /*********************************************************************//**
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197 * Macro defines for DMA Software Last Burst Request register
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198 **********************************************************************/
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199 #define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
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200 #define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
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202 /*********************************************************************//**
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203 * Macro defines for DMA Software Last Single Request register
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204 **********************************************************************/
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205 #define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
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206 #define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
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208 /*********************************************************************//**
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209 * Macro defines for DMA Configuration register
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210 **********************************************************************/
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211 #define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
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212 #define GPDMA_DMACConfig_M0 ((0x02)) /**< AHB Master 0 endianness configuration*/
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213 #define GPDMA_DMACConfig_M1 ((0x04)) /**< AHB Master 1 endianness configuration*/
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214 #define GPDMA_DMACConfig_BITMASK ((0x07))
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216 /*********************************************************************//**
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217 * Macro defines for DMA Synchronization register
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218 **********************************************************************/
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219 #define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
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220 #define GPDMA_DMACSync_BITMASK ((0xFFFF))
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222 /*********************************************************************//**
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223 * Macro defines for DMA Channel Linked List Item registers
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224 **********************************************************************/
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225 /** DMA Channel Linked List Item registers bit mask*/
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226 #define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
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228 /*********************************************************************//**
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229 * Macro defines for DMA channel control registers
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230 **********************************************************************/
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231 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
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232 #define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
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233 #define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
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234 #define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
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235 #define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
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236 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL<<24)) /**< Source AHB master select*/
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237 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL<<25)) /**< Destination AHB master select*/
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238 #define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
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239 #define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
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240 #define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
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241 #define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
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242 #define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
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243 #define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
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244 /** DMA channel control registers bit mask */
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245 #define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
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247 /*********************************************************************//**
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248 * Macro defines for DMA Channel Configuration registers
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249 **********************************************************************/
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250 #define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
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251 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
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252 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
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253 #define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
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254 #define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
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255 #define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
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256 #define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
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257 #define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
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258 #define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
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259 /** DMA Channel Configuration registers bit mask */
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260 #define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
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262 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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263 /* Macros check GPDMA channel */
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264 #define PARAM_GPDMA_CHANNEL(n) (n<=7)
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266 /* Macros check GPDMA connection type */
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267 #define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SPIFI) || (n==GPDMA_CONN_DAC) \
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268 || (n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
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269 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
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270 || (n==GPDMA_CONN_ADC_0) || (n==GPDMA_CONN_ADC_1) \
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271 || (n==GPDMA_CONN_I2S_Channel_0) || (n==GPDMA_CONN_I2S_Channel_1) \
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272 || (n==GPDMA_CONN_SCT_0) || (n==GPDMA_CONN_SCT_1) \
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273 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
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274 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
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275 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
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276 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
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277 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
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278 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
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279 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
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280 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
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282 /* Macros check GPDMA burst size type */
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283 #define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
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284 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
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285 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
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286 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
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288 /* Macros check GPDMA width type */
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289 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
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290 || (n==GPDMA_WIDTH_WORD))
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292 /* Macros check GPDMA status type */
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293 #define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
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294 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
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295 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
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297 /* Macros check GPDMA transfer type */
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298 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA) \
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299 ||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA)\
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300 ||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL)\
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301 ||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL))
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303 /* Macros check GPDMA state clear type */
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304 #define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
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311 /* Public Types --------------------------------------------------------------- */
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312 /** @defgroup GPDMA_Public_Types GPDMA Public Types
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317 * @brief GPDMA Channel Registers
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321 __IO uint32_t CSrcAddr;
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322 __IO uint32_t CDestAddr;
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323 __IO uint32_t CLLI;
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324 __IO uint32_t CControl;
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325 __IO uint32_t CConfig;
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326 } LPC_GPDMACH_TypeDef;
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329 * @brief GPDMA Status enumeration
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332 GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
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333 GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
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334 GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
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335 GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
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336 GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
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337 GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
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338 } GPDMA_Status_Type;
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341 * @brief GPDMA Interrupt clear status enumeration
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344 GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
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345 GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
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346 }GPDMA_StateClear_Type;
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349 * @brief GPDMA Channel configuration structure type definition
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352 uint32_t ChannelNum; /**< DMA channel number, should be in
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354 Note: DMA channel 0 has the highest priority
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355 and DMA channel 7 the lowest priority.
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357 uint32_t TransferSize; /**< Length/Size of transfer */
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358 uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
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359 uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
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360 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
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361 uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
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362 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
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363 uint32_t TransferType; /**< Transfer Type, should be one of the following:
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364 - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: Memory to memory - DMA control
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365 - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: Memory to peripheral - DMA control
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366 - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: Peripheral to memory - DMA control
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367 - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: Source peripheral to destination peripheral - DMA control
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368 - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: Source peripheral to destination peripheral - destination peripheral control
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369 - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: Memory to peripheral - peripheral control
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370 - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: Peripheral to memory - peripheral control
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371 - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: Source peripheral to destination peripheral - source peripheral control
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373 uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
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374 GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
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376 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
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377 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
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378 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
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379 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
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380 - GPDMA_CONN_ADC_0: ADC0
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381 - GPDMA_CONN_ADC_1: ADC1
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382 - GPDMA_CONN_SCT_0: SCT0
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383 - GPDMA_CONN_SCT_1: SCT1
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384 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
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385 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
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386 - GPDMA_CONN_DAC: DAC
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387 - GPDMA_CONN_SPIFI: SPIFI
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388 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
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389 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
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390 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
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391 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
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392 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
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393 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
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394 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
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395 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
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397 uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
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398 GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
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400 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
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401 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
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402 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
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403 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
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404 - GPDMA_CONN_ADC_0: ADC0
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405 - GPDMA_CONN_ADC_1: ADC1
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406 - GPDMA_CONN_SCT_0: SCT0
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407 - GPDMA_CONN_SCT_1: SCT1
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408 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
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409 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
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410 - GPDMA_CONN_DAC: DAC
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411 - GPDMA_CONN_SPIFI: SPIFI
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412 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
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413 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
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414 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
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415 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
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416 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
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417 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
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418 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
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419 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
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421 uint32_t DMALLI; /**< Linker List Item structure data address
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422 if there's no Linker List, set as '0'
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424 } GPDMA_Channel_CFG_Type;
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427 * @brief GPDMA Linker List Item structure type definition
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430 uint32_t SrcAddr; /**< Source Address */
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431 uint32_t DstAddr; /**< Destination address */
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432 uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
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433 uint32_t Control; /**< GPDMA Control of this LLI */
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441 /* Public Functions ----------------------------------------------------------- */
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442 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions
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446 void GPDMA_Init(void);
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448 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
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449 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
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450 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
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451 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
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462 #endif /* LPC18XX_GPDMA_H_ */
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468 /* --------------------------------- End Of File ------------------------------ */
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