2 * @brief LPC43xx basic chip inclusion file
\r
4 * Copyright(C) NXP Semiconductors, 2012
\r
5 * All rights reserved.
\r
7 * Software that is described herein is for illustrative purposes only
\r
8 * which provides customers with programming information regarding the
\r
9 * LPC products. This software is supplied "AS IS" without any warranties of
\r
10 * any kind, and NXP Semiconductors and its licensor disclaim any and
\r
11 * all warranties, express or implied, including all implied warranties of
\r
12 * merchantability, fitness for a particular purpose and non-infringement of
\r
13 * intellectual property rights. NXP Semiconductors assumes no responsibility
\r
14 * or liability for the use of the software, conveys no license or rights under any
\r
15 * patent, copyright, mask work right, or any other intellectual property rights in
\r
16 * or to any products. NXP Semiconductors reserves the right to make changes
\r
17 * in the software without notification. NXP Semiconductors also makes no
\r
18 * representation or warranty that such application will be suitable for the
\r
19 * specified use without further testing or modification.
\r
21 * Permission to use, copy, modify, and distribute this software and its
\r
22 * documentation is hereby granted, under NXP Semiconductors' and its
\r
23 * licensor's relevant copyrights in the software, without fee, provided that it
\r
24 * is used in conjunction with NXP Semiconductors microcontrollers. This
\r
25 * copyright, permission, and disclaimer notice must appear in all copies of
\r
29 #ifndef __CHIP_LPC43XX_H_
\r
30 #define __CHIP_LPC43XX_H_
\r
32 #include "lpc_types.h"
\r
33 #include "sys_config.h"
\r
39 #if !defined(CORE_M4) && !defined(CORE_M0)
\r
40 #error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture
\r
41 #error CORE_M4 or CORE_M0 should be defined as part of your compiler define list
\r
44 #ifndef CHIP_LPC43XX
\r
45 #error The LPC43XX Chip include path is used for this build, but
\r
46 #error CHIP_LPC43XX is not defined!
\r
49 /** @defgroup IP_LPC43XX_FILES CHIP: LPC43XX Chip layer required IP layer drivers
\r
50 * @ingroup CHIP_18XX_43XX_Drivers
\r
51 * This is a list of the IP drivers required for the LPC43XX device family.<br>
\r
52 * (adc_001.c, adc_001.h) @ref IP_ADC_001<br>
\r
53 * (atimer_001.c, atimer_001.h) @ref IP_ATIMER_001<br>
\r
54 * (ccan_001.c, ccan_001.h) @ref IP_CCAN_001<br>
\r
55 * (dac_001.c, dac_001.h) @ref IP_DAC_001<br>
\r
56 * (emc_001.c, emc_001.h) @ref IP_EMC_001<br>
\r
57 * (enet_001.c, enet_001.h) @ref IP_ENET_001<br>
\r
58 * (gima_001.h) @ref IP_GIMA_001<br>
\r
59 * (gpdma_001.c, gpdma_001.h) @ref IP_GPDMA_001<br>
\r
60 * (gpiogrpint_001.c, gpiogrpint_001.h) @ref IP_GPIOGRPINT_001<br>
\r
61 * (gpiopinint_001.c, gpiopinint_001.h) @ref IP_GPIOPININT_001<br>
\r
62 * (gpio_001.h) @ref IP_GPIO_001<br>
\r
63 * (i2c_001.c, i2c_001.h) @ref IP_I2C_001<br>
\r
64 * (i2s_001.c, i2s_001.h) @ref IP_I2S_001<br>
\r
65 * (lcd_001.c, lcd_001.h) @ref IP_LCD_001<br>
\r
66 * (mcpwm_001.h) @ref IP_MCPWM_001<br>
\r
67 * (pmc_001.h) @ref IP_PMC_001<br>
\r
68 * (qei_001.h) @ref IP_QEI_001<br>
\r
69 * (regfile_001.h) @ref IP_REGFILE_001<br>
\r
70 * (ritimer_001.c, ritimer_001.h) @ref IP_RITIMER_001<br>
\r
71 * (rtc_001.c, rtc_001.h) @ref IP_RTC_001<br>
\r
72 * (sct_001.c, sct_001.h) @ref IP_SCT_001<br>
\r
73 * (sdmmc_001.c, sdmmc_001.h) @ref IP_SDMMC_001<br>
\r
74 * (sgpio_001.h) @ref IP_SGPIO_001<br>
\r
75 * (spi_001.h) @ref IP_SPI_001<br>
\r
76 * (ssp_001.c, ssp_001.h) @ref IP_SSP_001<br>
\r
77 * (timer_001.c, timer_001.h) @ref IP_TIMER_001<br>
\r
78 * (usart_001.c, usart_001.h) @ref IP_USART_001<br>
\r
79 * (usbhs_001.h) @ref IP_USBHS_001<br>
\r
80 * (wwdt_001.c, wwdt_001.h) @ref IP_WWDT_001<br>
\r
81 * (eeprom_002.c, eeprom_002.h) @ref IP_EEPROM_002<br>
\r
90 #include "adc_001.h"
\r
91 #include "atimer_001.h"
\r
92 #include "ccan_001.h"
\r
93 #include "dac_001.h"
\r
94 #include "emc_001.h"
\r
95 #include "enet_001.h"
\r
96 #include "gima_001.h"
\r
97 #include "gpdma_001.h"
\r
98 #include "gpiogrpint_001.h"
\r
99 #include "gpiopinint_001.h"
\r
100 #include "gpio_001.h"
\r
101 #include "i2c_001.h"
\r
102 #include "i2s_001.h"
\r
103 #include "lcd_001.h"
\r
104 #include "mcpwm_001.h"
\r
105 #include "pmc_001.h"
\r
106 #include "qei_001.h"
\r
107 #include "regfile_001.h"
\r
108 #include "ritimer_001.h"
\r
109 #include "rtc_001.h"
\r
110 #include "sct_001.h"
\r
111 #include "sdmmc_001.h"
\r
112 #include "sgpio_001.h"
\r
113 #include "spi_001.h"
\r
114 #include "ssp_001.h"
\r
115 #include "timer_001.h"
\r
116 #include "usart_001.h"
\r
117 #include "usbhs_001.h"
\r
118 #include "wwdt_001.h"
\r
119 #include "rgu_18xx_43xx.h"
\r
120 #include "cguccu_18xx_43xx.h"
\r
121 #include "eeprom_002.h"
\r
123 /** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations
\r
124 * @ingroup CHIP_18XX_43XX_Drivers
\r
128 #define LPC_SCT_BASE 0x40000000
\r
129 #define LPC_GPDMA_BASE 0x40002000
\r
130 #define LPC_SDMMC_BASE 0x40004000
\r
131 #define LPC_EMC_BASE 0x40005000
\r
132 #define LPC_USB0_BASE 0x40006000
\r
133 #define LPC_USB1_BASE 0x40007000
\r
134 #define LPC_LCD_BASE 0x40008000
\r
135 #define LPC_ETHERNET_BASE 0x40010000
\r
136 #define LPC_ATIMER_BASE 0x40040000
\r
137 #define LPC_REGFILE_BASE 0x40041000
\r
138 #define LPC_PMC_BASE 0x40042000
\r
139 #define LPC_CREG_BASE 0x40043000
\r
140 #define LPC_EVRT_BASE 0x40044000
\r
141 #define LPC_RTC_BASE 0x40046000
\r
142 #define LPC_CGU_BASE 0x40050000
\r
143 #define LPC_CCU1_BASE 0x40051000
\r
144 #define LPC_CCU2_BASE 0x40052000
\r
145 #define LPC_RGU_BASE 0x40053000
\r
146 #define LPC_WWDT_BASE 0x40080000
\r
147 #define LPC_USART0_BASE 0x40081000
\r
148 #define LPC_USART2_BASE 0x400C1000
\r
149 #define LPC_USART3_BASE 0x400C2000
\r
150 #define LPC_UART1_BASE 0x40082000
\r
151 #define LPC_SSP0_BASE 0x40083000
\r
152 #define LPC_SSP1_BASE 0x400C5000
\r
153 #define LPC_TIMER0_BASE 0x40084000
\r
154 #define LPC_TIMER1_BASE 0x40085000
\r
155 #define LPC_TIMER2_BASE 0x400C3000
\r
156 #define LPC_TIMER3_BASE 0x400C4000
\r
157 #define LPC_SCU_BASE 0x40086000
\r
158 #define LPC_GPIO_PIN_INT_BASE 0x40087000
\r
159 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
\r
160 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
\r
161 #define LPC_MCPWM_BASE 0x400A0000
\r
162 #define LPC_I2C0_BASE 0x400A1000
\r
163 #define LPC_I2C1_BASE 0x400E0000
\r
164 #define LPC_I2S0_BASE 0x400A2000
\r
165 #define LPC_I2S1_BASE 0x400A3000
\r
166 #define LPC_C_CAN1_BASE 0x400A4000
\r
167 #define LPC_RITIMER_BASE 0x400C0000
\r
168 #define LPC_QEI_BASE 0x400C6000
\r
169 #define LPC_GIMA_BASE 0x400C7000
\r
170 #define LPC_DAC_BASE 0x400E1000
\r
171 #define LPC_C_CAN0_BASE 0x400E2000
\r
172 #define LPC_ADC0_BASE 0x400E3000
\r
173 #define LPC_ADC1_BASE 0x400E4000
\r
174 #define LPC_GPIO_PORT_BASE 0x400F4000
\r
175 #define LPC_SPI_BASE 0x40100000
\r
176 #define LPC_SGPIO_BASE 0x40101000
\r
177 #define LPC_EEPROM_BASE 0x4000E000
\r
179 /* Normalize types */
\r
180 typedef IP_SCT_001_T LPC_SCT_T;
\r
181 typedef IP_GPDMA_001_T LPC_GPDMA_T;
\r
182 typedef IP_SDMMC_001_T LPC_SDMMC_T;
\r
183 typedef IP_EMC_001_T LPC_EMC_T;
\r
184 typedef IP_USBHS_001_T LPC_USBHS_T;
\r
185 typedef IP_ENET_001_T LPC_ENET_T;
\r
186 typedef IP_ATIMER_001_T LPC_ATIMER_T;
\r
187 typedef IP_REGFILE_001_T LPC_REGFILE_T;
\r
188 typedef IP_PMC_001_T LPC_PMC_T;
\r
189 typedef IP_RTC_001_T LPC_RTC_T;
\r
190 typedef IP_WWDT_001_T LPC_WWDT_T;
\r
191 typedef IP_USART_001_T LPC_USART_T;
\r
192 typedef IP_SSP_001_T LPC_SSP_T;
\r
193 typedef IP_TIMER_001_T LPC_TIMER_T;
\r
194 typedef IP_GPIOPININT_001_T LPC_GPIOPININT_T;
\r
195 typedef IP_MCPWM_001_T LPC_MCPWM_T;
\r
196 typedef IP_I2C_001_T LPC_I2C_T;
\r
197 typedef IP_I2S_001_T LPC_I2S_T;
\r
198 typedef IP_CCAN_001_T LPC_CCAN_T;
\r
199 typedef IP_RITIMER_001_T LPC_RITIMER_T;
\r
200 typedef IP_QEI_001_T LPC_QEI_T;
\r
201 typedef IP_GIMA_001_T LPC_GIMA_T;
\r
202 typedef IP_DAC_001_T LPC_DAC_T;
\r
203 typedef IP_ADC_001_T LPC_ADC_T;
\r
204 typedef IP_GPIO_001_T LPC_GPIO_T;
\r
205 typedef IP_SPI_001_T LPC_SPI_T;
\r
206 typedef IP_SGPIO_001_T LPC_SGPIO_T;
\r
207 typedef IP_LCD_001_T LPC_LCD_T;
\r
208 typedef IP_EEPROM_002_T LPC_EEPROM_T;
\r
210 #define LPC_SCT ((IP_SCT_001_T *) LPC_SCT_BASE)
\r
211 #define LPC_GPDMA ((IP_GPDMA_001_T *) LPC_GPDMA_BASE)
\r
212 #define LPC_SDMMC ((IP_SDMMC_001_T *) LPC_SDMMC_BASE)
\r
213 #define LPC_EMC ((IP_EMC_001_T *) LPC_EMC_BASE)
\r
214 #define LPC_USB0 ((IP_USBHS_001_T *) LPC_USB0_BASE)
\r
215 #define LPC_USB1 ((IP_USBHS_001_T *) LPC_USB1_BASE)
\r
216 #define LPC_LCD ((IP_LCD_001_T *) LPC_LCD_BASE)
\r
217 #define LPC_ETHERNET ((IP_ENET_001_T *) LPC_ETHERNET_BASE)
\r
218 #define LPC_ATIMER ((IP_ATIMER_001_T *) LPC_ATIMER_BASE)
\r
219 #define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)
\r
220 #define LPC_PMC ((IP_PMC_001_T *) LPC_PMC_BASE)
\r
221 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
\r
222 #define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)
\r
223 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
\r
224 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
\r
225 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
\r
226 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
\r
227 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
\r
228 #define LPC_WWDT ((IP_WWDT_001_T *) LPC_WWDT_BASE)
\r
229 #define LPC_USART0 ((IP_USART_001_T *) LPC_USART0_BASE)
\r
230 #define LPC_USART2 ((IP_USART_001_T *) LPC_USART2_BASE)
\r
231 #define LPC_USART3 ((IP_USART_001_T *) LPC_USART3_BASE)
\r
232 #define LPC_UART1 ((IP_USART_001_T *) LPC_UART1_BASE)
\r
233 #define LPC_SSP0 ((IP_SSP_001_T *) LPC_SSP0_BASE)
\r
234 #define LPC_SSP1 ((IP_SSP_001_T *) LPC_SSP1_BASE)
\r
235 #define LPC_TIMER0 ((IP_TIMER_001_T *) LPC_TIMER0_BASE)
\r
236 #define LPC_TIMER1 ((IP_TIMER_001_T *) LPC_TIMER1_BASE)
\r
237 #define LPC_TIMER2 ((IP_TIMER_001_T *) LPC_TIMER2_BASE)
\r
238 #define LPC_TIMER3 ((IP_TIMER_001_T *) LPC_TIMER3_BASE)
\r
239 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
\r
240 #define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_T *) LPC_GPIO_PIN_INT_BASE)
\r
241 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT0_BASE)
\r
242 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT1_BASE)
\r
243 #define LPC_MCPWM ((IP_MCPWM_001_T *) LPC_MCPWM_BASE)
\r
244 #define LPC_I2C0 ((IP_I2C_001_T *) LPC_I2C0_BASE)
\r
245 #define LPC_I2C1 ((IP_I2C_001_T *) LPC_I2C1_BASE)
\r
246 #define LPC_I2S0 ((IP_I2S_001_T *) LPC_I2S0_BASE)
\r
247 #define LPC_I2S1 ((IP_I2S_001_T *) LPC_I2S1_BASE)
\r
248 #define LPC_C_CAN1 ((IP_CCAN_001_T *) LPC_C_CAN1_BASE)
\r
249 #define LPC_RITIMER ((IP_RITIMER_001_T *) LPC_RITIMER_BASE)
\r
250 #define LPC_QEI ((IP_QEI_001_T *) LPC_QEI_BASE)
\r
251 #define LPC_GIMA ((IP_GIMA_001_T *) LPC_GIMA_BASE)
\r
252 #define LPC_DAC ((IP_DAC_001_T *) LPC_DAC_BASE)
\r
253 #define LPC_C_CAN0 ((IP_CCAN_001_T *) LPC_C_CAN0_BASE)
\r
254 #define LPC_ADC0 ((IP_ADC_001_T *) LPC_ADC0_BASE)
\r
255 #define LPC_ADC1 ((IP_ADC_001_T *) LPC_ADC1_BASE)
\r
256 #define LPC_GPIO_PORT ((IP_GPIO_001_T *) LPC_GPIO_PORT_BASE)
\r
257 #define LPC_SPI ((IP_SPI_001_T *) LPC_SPI_BASE)
\r
258 #define LPC_SGPIO ((IP_SGPIO_001_T *) LPC_SGPIO_BASE)
\r
259 #define LPC_EEPROM ((IP_EEPROM_002_T *) LPC_EEPROM_BASE)
\r
264 #include "clock_18xx_43xx.h"
\r
265 #include "gpio_18xx_43xx.h"
\r
266 #include "scu_18xx_43xx.h"
\r
267 #include "sct_18xx_43xx.h"
\r
268 #include "uart_18xx_43xx.h"
\r
269 #include "gpdma_18xx_43xx.h"
\r
270 #include "enet_18xx_43xx.h"
\r
271 #include "rgu_18xx_43xx.h"
\r
272 #include "i2c_18xx_43xx.h"
\r
273 #include "i2s_18xx_43xx.h"
\r
274 #include "ssp_18xx_43xx.h"
\r
275 #include "rtc_18xx_43xx.h"
\r
276 #include "evrt_18xx_43xx.h"
\r
277 #include "atimer_18xx_43xx.h"
\r
278 #include "wwdt_18xx_43xx.h"
\r
279 #include "ritimer_18xx_43xx.h"
\r
280 #include "emc_18xx_43xx.h"
\r
281 #include "lcd_18xx_43xx.h"
\r
282 #include "adc_18xx_43xx.h"
\r
283 #include "dac_18xx_43xx.h"
\r
284 #include "timer_18xx_43xx.h"
\r
285 #include "sdif_18xx_43xx.h"
\r
286 #include "sdmmc_18xx_43xx.h"
\r
287 #include "fpu_init.h"
\r
288 #include "creg_18xx_43xx.h"
\r
289 #include "ccan_18xx_43xx.h"
\r
290 #include "pmc_18xx_43xx.h"
\r
291 #include "otp_18xx_43xx.h"
\r
292 #include "aes_18xx_43xx.h"
\r
293 #include "eeprom_18xx_43xx.h"
\r
299 #endif /* __CHIP_LPC43XX_H_ */
\r