2 ******************************************************************************
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3 * @file stm32l4xx_hal_tim.h
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4 * @author MCD Application Team
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5 * @brief Header file of TIM HAL module.
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6 ******************************************************************************
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9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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10 * All rights reserved.</center></h2>
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12 * This software component is licensed by ST under BSD 3-Clause license,
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13 * the "License"; You may not use this file except in compliance with the
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14 * License. You may obtain a copy of the License at:
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15 * opensource.org/licenses/BSD-3-Clause
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17 ******************************************************************************
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20 /* Define to prevent recursive inclusion -------------------------------------*/
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21 #ifndef STM32L4xx_HAL_TIM_H
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22 #define STM32L4xx_HAL_TIM_H
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28 /* Includes ------------------------------------------------------------------*/
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29 #include "stm32l4xx_hal_def.h"
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31 /** @addtogroup STM32L4xx_HAL_Driver
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39 /* Exported types ------------------------------------------------------------*/
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40 /** @defgroup TIM_Exported_Types TIM Exported Types
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45 * @brief TIM Time base Configuration Structure definition
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49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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52 uint32_t CounterMode; /*!< Specifies the counter mode.
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53 This parameter can be a value of @ref TIM_Counter_Mode */
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55 uint32_t Period; /*!< Specifies the period value to be loaded into the active
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56 Auto-Reload Register at the next update event.
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57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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59 uint32_t ClockDivision; /*!< Specifies the clock division.
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60 This parameter can be a value of @ref TIM_ClockDivision */
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62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
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63 reaches zero, an update event is generated and counting restarts
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64 from the RCR value (N).
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65 This means in PWM mode that (N+1) corresponds to:
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66 - the number of PWM periods in edge-aligned mode
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67 - the number of half PWM period in center-aligned mode
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68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
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69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
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72 This parameter can be a value of @ref TIM_AutoReloadPreload */
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73 } TIM_Base_InitTypeDef;
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76 * @brief TIM Output Compare Configuration Structure definition
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80 uint32_t OCMode; /*!< Specifies the TIM mode.
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81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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86 uint32_t OCPolarity; /*!< Specifies the output polarity.
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87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
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90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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91 @note This parameter is valid only for timer instances supporting break feature. */
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93 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
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94 This parameter can be a value of @ref TIM_Output_Fast_State
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95 @note This parameter is valid only in PWM1 and PWM2 mode. */
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98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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100 @note This parameter is valid only for timer instances supporting break feature. */
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102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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104 @note This parameter is valid only for timer instances supporting break feature. */
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105 } TIM_OC_InitTypeDef;
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108 * @brief TIM One Pulse Mode Configuration Structure definition
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112 uint32_t OCMode; /*!< Specifies the TIM mode.
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113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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118 uint32_t OCPolarity; /*!< Specifies the output polarity.
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119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
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122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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123 @note This parameter is valid only for timer instances supporting break feature. */
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125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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127 @note This parameter is valid only for timer instances supporting break feature. */
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129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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131 @note This parameter is valid only for timer instances supporting break feature. */
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133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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136 uint32_t ICSelection; /*!< Specifies the input.
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137 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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139 uint32_t ICFilter; /*!< Specifies the input capture filter.
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140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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141 } TIM_OnePulse_InitTypeDef;
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144 * @brief TIM Input Capture Configuration Structure definition
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148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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151 uint32_t ICSelection; /*!< Specifies the input.
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152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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157 uint32_t ICFilter; /*!< Specifies the input capture filter.
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158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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159 } TIM_IC_InitTypeDef;
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162 * @brief TIM Encoder Configuration Structure definition
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166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
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167 This parameter can be a value of @ref TIM_Encoder_Mode */
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169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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170 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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172 uint32_t IC1Selection; /*!< Specifies the input.
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173 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
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176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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178 uint32_t IC1Filter; /*!< Specifies the input capture filter.
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179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
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182 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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184 uint32_t IC2Selection; /*!< Specifies the input.
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185 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
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188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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190 uint32_t IC2Filter; /*!< Specifies the input capture filter.
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191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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192 } TIM_Encoder_InitTypeDef;
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195 * @brief Clock Configuration Handle Structure definition
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199 uint32_t ClockSource; /*!< TIM clock sources
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200 This parameter can be a value of @ref TIM_Clock_Source */
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201 uint32_t ClockPolarity; /*!< TIM clock polarity
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202 This parameter can be a value of @ref TIM_Clock_Polarity */
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203 uint32_t ClockPrescaler; /*!< TIM clock prescaler
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204 This parameter can be a value of @ref TIM_Clock_Prescaler */
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205 uint32_t ClockFilter; /*!< TIM clock filter
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206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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207 } TIM_ClockConfigTypeDef;
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210 * @brief TIM Clear Input Configuration Handle Structure definition
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214 uint32_t ClearInputState; /*!< TIM clear Input state
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215 This parameter can be ENABLE or DISABLE */
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216 uint32_t ClearInputSource; /*!< TIM clear Input sources
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217 This parameter can be a value of @ref TIM_ClearInput_Source */
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218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
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219 This parameter can be a value of @ref TIM_ClearInput_Polarity */
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220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
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221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
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222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
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223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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224 } TIM_ClearInputConfigTypeDef;
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227 * @brief TIM Master configuration Structure definition
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228 * @note Advanced timers provide TRGO2 internal line which is redirected
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233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
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234 This parameter can be a value of @ref TIM_Master_Mode_Selection */
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235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
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236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
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237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
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238 This parameter can be a value of @ref TIM_Master_Slave_Mode */
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239 } TIM_MasterConfigTypeDef;
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242 * @brief TIM Slave configuration Structure definition
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246 uint32_t SlaveMode; /*!< Slave mode selection
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247 This parameter can be a value of @ref TIM_Slave_Mode */
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248 uint32_t InputTrigger; /*!< Input Trigger source
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249 This parameter can be a value of @ref TIM_Trigger_Selection */
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250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
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251 This parameter can be a value of @ref TIM_Trigger_Polarity */
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252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
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253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
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254 uint32_t TriggerFilter; /*!< Input trigger filter
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255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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257 } TIM_SlaveConfigTypeDef;
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260 * @brief TIM Break input(s) and Dead time configuration Structure definition
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261 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
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262 * filter and polarity.
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266 uint32_t OffStateRunMode; /*!< TIM off state in run mode
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267 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
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268 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
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269 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
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270 uint32_t LockLevel; /*!< TIM Lock level
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271 This parameter can be a value of @ref TIM_Lock_level */
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272 uint32_t DeadTime; /*!< TIM dead Time
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273 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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274 uint32_t BreakState; /*!< TIM Break State
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275 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
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276 uint32_t BreakPolarity; /*!< TIM Break input polarity
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277 This parameter can be a value of @ref TIM_Break_Polarity */
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278 uint32_t BreakFilter; /*!< Specifies the break input filter.
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279 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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280 uint32_t Break2State; /*!< TIM Break2 State
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281 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
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282 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
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283 This parameter can be a value of @ref TIM_Break2_Polarity */
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284 uint32_t Break2Filter; /*!< TIM break2 input filter.
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285 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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286 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
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287 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
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288 } TIM_BreakDeadTimeConfigTypeDef;
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291 * @brief HAL State structures definition
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295 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
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296 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
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297 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
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298 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
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299 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
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300 } HAL_TIM_StateTypeDef;
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303 * @brief HAL Active channel structures definition
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307 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
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308 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
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309 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
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310 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
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311 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
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312 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
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313 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
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314 } HAL_TIM_ActiveChannel;
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317 * @brief TIM Time Base Handle Structure definition
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319 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
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320 typedef struct __TIM_HandleTypeDef
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323 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
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325 TIM_TypeDef *Instance; /*!< Register base address */
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326 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
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327 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
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328 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
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329 This array is accessed by a @ref DMA_Handle_index */
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330 HAL_LockTypeDef Lock; /*!< Locking object */
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331 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
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333 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
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334 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
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335 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
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336 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
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337 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
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338 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
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339 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
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340 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
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341 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
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342 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
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343 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
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344 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
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345 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
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346 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
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347 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
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348 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
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349 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
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350 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
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351 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
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352 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
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353 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
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354 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
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355 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
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356 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
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357 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
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358 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
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359 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
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360 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
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361 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
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362 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
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363 } TIM_HandleTypeDef;
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365 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
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367 * @brief HAL TIM Callback ID enumeration definition
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371 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
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372 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
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373 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
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374 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
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375 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
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376 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
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377 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
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378 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
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379 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
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380 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
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381 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
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382 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
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383 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
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384 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
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385 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
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386 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
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387 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
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388 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
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390 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
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391 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
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392 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
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393 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
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394 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
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395 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
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396 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
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397 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
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398 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
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399 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
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400 } HAL_TIM_CallbackIDTypeDef;
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403 * @brief HAL TIM Callback pointer definition
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405 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
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407 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
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412 /* End of exported types -----------------------------------------------------*/
\r
414 /* Exported constants --------------------------------------------------------*/
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415 /** @defgroup TIM_Exported_Constants TIM Exported Constants
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419 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
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422 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
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423 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
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424 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */
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429 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
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432 #define TIM_DMABASE_CR1 0x00000000U
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433 #define TIM_DMABASE_CR2 0x00000001U
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434 #define TIM_DMABASE_SMCR 0x00000002U
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435 #define TIM_DMABASE_DIER 0x00000003U
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436 #define TIM_DMABASE_SR 0x00000004U
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437 #define TIM_DMABASE_EGR 0x00000005U
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438 #define TIM_DMABASE_CCMR1 0x00000006U
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439 #define TIM_DMABASE_CCMR2 0x00000007U
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440 #define TIM_DMABASE_CCER 0x00000008U
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441 #define TIM_DMABASE_CNT 0x00000009U
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442 #define TIM_DMABASE_PSC 0x0000000AU
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443 #define TIM_DMABASE_ARR 0x0000000BU
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444 #define TIM_DMABASE_RCR 0x0000000CU
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445 #define TIM_DMABASE_CCR1 0x0000000DU
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446 #define TIM_DMABASE_CCR2 0x0000000EU
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447 #define TIM_DMABASE_CCR3 0x0000000FU
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448 #define TIM_DMABASE_CCR4 0x00000010U
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449 #define TIM_DMABASE_BDTR 0x00000011U
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450 #define TIM_DMABASE_DCR 0x00000012U
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451 #define TIM_DMABASE_DMAR 0x00000013U
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452 #define TIM_DMABASE_OR1 0x00000014U
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453 #define TIM_DMABASE_CCMR3 0x00000015U
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454 #define TIM_DMABASE_CCR5 0x00000016U
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455 #define TIM_DMABASE_CCR6 0x00000017U
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456 #define TIM_DMABASE_OR2 0x00000018U
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457 #define TIM_DMABASE_OR3 0x00000019U
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462 /** @defgroup TIM_Event_Source TIM Event Source
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465 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
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466 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
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467 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
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468 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
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469 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
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470 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
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471 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
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472 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
\r
473 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
\r
478 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
\r
481 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
\r
482 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
\r
483 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
\r
488 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
\r
491 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
\r
492 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
\r
497 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
\r
500 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
\r
501 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
\r
502 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
\r
503 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
\r
508 /** @defgroup TIM_Counter_Mode TIM Counter Mode
\r
511 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
\r
512 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
\r
513 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
\r
514 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
\r
515 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
\r
520 /** @defgroup TIM_ClockDivision TIM Clock Division
\r
523 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
\r
524 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
\r
525 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
\r
530 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
\r
533 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
\r
534 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
\r
539 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
\r
542 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
\r
543 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
\r
549 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
\r
552 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
\r
553 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
\r
558 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
\r
561 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
\r
562 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
\r
567 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
\r
570 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
\r
571 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
\r
576 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
\r
579 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
\r
580 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
\r
585 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
\r
588 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
\r
589 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
\r
594 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
\r
597 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
\r
598 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
\r
603 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
\r
606 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
\r
607 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
\r
608 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
\r
613 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
\r
616 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
\r
617 connected to IC1, IC2, IC3 or IC4, respectively */
\r
618 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
\r
619 connected to IC2, IC1, IC4 or IC3, respectively */
\r
620 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
\r
625 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
\r
628 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
\r
629 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
\r
630 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
\r
631 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
\r
636 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
\r
639 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
\r
640 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
\r
645 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
\r
648 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
\r
649 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
\r
650 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
\r
655 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
\r
658 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
\r
659 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
\r
660 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
\r
661 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
\r
662 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
\r
663 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
\r
664 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
\r
665 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
\r
670 /** @defgroup TIM_Commutation_Source TIM Commutation Source
\r
673 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
\r
674 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
\r
679 /** @defgroup TIM_DMA_sources TIM DMA Sources
\r
682 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
\r
683 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
\r
684 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
\r
685 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
\r
686 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
\r
687 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
\r
688 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
\r
693 /** @defgroup TIM_Flag_definition TIM Flag Definition
\r
696 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
\r
697 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
\r
698 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
\r
699 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
\r
700 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
\r
701 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
\r
702 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
\r
703 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
\r
704 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
\r
705 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
\r
706 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
\r
707 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
\r
708 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
\r
709 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
\r
710 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
\r
711 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
\r
716 /** @defgroup TIM_Channel TIM Channel
\r
719 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
\r
720 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
\r
721 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
\r
722 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
\r
723 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
\r
724 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
\r
725 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
\r
730 /** @defgroup TIM_Clock_Source TIM Clock Source
\r
733 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
\r
734 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
\r
735 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
\r
736 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
\r
737 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
\r
738 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
\r
739 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
\r
740 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
\r
741 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
\r
742 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
\r
747 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
\r
750 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
\r
751 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
\r
752 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
\r
753 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
\r
754 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
\r
759 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
\r
762 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
763 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
\r
764 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
\r
765 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
\r
770 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
\r
773 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
\r
774 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
\r
779 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
\r
782 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
783 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
\r
784 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
\r
785 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
\r
790 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
\r
793 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
\r
794 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
\r
799 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
\r
802 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
\r
803 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
\r
807 /** @defgroup TIM_Lock_level TIM Lock level
\r
810 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
\r
811 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
\r
812 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
\r
813 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
\r
818 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
\r
821 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
\r
822 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
\r
827 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
\r
830 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
\r
831 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
\r
836 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
\r
839 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
\r
840 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
\r
845 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
\r
848 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
\r
849 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
\r
854 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
\r
857 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
\r
858 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
\r
859 (if none of the break inputs BRK and BRK2 is active) */
\r
864 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
\r
867 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
\r
868 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
\r
869 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
\r
870 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
\r
875 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
\r
878 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
\r
879 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
\r
880 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
\r
881 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
\r
882 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
\r
883 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
\r
884 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
\r
885 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
\r
890 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
\r
893 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
\r
894 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
\r
895 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
\r
896 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
\r
897 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
\r
898 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
\r
899 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
\r
900 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
\r
901 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
\r
902 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
\r
903 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
\r
904 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
\r
905 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
\r
906 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
\r
907 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
\r
908 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
\r
913 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
\r
916 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
\r
917 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
\r
922 /** @defgroup TIM_Slave_Mode TIM Slave mode
\r
925 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
\r
926 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
\r
927 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
\r
928 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
\r
929 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
\r
930 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
\r
935 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
\r
938 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
\r
939 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
\r
940 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
\r
941 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
\r
942 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
\r
943 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
\r
944 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
\r
945 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
\r
946 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
\r
947 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
\r
948 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
\r
949 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
\r
950 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
\r
951 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
\r
956 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
\r
959 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
\r
960 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
\r
961 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
\r
962 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
\r
963 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
\r
964 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
\r
965 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
\r
966 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
\r
967 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
\r
972 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
\r
975 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
\r
976 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
\r
977 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
978 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
979 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
984 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
\r
987 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
988 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
\r
989 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
\r
990 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
\r
995 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
\r
998 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
\r
999 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
\r
1004 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
\r
1007 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1008 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1009 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1010 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1011 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1012 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1013 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1014 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1015 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1016 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1017 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1018 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1019 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1020 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1021 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1022 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1023 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1024 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
1029 /** @defgroup DMA_Handle_index TIM DMA Handle Index
\r
1032 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
\r
1033 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
\r
1034 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
\r
1035 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
\r
1036 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
\r
1037 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
\r
1038 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
\r
1043 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
\r
1046 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
\r
1047 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
\r
1048 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
\r
1049 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
\r
1054 /** @defgroup TIM_Break_System TIM Break System
\r
1057 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
\r
1058 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
\r
1059 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
\r
1060 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
\r
1068 /* End of exported constants -------------------------------------------------*/
\r
1070 /* Exported macros -----------------------------------------------------------*/
\r
1071 /** @defgroup TIM_Exported_Macros TIM Exported Macros
\r
1075 /** @brief Reset TIM handle state.
\r
1076 * @param __HANDLE__ TIM handle.
\r
1079 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
\r
1080 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
\r
1081 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
\r
1082 (__HANDLE__)->Base_MspInitCallback = NULL; \
\r
1083 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
\r
1084 (__HANDLE__)->IC_MspInitCallback = NULL; \
\r
1085 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
\r
1086 (__HANDLE__)->OC_MspInitCallback = NULL; \
\r
1087 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
\r
1088 (__HANDLE__)->PWM_MspInitCallback = NULL; \
\r
1089 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
\r
1090 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
\r
1091 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
\r
1092 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
\r
1093 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
\r
1094 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
\r
1095 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
\r
1098 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
\r
1099 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
\r
1102 * @brief Enable the TIM peripheral.
\r
1103 * @param __HANDLE__ TIM handle
\r
1106 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
\r
1109 * @brief Enable the TIM main Output.
\r
1110 * @param __HANDLE__ TIM handle
\r
1113 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
\r
1116 * @brief Disable the TIM peripheral.
\r
1117 * @param __HANDLE__ TIM handle
\r
1120 #define __HAL_TIM_DISABLE(__HANDLE__) \
\r
1122 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
\r
1124 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
\r
1126 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
\r
1132 * @brief Disable the TIM main Output.
\r
1133 * @param __HANDLE__ TIM handle
\r
1135 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
\r
1137 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
\r
1139 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
\r
1141 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
\r
1143 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
\r
1149 * @brief Disable the TIM main Output.
\r
1150 * @param __HANDLE__ TIM handle
\r
1152 * @note The Main Output Enable of a timer instance is disabled unconditionally
\r
1154 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
\r
1156 /** @brief Enable the specified TIM interrupt.
\r
1157 * @param __HANDLE__ specifies the TIM Handle.
\r
1158 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
\r
1159 * This parameter can be one of the following values:
\r
1160 * @arg TIM_IT_UPDATE: Update interrupt
\r
1161 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
1162 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
1163 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
1164 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
1165 * @arg TIM_IT_COM: Commutation interrupt
\r
1166 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
1167 * @arg TIM_IT_BREAK: Break interrupt
\r
1170 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
\r
1172 /** @brief Disable the specified TIM interrupt.
\r
1173 * @param __HANDLE__ specifies the TIM Handle.
\r
1174 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
\r
1175 * This parameter can be one of the following values:
\r
1176 * @arg TIM_IT_UPDATE: Update interrupt
\r
1177 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
1178 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
1179 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
1180 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
1181 * @arg TIM_IT_COM: Commutation interrupt
\r
1182 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
1183 * @arg TIM_IT_BREAK: Break interrupt
\r
1186 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
\r
1188 /** @brief Enable the specified DMA request.
\r
1189 * @param __HANDLE__ specifies the TIM Handle.
\r
1190 * @param __DMA__ specifies the TIM DMA request to enable.
\r
1191 * This parameter can be one of the following values:
\r
1192 * @arg TIM_DMA_UPDATE: Update DMA request
\r
1193 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
\r
1194 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
\r
1195 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
\r
1196 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
\r
1197 * @arg TIM_DMA_COM: Commutation DMA request
\r
1198 * @arg TIM_DMA_TRIGGER: Trigger DMA request
\r
1201 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
\r
1203 /** @brief Disable the specified DMA request.
\r
1204 * @param __HANDLE__ specifies the TIM Handle.
\r
1205 * @param __DMA__ specifies the TIM DMA request to disable.
\r
1206 * This parameter can be one of the following values:
\r
1207 * @arg TIM_DMA_UPDATE: Update DMA request
\r
1208 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
\r
1209 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
\r
1210 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
\r
1211 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
\r
1212 * @arg TIM_DMA_COM: Commutation DMA request
\r
1213 * @arg TIM_DMA_TRIGGER: Trigger DMA request
\r
1216 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
\r
1218 /** @brief Check whether the specified TIM interrupt flag is set or not.
\r
1219 * @param __HANDLE__ specifies the TIM Handle.
\r
1220 * @param __FLAG__ specifies the TIM interrupt flag to check.
\r
1221 * This parameter can be one of the following values:
\r
1222 * @arg TIM_FLAG_UPDATE: Update interrupt flag
\r
1223 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
\r
1224 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
\r
1225 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
\r
1226 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
\r
1227 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
\r
1228 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
\r
1229 * @arg TIM_FLAG_COM: Commutation interrupt flag
\r
1230 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
\r
1231 * @arg TIM_FLAG_BREAK: Break interrupt flag
\r
1232 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
\r
1233 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
\r
1234 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
\r
1235 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
\r
1236 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
\r
1237 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
\r
1238 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
1240 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
\r
1242 /** @brief Clear the specified TIM interrupt flag.
\r
1243 * @param __HANDLE__ specifies the TIM Handle.
\r
1244 * @param __FLAG__ specifies the TIM interrupt flag to clear.
\r
1245 * This parameter can be one of the following values:
\r
1246 * @arg TIM_FLAG_UPDATE: Update interrupt flag
\r
1247 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
\r
1248 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
\r
1249 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
\r
1250 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
\r
1251 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
\r
1252 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
\r
1253 * @arg TIM_FLAG_COM: Commutation interrupt flag
\r
1254 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
\r
1255 * @arg TIM_FLAG_BREAK: Break interrupt flag
\r
1256 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
\r
1257 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
\r
1258 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
\r
1259 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
\r
1260 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
\r
1261 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
\r
1262 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
1264 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
\r
1267 * @brief Check whether the specified TIM interrupt source is enabled or not.
\r
1268 * @param __HANDLE__ TIM handle
\r
1269 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
\r
1270 * This parameter can be one of the following values:
\r
1271 * @arg TIM_IT_UPDATE: Update interrupt
\r
1272 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
1273 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
1274 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
1275 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
1276 * @arg TIM_IT_COM: Commutation interrupt
\r
1277 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
1278 * @arg TIM_IT_BREAK: Break interrupt
\r
1279 * @retval The state of TIM_IT (SET or RESET).
\r
1281 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
\r
1282 == (__INTERRUPT__)) ? SET : RESET)
\r
1284 /** @brief Clear the TIM interrupt pending bits.
\r
1285 * @param __HANDLE__ TIM handle
\r
1286 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
\r
1287 * This parameter can be one of the following values:
\r
1288 * @arg TIM_IT_UPDATE: Update interrupt
\r
1289 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
1290 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
1291 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
1292 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
1293 * @arg TIM_IT_COM: Commutation interrupt
\r
1294 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
1295 * @arg TIM_IT_BREAK: Break interrupt
\r
1298 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
\r
1301 * @brief Indicates whether or not the TIM Counter is used as downcounter.
\r
1302 * @param __HANDLE__ TIM handle.
\r
1303 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
\r
1304 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
\r
1307 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
\r
1310 * @brief Set the TIM Prescaler on runtime.
\r
1311 * @param __HANDLE__ TIM handle.
\r
1312 * @param __PRESC__ specifies the Prescaler new value.
\r
1315 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
\r
1318 * @brief Set the TIM Counter Register value on runtime.
\r
1319 * @param __HANDLE__ TIM handle.
\r
1320 * @param __COUNTER__ specifies the Counter register new value.
\r
1323 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
\r
1326 * @brief Get the TIM Counter Register value on runtime.
\r
1327 * @param __HANDLE__ TIM handle.
\r
1328 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
\r
1330 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
\r
1333 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
\r
1334 * @param __HANDLE__ TIM handle.
\r
1335 * @param __AUTORELOAD__ specifies the Counter register new value.
\r
1338 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
\r
1340 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
\r
1341 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
\r
1345 * @brief Get the TIM Autoreload Register value on runtime.
\r
1346 * @param __HANDLE__ TIM handle.
\r
1347 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
\r
1349 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
\r
1352 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
\r
1353 * @param __HANDLE__ TIM handle.
\r
1354 * @param __CKD__ specifies the clock division value.
\r
1355 * This parameter can be one of the following value:
\r
1356 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
\r
1357 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
\r
1358 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
\r
1361 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
\r
1363 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
\r
1364 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
\r
1365 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
\r
1369 * @brief Get the TIM Clock Division value on runtime.
\r
1370 * @param __HANDLE__ TIM handle.
\r
1371 * @retval The clock division can be one of the following values:
\r
1372 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
\r
1373 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
\r
1374 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
\r
1376 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
\r
1379 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
\r
1380 * @param __HANDLE__ TIM handle.
\r
1381 * @param __CHANNEL__ TIM Channels to be configured.
\r
1382 * This parameter can be one of the following values:
\r
1383 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1384 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1385 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1386 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1387 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
\r
1388 * This parameter can be one of the following values:
\r
1389 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1390 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1391 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1392 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1395 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
\r
1397 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
\r
1398 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
\r
1402 * @brief Get the TIM Input Capture prescaler on runtime.
\r
1403 * @param __HANDLE__ TIM handle.
\r
1404 * @param __CHANNEL__ TIM Channels to be configured.
\r
1405 * This parameter can be one of the following values:
\r
1406 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
\r
1407 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
\r
1408 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
\r
1409 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
\r
1410 * @retval The input capture prescaler can be one of the following values:
\r
1411 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1412 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1413 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1414 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1416 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
\r
1417 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
\r
1418 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
\r
1419 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
\r
1420 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
\r
1423 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
\r
1424 * @param __HANDLE__ TIM handle.
\r
1425 * @param __CHANNEL__ TIM Channels to be configured.
\r
1426 * This parameter can be one of the following values:
\r
1427 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1428 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1429 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1430 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1431 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
\r
1432 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
\r
1433 * @param __COMPARE__ specifies the Capture Compare register new value.
\r
1436 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
\r
1437 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
\r
1438 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
\r
1439 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
\r
1440 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
\r
1441 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
\r
1442 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
\r
1445 * @brief Get the TIM Capture Compare Register value on runtime.
\r
1446 * @param __HANDLE__ TIM handle.
\r
1447 * @param __CHANNEL__ TIM Channel associated with the capture compare register
\r
1448 * This parameter can be one of the following values:
\r
1449 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
\r
1450 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
\r
1451 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
\r
1452 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
\r
1453 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
\r
1454 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
\r
1455 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
\r
1457 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
\r
1458 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
\r
1459 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
\r
1460 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
\r
1461 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
\r
1462 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
\r
1463 ((__HANDLE__)->Instance->CCR6))
\r
1466 * @brief Set the TIM Output compare preload.
\r
1467 * @param __HANDLE__ TIM handle.
\r
1468 * @param __CHANNEL__ TIM Channels to be configured.
\r
1469 * This parameter can be one of the following values:
\r
1470 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1471 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1472 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1473 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1474 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
\r
1475 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
\r
1478 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
\r
1479 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
\r
1480 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
\r
1481 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
\r
1482 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
\r
1483 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
\r
1484 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
\r
1487 * @brief Reset the TIM Output compare preload.
\r
1488 * @param __HANDLE__ TIM handle.
\r
1489 * @param __CHANNEL__ TIM Channels to be configured.
\r
1490 * This parameter can be one of the following values:
\r
1491 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1492 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1493 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1494 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1495 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
\r
1496 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
\r
1499 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
\r
1500 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
\r
1501 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
\r
1502 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
\r
1503 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
\r
1504 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
\r
1505 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
\r
1508 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
\r
1509 * @param __HANDLE__ TIM handle.
\r
1510 * @note When the URS bit of the TIMx_CR1 register is set, only counter
\r
1511 * overflow/underflow generates an update interrupt or DMA request (if
\r
1515 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
\r
1518 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
\r
1519 * @param __HANDLE__ TIM handle.
\r
1520 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
\r
1521 * following events generate an update interrupt or DMA request (if
\r
1523 * _ Counter overflow underflow
\r
1524 * _ Setting the UG bit
\r
1525 * _ Update generation through the slave mode controller
\r
1528 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
\r
1531 * @brief Set the TIM Capture x input polarity on runtime.
\r
1532 * @param __HANDLE__ TIM handle.
\r
1533 * @param __CHANNEL__ TIM Channels to be configured.
\r
1534 * This parameter can be one of the following values:
\r
1535 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1536 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1537 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1538 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1539 * @param __POLARITY__ Polarity for TIx source
\r
1540 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
\r
1541 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
\r
1542 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
\r
1545 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
\r
1547 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
\r
1548 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
\r
1554 /* End of exported macros ----------------------------------------------------*/
\r
1556 /* Private constants ---------------------------------------------------------*/
\r
1557 /** @defgroup TIM_Private_Constants TIM Private Constants
\r
1560 /* The counter of a timer instance is disabled only if all the CCx and CCxN
\r
1561 channels have been disabled */
\r
1562 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
\r
1563 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
\r
1567 /* End of private constants --------------------------------------------------*/
\r
1569 /* Private macros ------------------------------------------------------------*/
\r
1570 /** @defgroup TIM_Private_Macros TIM Private Macros
\r
1573 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
\r
1574 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
\r
1575 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
\r
1577 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
\r
1578 ((__BASE__) == TIM_DMABASE_CR2) || \
\r
1579 ((__BASE__) == TIM_DMABASE_SMCR) || \
\r
1580 ((__BASE__) == TIM_DMABASE_DIER) || \
\r
1581 ((__BASE__) == TIM_DMABASE_SR) || \
\r
1582 ((__BASE__) == TIM_DMABASE_EGR) || \
\r
1583 ((__BASE__) == TIM_DMABASE_CCMR1) || \
\r
1584 ((__BASE__) == TIM_DMABASE_CCMR2) || \
\r
1585 ((__BASE__) == TIM_DMABASE_CCER) || \
\r
1586 ((__BASE__) == TIM_DMABASE_CNT) || \
\r
1587 ((__BASE__) == TIM_DMABASE_PSC) || \
\r
1588 ((__BASE__) == TIM_DMABASE_ARR) || \
\r
1589 ((__BASE__) == TIM_DMABASE_RCR) || \
\r
1590 ((__BASE__) == TIM_DMABASE_CCR1) || \
\r
1591 ((__BASE__) == TIM_DMABASE_CCR2) || \
\r
1592 ((__BASE__) == TIM_DMABASE_CCR3) || \
\r
1593 ((__BASE__) == TIM_DMABASE_CCR4) || \
\r
1594 ((__BASE__) == TIM_DMABASE_BDTR) || \
\r
1595 ((__BASE__) == TIM_DMABASE_OR1) || \
\r
1596 ((__BASE__) == TIM_DMABASE_CCMR3) || \
\r
1597 ((__BASE__) == TIM_DMABASE_CCR5) || \
\r
1598 ((__BASE__) == TIM_DMABASE_CCR6) || \
\r
1599 ((__BASE__) == TIM_DMABASE_OR2) || \
\r
1600 ((__BASE__) == TIM_DMABASE_OR3))
\r
1602 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
\r
1604 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
\r
1605 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
\r
1606 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
\r
1607 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
\r
1608 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
\r
1610 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
\r
1611 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
\r
1612 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
\r
1614 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
\r
1615 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
\r
1617 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
\r
1618 ((__STATE__) == TIM_OCFAST_ENABLE))
\r
1620 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
\r
1621 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
\r
1623 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
\r
1624 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
\r
1626 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
\r
1627 ((__STATE__) == TIM_OCIDLESTATE_RESET))
\r
1629 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
\r
1630 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
\r
1632 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
\r
1633 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
\r
1634 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
\r
1636 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
\r
1637 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
\r
1638 ((__SELECTION__) == TIM_ICSELECTION_TRC))
\r
1640 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
\r
1641 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
\r
1642 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
\r
1643 ((__PRESCALER__) == TIM_ICPSC_DIV8))
\r
1645 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
\r
1646 ((__MODE__) == TIM_OPMODE_REPETITIVE))
\r
1648 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
\r
1649 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
\r
1650 ((__MODE__) == TIM_ENCODERMODE_TI12))
\r
1652 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
\r
1654 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
1655 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
1656 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
1657 ((__CHANNEL__) == TIM_CHANNEL_4) || \
\r
1658 ((__CHANNEL__) == TIM_CHANNEL_5) || \
\r
1659 ((__CHANNEL__) == TIM_CHANNEL_6) || \
\r
1660 ((__CHANNEL__) == TIM_CHANNEL_ALL))
\r
1662 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
1663 ((__CHANNEL__) == TIM_CHANNEL_2))
\r
1665 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
1666 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
1667 ((__CHANNEL__) == TIM_CHANNEL_3))
\r
1669 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
\r
1670 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
\r
1671 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
\r
1672 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
\r
1673 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
\r
1674 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
\r
1675 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
\r
1676 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
\r
1677 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
\r
1678 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
\r
1680 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
\r
1681 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
\r
1682 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
\r
1683 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
\r
1684 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
\r
1686 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
\r
1687 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
\r
1688 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
\r
1689 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
\r
1691 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1693 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
\r
1694 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
\r
1696 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
\r
1697 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
\r
1698 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
\r
1699 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
\r
1701 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1703 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
\r
1704 ((__STATE__) == TIM_OSSR_DISABLE))
\r
1706 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
\r
1707 ((__STATE__) == TIM_OSSI_DISABLE))
\r
1709 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
\r
1710 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
\r
1711 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
\r
1712 ((__LEVEL__) == TIM_LOCKLEVEL_3))
\r
1714 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
\r
1717 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
\r
1718 ((__STATE__) == TIM_BREAK_DISABLE))
\r
1720 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
\r
1721 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
\r
1723 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
\r
1724 ((__STATE__) == TIM_BREAK2_DISABLE))
\r
1726 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
\r
1727 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
\r
1729 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
\r
1730 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
\r
1732 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
\r
1734 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
\r
1735 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
\r
1736 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
\r
1737 ((__SOURCE__) == TIM_TRGO_OC1) || \
\r
1738 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
\r
1739 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
\r
1740 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
\r
1741 ((__SOURCE__) == TIM_TRGO_OC4REF))
\r
1743 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
\r
1744 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
\r
1745 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
\r
1746 ((__SOURCE__) == TIM_TRGO2_OC1) || \
\r
1747 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
\r
1748 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
\r
1749 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
\r
1750 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
\r
1751 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
\r
1752 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
\r
1753 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
\r
1754 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
\r
1755 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
\r
1756 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
\r
1757 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
\r
1758 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
\r
1759 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
\r
1761 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
\r
1762 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
\r
1764 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
\r
1765 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
\r
1766 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
\r
1767 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
\r
1768 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
\r
1769 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
\r
1771 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
\r
1772 ((__MODE__) == TIM_OCMODE_PWM2) || \
\r
1773 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
\r
1774 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
\r
1775 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
\r
1776 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
\r
1778 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
\r
1779 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
\r
1780 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
\r
1781 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
\r
1782 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
\r
1783 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
\r
1784 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
\r
1785 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
\r
1787 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
\r
1788 ((__SELECTION__) == TIM_TS_ITR1) || \
\r
1789 ((__SELECTION__) == TIM_TS_ITR2) || \
\r
1790 ((__SELECTION__) == TIM_TS_ITR3) || \
\r
1791 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
\r
1792 ((__SELECTION__) == TIM_TS_TI1FP1) || \
\r
1793 ((__SELECTION__) == TIM_TS_TI2FP2) || \
\r
1794 ((__SELECTION__) == TIM_TS_ETRF))
\r
1796 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
\r
1797 ((__SELECTION__) == TIM_TS_ITR1) || \
\r
1798 ((__SELECTION__) == TIM_TS_ITR2) || \
\r
1799 ((__SELECTION__) == TIM_TS_ITR3) || \
\r
1800 ((__SELECTION__) == TIM_TS_NONE))
\r
1802 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
\r
1803 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
\r
1804 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
\r
1805 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
\r
1806 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
\r
1808 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
\r
1809 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
\r
1810 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
\r
1811 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
\r
1813 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1815 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
\r
1816 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
\r
1818 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
\r
1819 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
\r
1820 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
\r
1821 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
\r
1822 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
\r
1823 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
\r
1824 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
\r
1825 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
\r
1826 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
\r
1827 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
\r
1828 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
\r
1829 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
\r
1830 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
\r
1831 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
\r
1832 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
\r
1833 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
\r
1834 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
\r
1835 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
\r
1837 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1839 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
\r
1841 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
\r
1842 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
\r
1843 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \
\r
1844 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
\r
1846 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
\r
1847 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
\r
1849 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
\r
1850 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
\r
1851 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
\r
1852 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
\r
1853 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
\r
1855 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
\r
1856 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
\r
1857 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
\r
1858 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
\r
1859 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
\r
1861 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
\r
1862 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
\r
1863 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
\r
1864 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
\r
1865 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
\r
1867 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
\r
1868 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
\r
1869 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
\r
1870 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
\r
1871 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
\r
1876 /* End of private macros -----------------------------------------------------*/
\r
1878 /* Include TIM HAL Extended module */
\r
1879 #include "stm32l4xx_hal_tim_ex.h"
\r
1881 /* Exported functions --------------------------------------------------------*/
\r
1882 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
\r
1886 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
\r
1887 * @brief Time Base functions
\r
1890 /* Time Base functions ********************************************************/
\r
1891 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
\r
1892 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
\r
1893 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
\r
1894 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
\r
1895 /* Blocking mode: Polling */
\r
1896 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
\r
1897 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
\r
1898 /* Non-Blocking mode: Interrupt */
\r
1899 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
\r
1900 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
\r
1901 /* Non-Blocking mode: DMA */
\r
1902 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
\r
1903 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
\r
1908 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
\r
1909 * @brief TIM Output Compare functions
\r
1912 /* Timer Output Compare functions *********************************************/
\r
1913 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
\r
1914 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
\r
1915 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
\r
1916 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
\r
1917 /* Blocking mode: Polling */
\r
1918 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1919 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1920 /* Non-Blocking mode: Interrupt */
\r
1921 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1922 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1923 /* Non-Blocking mode: DMA */
\r
1924 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1925 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1930 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
\r
1931 * @brief TIM PWM functions
\r
1934 /* Timer PWM functions ********************************************************/
\r
1935 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
\r
1936 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
\r
1937 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
\r
1938 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
\r
1939 /* Blocking mode: Polling */
\r
1940 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1941 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1942 /* Non-Blocking mode: Interrupt */
\r
1943 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1944 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1945 /* Non-Blocking mode: DMA */
\r
1946 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1947 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1952 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
\r
1953 * @brief TIM Input Capture functions
\r
1956 /* Timer Input Capture functions **********************************************/
\r
1957 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
\r
1958 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
\r
1959 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
\r
1960 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
\r
1961 /* Blocking mode: Polling */
\r
1962 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1963 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1964 /* Non-Blocking mode: Interrupt */
\r
1965 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1966 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1967 /* Non-Blocking mode: DMA */
\r
1968 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1969 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1974 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
\r
1975 * @brief TIM One Pulse functions
\r
1978 /* Timer One Pulse functions **************************************************/
\r
1979 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
\r
1980 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
\r
1981 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
\r
1982 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
\r
1983 /* Blocking mode: Polling */
\r
1984 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1985 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1986 /* Non-Blocking mode: Interrupt */
\r
1987 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1988 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1993 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
\r
1994 * @brief TIM Encoder functions
\r
1997 /* Timer Encoder functions ****************************************************/
\r
1998 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
\r
1999 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
\r
2000 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
\r
2001 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
\r
2002 /* Blocking mode: Polling */
\r
2003 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
2004 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
2005 /* Non-Blocking mode: Interrupt */
\r
2006 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
2007 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
2008 /* Non-Blocking mode: DMA */
\r
2009 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
\r
2010 uint32_t *pData2, uint16_t Length);
\r
2011 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
2016 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
\r
2017 * @brief IRQ handler management
\r
2020 /* Interrupt Handler functions ***********************************************/
\r
2021 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
\r
2026 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
\r
2027 * @brief Peripheral Control functions
\r
2030 /* Control functions *********************************************************/
\r
2031 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
\r
2032 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
\r
2033 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
\r
2034 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
\r
2035 uint32_t OutputChannel, uint32_t InputChannel);
\r
2036 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
\r
2037 uint32_t Channel);
\r
2038 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
\r
2039 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
\r
2040 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
\r
2041 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
\r
2042 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
\r
2043 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
\r
2044 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
\r
2045 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
\r
2046 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
\r
2047 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
\r
2048 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
\r
2049 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
2054 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
\r
2055 * @brief TIM Callbacks functions
\r
2058 /* Callback in non blocking modes (Interrupt and DMA) *************************/
\r
2059 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
\r
2060 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
2061 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
\r
2062 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
\r
2063 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
2064 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
\r
2065 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
2066 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
\r
2067 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
2068 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
\r
2070 /* Callbacks Register/UnRegister functions ***********************************/
\r
2071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
\r
2072 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
\r
2073 pTIM_CallbackTypeDef pCallback);
\r
2074 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
\r
2075 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
\r
2081 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
\r
2082 * @brief Peripheral State functions
\r
2085 /* Peripheral State functions ************************************************/
\r
2086 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
\r
2087 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
\r
2088 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
\r
2089 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
\r
2090 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
\r
2091 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
\r
2099 /* End of exported functions -------------------------------------------------*/
\r
2101 /* Private functions----------------------------------------------------------*/
\r
2102 /** @defgroup TIM_Private_Functions TIM Private Functions
\r
2105 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
\r
2106 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
\r
2107 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
\r
2108 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
\r
2109 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
\r
2111 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
\r
2112 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
\r
2113 void TIM_DMAError(DMA_HandleTypeDef *hdma);
\r
2114 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
\r
2115 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
\r
2116 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
\r
2118 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
\r
2119 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
\r
2120 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
\r
2125 /* End of private functions --------------------------------------------------*/
\r
2135 #ifdef __cplusplus
\r
2139 #endif /* STM32L4xx_HAL_TIM_H */
\r
2141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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