1 /***************************************************************************//**
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3 * @brief Analog to Digital Converter (ADC) peripheral API
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5 *******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
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8 *******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
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21 * obligation to support this Software. Silicon Labs is providing the
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22 * Software "AS IS", with no express or implied warranties of any kind,
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23 * including, but not limited to, any implied warranties of merchantability
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24 * or fitness for any particular purpose or warranties against infringement
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25 * of any proprietary rights of a third party.
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27 * Silicon Labs will not be liable for any consequential, incidental, or
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28 * special damages, or any other relief, or for any claim by any third party,
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29 * arising from your use of this Software.
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31 ******************************************************************************/
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33 #ifndef __SILICON_LABS_EM_ADC_H__
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34 #define __SILICON_LABS_EM_ADC_H__
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36 #include "em_device.h"
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37 #if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
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39 #include <stdbool.h>
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45 /***************************************************************************//**
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46 * @addtogroup EM_Library
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48 ******************************************************************************/
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50 /***************************************************************************//**
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53 ******************************************************************************/
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55 /*******************************************************************************
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56 ******************************** ENUMS ************************************
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57 ******************************************************************************/
\r
59 /** Acquisition time (in ADC clock cycles). */
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62 adcAcqTime1 = _ADC_SINGLECTRL_AT_1CYCLE, /**< 1 clock cycle. */
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63 adcAcqTime2 = _ADC_SINGLECTRL_AT_2CYCLES, /**< 2 clock cycles. */
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64 adcAcqTime4 = _ADC_SINGLECTRL_AT_4CYCLES, /**< 4 clock cycles. */
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65 adcAcqTime8 = _ADC_SINGLECTRL_AT_8CYCLES, /**< 8 clock cycles. */
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66 adcAcqTime16 = _ADC_SINGLECTRL_AT_16CYCLES, /**< 16 clock cycles. */
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67 adcAcqTime32 = _ADC_SINGLECTRL_AT_32CYCLES, /**< 32 clock cycles. */
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68 adcAcqTime64 = _ADC_SINGLECTRL_AT_64CYCLES, /**< 64 clock cycles. */
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69 adcAcqTime128 = _ADC_SINGLECTRL_AT_128CYCLES, /**< 128 clock cycles. */
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70 adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES /**< 256 clock cycles. */
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71 } ADC_AcqTime_TypeDef;
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73 #if defined( _ADC_CTRL_LPFMODE_MASK )
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74 /** Lowpass filter mode. */
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77 /** No filter or decoupling capacitor. */
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78 adcLPFilterBypass = _ADC_CTRL_LPFMODE_BYPASS,
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80 /** On-chip RC filter. */
\r
81 adcLPFilterRC = _ADC_CTRL_LPFMODE_RCFILT,
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83 /** On-chip decoupling capacitor. */
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84 adcLPFilterDeCap = _ADC_CTRL_LPFMODE_DECAP
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85 } ADC_LPFilter_TypeDef;
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88 /** Oversample rate select. */
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91 /** 2 samples per conversion result. */
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92 adcOvsRateSel2 = _ADC_CTRL_OVSRSEL_X2,
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94 /** 4 samples per conversion result. */
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95 adcOvsRateSel4 = _ADC_CTRL_OVSRSEL_X4,
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97 /** 8 samples per conversion result. */
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98 adcOvsRateSel8 = _ADC_CTRL_OVSRSEL_X8,
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100 /** 16 samples per conversion result. */
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101 adcOvsRateSel16 = _ADC_CTRL_OVSRSEL_X16,
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103 /** 32 samples per conversion result. */
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104 adcOvsRateSel32 = _ADC_CTRL_OVSRSEL_X32,
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106 /** 64 samples per conversion result. */
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107 adcOvsRateSel64 = _ADC_CTRL_OVSRSEL_X64,
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109 /** 128 samples per conversion result. */
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110 adcOvsRateSel128 = _ADC_CTRL_OVSRSEL_X128,
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112 /** 256 samples per conversion result. */
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113 adcOvsRateSel256 = _ADC_CTRL_OVSRSEL_X256,
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115 /** 512 samples per conversion result. */
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116 adcOvsRateSel512 = _ADC_CTRL_OVSRSEL_X512,
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118 /** 1024 samples per conversion result. */
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119 adcOvsRateSel1024 = _ADC_CTRL_OVSRSEL_X1024,
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121 /** 2048 samples per conversion result. */
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122 adcOvsRateSel2048 = _ADC_CTRL_OVSRSEL_X2048,
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124 /** 4096 samples per conversion result. */
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125 adcOvsRateSel4096 = _ADC_CTRL_OVSRSEL_X4096
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126 } ADC_OvsRateSel_TypeDef;
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129 /** Peripheral Reflex System signal used to trigger single sample. */
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132 #if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
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133 adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
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134 adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
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135 adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
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136 adcPRSSELCh3 = _ADC_SINGLECTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
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137 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH4 )
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138 adcPRSSELCh4 = _ADC_SINGLECTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
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140 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH5 )
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141 adcPRSSELCh5 = _ADC_SINGLECTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
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143 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH6 )
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144 adcPRSSELCh6 = _ADC_SINGLECTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
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146 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH7 )
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147 adcPRSSELCh7 = _ADC_SINGLECTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
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149 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH8 )
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150 adcPRSSELCh8 = _ADC_SINGLECTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
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152 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH9 )
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153 adcPRSSELCh9 = _ADC_SINGLECTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
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155 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH10 )
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156 adcPRSSELCh10 = _ADC_SINGLECTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
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158 #if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH11 )
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159 adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
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161 #elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK)
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162 adcPRSSELCh0 = _ADC_SINGLECTRLX_PRSSEL_PRSCH0, /**< PRS channel 0. */
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163 adcPRSSELCh1 = _ADC_SINGLECTRLX_PRSSEL_PRSCH1, /**< PRS channel 1. */
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164 adcPRSSELCh2 = _ADC_SINGLECTRLX_PRSSEL_PRSCH2, /**< PRS channel 2. */
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165 adcPRSSELCh3 = _ADC_SINGLECTRLX_PRSSEL_PRSCH3, /**< PRS channel 3. */
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166 adcPRSSELCh4 = _ADC_SINGLECTRLX_PRSSEL_PRSCH4, /**< PRS channel 4. */
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167 adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */
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168 adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */
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169 adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */
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170 adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */
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171 adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */
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172 adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */
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173 adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */
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174 #if defined( _ADC_SINGLECTRLX_PRSSEL_PRSCH12 )
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175 adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */
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176 adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */
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177 adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14, /**< PRS channel 14. */
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178 adcPRSSELCh15 = _ADC_SINGLECTRLX_PRSSEL_PRSCH15, /**< PRS channel 15. */
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181 } ADC_PRSSEL_TypeDef;
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184 /** Single and scan mode voltage references. Using unshifted enums and or
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185 in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */
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186 #if defined( _ADC_SCANCTRLX_VREFSEL_MASK )
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187 #define ADC_CTRLX_VREFSEL_REG 0x80
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191 /** Internal 1.25V reference. */
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192 adcRef1V25 = _ADC_SINGLECTRL_REF_1V25,
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194 /** Internal 2.5V reference. */
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195 adcRef2V5 = _ADC_SINGLECTRL_REF_2V5,
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197 /** Buffered VDD. */
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198 adcRefVDD = _ADC_SINGLECTRL_REF_VDD,
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200 /** Internal differential 5V reference. */
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201 adcRef5VDIFF = _ADC_SINGLECTRL_REF_5VDIFF,
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203 /** Single ended external reference from pin 6. */
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204 adcRefExtSingle = _ADC_SINGLECTRL_REF_EXTSINGLE,
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206 /** Differential external reference from pin 6 and 7. */
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207 adcRef2xExtDiff = _ADC_SINGLECTRL_REF_2XEXTDIFF,
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209 /** Unbuffered 2xVDD. */
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210 adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD,
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212 #if defined( _ADC_SINGLECTRLX_VREFSEL_VBGR )
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213 /** Custom VFS: Internal Bandgap reference */
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214 adcRefVBGR = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG,
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217 #if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
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218 /** Custom VFS: Scaled AVDD: AVDD * VREFATT */
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219 adcRefVddxAtt = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG,
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222 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPWATT )
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223 /** Custom VFS: Scaled singled ended external reference from pin 6:
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225 adcRefVPxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG,
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228 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFP )
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229 /** Custom VFS: Raw single ended external reference from pin 6. */
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230 adcRefP = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG,
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233 #if defined( _ADC_SINGLECTRLX_VREFSEL_VENTROPY )
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234 /** Custom VFS: Special mode for entropy generation */
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235 adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG,
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238 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT )
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239 /** Custom VFS: Scaled differential external Vref from pin 6 and 7:
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240 (VREFP - VREFN) * VREFATT */
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241 adcRefVPNxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG,
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244 #if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPN )
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245 /** Custom VFS: Raw differential external Vref from pin 6 and 7:
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247 adcRefPN = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG,
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252 /** Sample resolution. */
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255 adcRes12Bit = _ADC_SINGLECTRL_RES_12BIT, /**< 12 bit sampling. */
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256 adcRes8Bit = _ADC_SINGLECTRL_RES_8BIT, /**< 8 bit sampling. */
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257 adcRes6Bit = _ADC_SINGLECTRL_RES_6BIT, /**< 6 bit sampling. */
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258 adcResOVS = _ADC_SINGLECTRL_RES_OVS /**< Oversampling. */
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262 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
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263 /** Single sample input selection. */
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266 /* Differential mode disabled */
\r
267 adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */
\r
268 adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */
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269 adcSingleInputCh2 = _ADC_SINGLECTRL_INPUTSEL_CH2, /**< Channel 2. */
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270 adcSingleInputCh3 = _ADC_SINGLECTRL_INPUTSEL_CH3, /**< Channel 3. */
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271 adcSingleInputCh4 = _ADC_SINGLECTRL_INPUTSEL_CH4, /**< Channel 4. */
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272 adcSingleInputCh5 = _ADC_SINGLECTRL_INPUTSEL_CH5, /**< Channel 5. */
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273 adcSingleInputCh6 = _ADC_SINGLECTRL_INPUTSEL_CH6, /**< Channel 6. */
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274 adcSingleInputCh7 = _ADC_SINGLECTRL_INPUTSEL_CH7, /**< Channel 7. */
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275 adcSingleInputTemp = _ADC_SINGLECTRL_INPUTSEL_TEMP, /**< Temperature reference. */
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276 adcSingleInputVDDDiv3 = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3, /**< VDD divided by 3. */
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277 adcSingleInputVDD = _ADC_SINGLECTRL_INPUTSEL_VDD, /**< VDD. */
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278 adcSingleInputVSS = _ADC_SINGLECTRL_INPUTSEL_VSS, /**< VSS. */
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279 adcSingleInputVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */
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280 adcSingleInputDACOut0 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */
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281 adcSingleInputDACOut1 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */
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282 /* TBD: Use define when available */
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283 adcSingleInputATEST = 15, /**< ATEST. */
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285 /* Differential mode enabled */
\r
286 adcSingleInputCh0Ch1 = _ADC_SINGLECTRL_INPUTSEL_CH0CH1, /**< Positive Ch0, negative Ch1. */
\r
287 adcSingleInputCh2Ch3 = _ADC_SINGLECTRL_INPUTSEL_CH2CH3, /**< Positive Ch2, negative Ch3. */
\r
288 adcSingleInputCh4Ch5 = _ADC_SINGLECTRL_INPUTSEL_CH4CH5, /**< Positive Ch4, negative Ch5. */
\r
289 adcSingleInputCh6Ch7 = _ADC_SINGLECTRL_INPUTSEL_CH6CH7, /**< Positive Ch6, negative Ch7. */
\r
290 /* TBD: Use define when available */
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291 adcSingleInputDiff0 = 4 /**< Differential 0. */
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292 } ADC_SingleInput_TypeDef;
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294 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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295 /* Legacy enum names */
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296 #define adcSingleInpCh0 adcSingleInputCh0
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297 #define adcSingleInpCh1 adcSingleInputCh1
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298 #define adcSingleInpCh2 adcSingleInputCh2
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299 #define adcSingleInpCh3 adcSingleInputCh3
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300 #define adcSingleInpCh4 adcSingleInputCh4
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301 #define adcSingleInpCh5 adcSingleInputCh5
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302 #define adcSingleInpCh6 adcSingleInputCh6
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303 #define adcSingleInpCh7 adcSingleInputCh7
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304 #define adcSingleInpTemp adcSingleInputTemp
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305 #define adcSingleInpVDDDiv3 adcSingleInputVDDDiv3
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306 #define adcSingleInpVDD adcSingleInputVDD
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307 #define adcSingleInpVSS adcSingleInputVSS
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308 #define adcSingleInpVrefDiv2 adcSingleInputVrefDiv2
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309 #define adcSingleInpDACOut0 adcSingleInputDACOut0
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310 #define adcSingleInpDACOut1 adcSingleInputDACOut1
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311 #define adcSingleInpATEST adcSingleInputATEST
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312 #define adcSingleInpCh0Ch1 adcSingleInputCh0Ch1
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313 #define adcSingleInpCh2Ch3 adcSingleInputCh2Ch3
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314 #define adcSingleInpCh4Ch5 adcSingleInputCh4Ch5
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315 #define adcSingleInpCh6Ch7 adcSingleInputCh6Ch7
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316 #define adcSingleInpDiff0 adcSingleInputDiff0
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320 #if defined( _ADC_SINGLECTRL_POSSEL_MASK )
\r
321 /** Positive input selection for single and scan coversion. */
\r
324 adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
\r
325 adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
\r
326 adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,
\r
327 adcPosSelAPORT0XCH3 = _ADC_SINGLECTRL_POSSEL_APORT0XCH3,
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328 adcPosSelAPORT0XCH4 = _ADC_SINGLECTRL_POSSEL_APORT0XCH4,
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329 adcPosSelAPORT0XCH5 = _ADC_SINGLECTRL_POSSEL_APORT0XCH5,
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330 adcPosSelAPORT0XCH6 = _ADC_SINGLECTRL_POSSEL_APORT0XCH6,
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331 adcPosSelAPORT0XCH7 = _ADC_SINGLECTRL_POSSEL_APORT0XCH7,
\r
332 adcPosSelAPORT0XCH8 = _ADC_SINGLECTRL_POSSEL_APORT0XCH8,
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333 adcPosSelAPORT0XCH9 = _ADC_SINGLECTRL_POSSEL_APORT0XCH9,
\r
334 adcPosSelAPORT0XCH10 = _ADC_SINGLECTRL_POSSEL_APORT0XCH10,
\r
335 adcPosSelAPORT0XCH11 = _ADC_SINGLECTRL_POSSEL_APORT0XCH11,
\r
336 adcPosSelAPORT0XCH12 = _ADC_SINGLECTRL_POSSEL_APORT0XCH12,
\r
337 adcPosSelAPORT0XCH13 = _ADC_SINGLECTRL_POSSEL_APORT0XCH13,
\r
338 adcPosSelAPORT0XCH14 = _ADC_SINGLECTRL_POSSEL_APORT0XCH14,
\r
339 adcPosSelAPORT0XCH15 = _ADC_SINGLECTRL_POSSEL_APORT0XCH15,
\r
340 adcPosSelAPORT0YCH0 = _ADC_SINGLECTRL_POSSEL_APORT0YCH0,
\r
341 adcPosSelAPORT0YCH1 = _ADC_SINGLECTRL_POSSEL_APORT0YCH1,
\r
342 adcPosSelAPORT0YCH2 = _ADC_SINGLECTRL_POSSEL_APORT0YCH2,
\r
343 adcPosSelAPORT0YCH3 = _ADC_SINGLECTRL_POSSEL_APORT0YCH3,
\r
344 adcPosSelAPORT0YCH4 = _ADC_SINGLECTRL_POSSEL_APORT0YCH4,
\r
345 adcPosSelAPORT0YCH5 = _ADC_SINGLECTRL_POSSEL_APORT0YCH5,
\r
346 adcPosSelAPORT0YCH6 = _ADC_SINGLECTRL_POSSEL_APORT0YCH6,
\r
347 adcPosSelAPORT0YCH7 = _ADC_SINGLECTRL_POSSEL_APORT0YCH7,
\r
348 adcPosSelAPORT0YCH8 = _ADC_SINGLECTRL_POSSEL_APORT0YCH8,
\r
349 adcPosSelAPORT0YCH9 = _ADC_SINGLECTRL_POSSEL_APORT0YCH9,
\r
350 adcPosSelAPORT0YCH10 = _ADC_SINGLECTRL_POSSEL_APORT0YCH10,
\r
351 adcPosSelAPORT0YCH11 = _ADC_SINGLECTRL_POSSEL_APORT0YCH11,
\r
352 adcPosSelAPORT0YCH12 = _ADC_SINGLECTRL_POSSEL_APORT0YCH12,
\r
353 adcPosSelAPORT0YCH13 = _ADC_SINGLECTRL_POSSEL_APORT0YCH13,
\r
354 adcPosSelAPORT0YCH14 = _ADC_SINGLECTRL_POSSEL_APORT0YCH14,
\r
355 adcPosSelAPORT0YCH15 = _ADC_SINGLECTRL_POSSEL_APORT0YCH15,
\r
356 adcPosSelAPORT1XCH0 = _ADC_SINGLECTRL_POSSEL_APORT1XCH0,
\r
357 adcPosSelAPORT1YCH1 = _ADC_SINGLECTRL_POSSEL_APORT1YCH1,
\r
358 adcPosSelAPORT1XCH2 = _ADC_SINGLECTRL_POSSEL_APORT1XCH2,
\r
359 adcPosSelAPORT1YCH3 = _ADC_SINGLECTRL_POSSEL_APORT1YCH3,
\r
360 adcPosSelAPORT1XCH4 = _ADC_SINGLECTRL_POSSEL_APORT1XCH4,
\r
361 adcPosSelAPORT1YCH5 = _ADC_SINGLECTRL_POSSEL_APORT1YCH5,
\r
362 adcPosSelAPORT1XCH6 = _ADC_SINGLECTRL_POSSEL_APORT1XCH6,
\r
363 adcPosSelAPORT1YCH7 = _ADC_SINGLECTRL_POSSEL_APORT1YCH7,
\r
364 adcPosSelAPORT1XCH8 = _ADC_SINGLECTRL_POSSEL_APORT1XCH8,
\r
365 adcPosSelAPORT1YCH9 = _ADC_SINGLECTRL_POSSEL_APORT1YCH9,
\r
366 adcPosSelAPORT1XCH10 = _ADC_SINGLECTRL_POSSEL_APORT1XCH10,
\r
367 adcPosSelAPORT1YCH11 = _ADC_SINGLECTRL_POSSEL_APORT1YCH11,
\r
368 adcPosSelAPORT1XCH12 = _ADC_SINGLECTRL_POSSEL_APORT1XCH12,
\r
369 adcPosSelAPORT1YCH13 = _ADC_SINGLECTRL_POSSEL_APORT1YCH13,
\r
370 adcPosSelAPORT1XCH14 = _ADC_SINGLECTRL_POSSEL_APORT1XCH14,
\r
371 adcPosSelAPORT1YCH15 = _ADC_SINGLECTRL_POSSEL_APORT1YCH15,
\r
372 adcPosSelAPORT1XCH16 = _ADC_SINGLECTRL_POSSEL_APORT1XCH16,
\r
373 adcPosSelAPORT1YCH17 = _ADC_SINGLECTRL_POSSEL_APORT1YCH17,
\r
374 adcPosSelAPORT1XCH18 = _ADC_SINGLECTRL_POSSEL_APORT1XCH18,
\r
375 adcPosSelAPORT1YCH19 = _ADC_SINGLECTRL_POSSEL_APORT1YCH19,
\r
376 adcPosSelAPORT1XCH20 = _ADC_SINGLECTRL_POSSEL_APORT1XCH20,
\r
377 adcPosSelAPORT1YCH21 = _ADC_SINGLECTRL_POSSEL_APORT1YCH21,
\r
378 adcPosSelAPORT1XCH22 = _ADC_SINGLECTRL_POSSEL_APORT1XCH22,
\r
379 adcPosSelAPORT1YCH23 = _ADC_SINGLECTRL_POSSEL_APORT1YCH23,
\r
380 adcPosSelAPORT1XCH24 = _ADC_SINGLECTRL_POSSEL_APORT1XCH24,
\r
381 adcPosSelAPORT1YCH25 = _ADC_SINGLECTRL_POSSEL_APORT1YCH25,
\r
382 adcPosSelAPORT1XCH26 = _ADC_SINGLECTRL_POSSEL_APORT1XCH26,
\r
383 adcPosSelAPORT1YCH27 = _ADC_SINGLECTRL_POSSEL_APORT1YCH27,
\r
384 adcPosSelAPORT1XCH28 = _ADC_SINGLECTRL_POSSEL_APORT1XCH28,
\r
385 adcPosSelAPORT1YCH29 = _ADC_SINGLECTRL_POSSEL_APORT1YCH29,
\r
386 adcPosSelAPORT1XCH30 = _ADC_SINGLECTRL_POSSEL_APORT1XCH30,
\r
387 adcPosSelAPORT1YCH31 = _ADC_SINGLECTRL_POSSEL_APORT1YCH31,
\r
388 adcPosSelAPORT2YCH0 = _ADC_SINGLECTRL_POSSEL_APORT2YCH0,
\r
389 adcPosSelAPORT2XCH1 = _ADC_SINGLECTRL_POSSEL_APORT2XCH1,
\r
390 adcPosSelAPORT2YCH2 = _ADC_SINGLECTRL_POSSEL_APORT2YCH2,
\r
391 adcPosSelAPORT2XCH3 = _ADC_SINGLECTRL_POSSEL_APORT2XCH3,
\r
392 adcPosSelAPORT2YCH4 = _ADC_SINGLECTRL_POSSEL_APORT2YCH4,
\r
393 adcPosSelAPORT2XCH5 = _ADC_SINGLECTRL_POSSEL_APORT2XCH5,
\r
394 adcPosSelAPORT2YCH6 = _ADC_SINGLECTRL_POSSEL_APORT2YCH6,
\r
395 adcPosSelAPORT2XCH7 = _ADC_SINGLECTRL_POSSEL_APORT2XCH7,
\r
396 adcPosSelAPORT2YCH8 = _ADC_SINGLECTRL_POSSEL_APORT2YCH8,
\r
397 adcPosSelAPORT2XCH9 = _ADC_SINGLECTRL_POSSEL_APORT2XCH9,
\r
398 adcPosSelAPORT2YCH10 = _ADC_SINGLECTRL_POSSEL_APORT2YCH10,
\r
399 adcPosSelAPORT2XCH11 = _ADC_SINGLECTRL_POSSEL_APORT2XCH11,
\r
400 adcPosSelAPORT2YCH12 = _ADC_SINGLECTRL_POSSEL_APORT2YCH12,
\r
401 adcPosSelAPORT2XCH13 = _ADC_SINGLECTRL_POSSEL_APORT2XCH13,
\r
402 adcPosSelAPORT2YCH14 = _ADC_SINGLECTRL_POSSEL_APORT2YCH14,
\r
403 adcPosSelAPORT2XCH15 = _ADC_SINGLECTRL_POSSEL_APORT2XCH15,
\r
404 adcPosSelAPORT2YCH16 = _ADC_SINGLECTRL_POSSEL_APORT2YCH16,
\r
405 adcPosSelAPORT2XCH17 = _ADC_SINGLECTRL_POSSEL_APORT2XCH17,
\r
406 adcPosSelAPORT2YCH18 = _ADC_SINGLECTRL_POSSEL_APORT2YCH18,
\r
407 adcPosSelAPORT2XCH19 = _ADC_SINGLECTRL_POSSEL_APORT2XCH19,
\r
408 adcPosSelAPORT2YCH20 = _ADC_SINGLECTRL_POSSEL_APORT2YCH20,
\r
409 adcPosSelAPORT2XCH21 = _ADC_SINGLECTRL_POSSEL_APORT2XCH21,
\r
410 adcPosSelAPORT2YCH22 = _ADC_SINGLECTRL_POSSEL_APORT2YCH22,
\r
411 adcPosSelAPORT2XCH23 = _ADC_SINGLECTRL_POSSEL_APORT2XCH23,
\r
412 adcPosSelAPORT2YCH24 = _ADC_SINGLECTRL_POSSEL_APORT2YCH24,
\r
413 adcPosSelAPORT2XCH25 = _ADC_SINGLECTRL_POSSEL_APORT2XCH25,
\r
414 adcPosSelAPORT2YCH26 = _ADC_SINGLECTRL_POSSEL_APORT2YCH26,
\r
415 adcPosSelAPORT2XCH27 = _ADC_SINGLECTRL_POSSEL_APORT2XCH27,
\r
416 adcPosSelAPORT2YCH28 = _ADC_SINGLECTRL_POSSEL_APORT2YCH28,
\r
417 adcPosSelAPORT2XCH29 = _ADC_SINGLECTRL_POSSEL_APORT2XCH29,
\r
418 adcPosSelAPORT2YCH30 = _ADC_SINGLECTRL_POSSEL_APORT2YCH30,
\r
419 adcPosSelAPORT2XCH31 = _ADC_SINGLECTRL_POSSEL_APORT2XCH31,
\r
420 adcPosSelAPORT3XCH0 = _ADC_SINGLECTRL_POSSEL_APORT3XCH0,
\r
421 adcPosSelAPORT3YCH1 = _ADC_SINGLECTRL_POSSEL_APORT3YCH1,
\r
422 adcPosSelAPORT3XCH2 = _ADC_SINGLECTRL_POSSEL_APORT3XCH2,
\r
423 adcPosSelAPORT3YCH3 = _ADC_SINGLECTRL_POSSEL_APORT3YCH3,
\r
424 adcPosSelAPORT3XCH4 = _ADC_SINGLECTRL_POSSEL_APORT3XCH4,
\r
425 adcPosSelAPORT3YCH5 = _ADC_SINGLECTRL_POSSEL_APORT3YCH5,
\r
426 adcPosSelAPORT3XCH6 = _ADC_SINGLECTRL_POSSEL_APORT3XCH6,
\r
427 adcPosSelAPORT3YCH7 = _ADC_SINGLECTRL_POSSEL_APORT3YCH7,
\r
428 adcPosSelAPORT3XCH8 = _ADC_SINGLECTRL_POSSEL_APORT3XCH8,
\r
429 adcPosSelAPORT3YCH9 = _ADC_SINGLECTRL_POSSEL_APORT3YCH9,
\r
430 adcPosSelAPORT3XCH10 = _ADC_SINGLECTRL_POSSEL_APORT3XCH10,
\r
431 adcPosSelAPORT3YCH11 = _ADC_SINGLECTRL_POSSEL_APORT3YCH11,
\r
432 adcPosSelAPORT3XCH12 = _ADC_SINGLECTRL_POSSEL_APORT3XCH12,
\r
433 adcPosSelAPORT3YCH13 = _ADC_SINGLECTRL_POSSEL_APORT3YCH13,
\r
434 adcPosSelAPORT3XCH14 = _ADC_SINGLECTRL_POSSEL_APORT3XCH14,
\r
435 adcPosSelAPORT3YCH15 = _ADC_SINGLECTRL_POSSEL_APORT3YCH15,
\r
436 adcPosSelAPORT3XCH16 = _ADC_SINGLECTRL_POSSEL_APORT3XCH16,
\r
437 adcPosSelAPORT3YCH17 = _ADC_SINGLECTRL_POSSEL_APORT3YCH17,
\r
438 adcPosSelAPORT3XCH18 = _ADC_SINGLECTRL_POSSEL_APORT3XCH18,
\r
439 adcPosSelAPORT3YCH19 = _ADC_SINGLECTRL_POSSEL_APORT3YCH19,
\r
440 adcPosSelAPORT3XCH20 = _ADC_SINGLECTRL_POSSEL_APORT3XCH20,
\r
441 adcPosSelAPORT3YCH21 = _ADC_SINGLECTRL_POSSEL_APORT3YCH21,
\r
442 adcPosSelAPORT3XCH22 = _ADC_SINGLECTRL_POSSEL_APORT3XCH22,
\r
443 adcPosSelAPORT3YCH23 = _ADC_SINGLECTRL_POSSEL_APORT3YCH23,
\r
444 adcPosSelAPORT3XCH24 = _ADC_SINGLECTRL_POSSEL_APORT3XCH24,
\r
445 adcPosSelAPORT3YCH25 = _ADC_SINGLECTRL_POSSEL_APORT3YCH25,
\r
446 adcPosSelAPORT3XCH26 = _ADC_SINGLECTRL_POSSEL_APORT3XCH26,
\r
447 adcPosSelAPORT3YCH27 = _ADC_SINGLECTRL_POSSEL_APORT3YCH27,
\r
448 adcPosSelAPORT3XCH28 = _ADC_SINGLECTRL_POSSEL_APORT3XCH28,
\r
449 adcPosSelAPORT3YCH29 = _ADC_SINGLECTRL_POSSEL_APORT3YCH29,
\r
450 adcPosSelAPORT3XCH30 = _ADC_SINGLECTRL_POSSEL_APORT3XCH30,
\r
451 adcPosSelAPORT3YCH31 = _ADC_SINGLECTRL_POSSEL_APORT3YCH31,
\r
452 adcPosSelAPORT4YCH0 = _ADC_SINGLECTRL_POSSEL_APORT4YCH0,
\r
453 adcPosSelAPORT4XCH1 = _ADC_SINGLECTRL_POSSEL_APORT4XCH1,
\r
454 adcPosSelAPORT4YCH2 = _ADC_SINGLECTRL_POSSEL_APORT4YCH2,
\r
455 adcPosSelAPORT4XCH3 = _ADC_SINGLECTRL_POSSEL_APORT4XCH3,
\r
456 adcPosSelAPORT4YCH4 = _ADC_SINGLECTRL_POSSEL_APORT4YCH4,
\r
457 adcPosSelAPORT4XCH5 = _ADC_SINGLECTRL_POSSEL_APORT4XCH5,
\r
458 adcPosSelAPORT4YCH6 = _ADC_SINGLECTRL_POSSEL_APORT4YCH6,
\r
459 adcPosSelAPORT4XCH7 = _ADC_SINGLECTRL_POSSEL_APORT4XCH7,
\r
460 adcPosSelAPORT4YCH8 = _ADC_SINGLECTRL_POSSEL_APORT4YCH8,
\r
461 adcPosSelAPORT4XCH9 = _ADC_SINGLECTRL_POSSEL_APORT4XCH9,
\r
462 adcPosSelAPORT4YCH10 = _ADC_SINGLECTRL_POSSEL_APORT4YCH10,
\r
463 adcPosSelAPORT4XCH11 = _ADC_SINGLECTRL_POSSEL_APORT4XCH11,
\r
464 adcPosSelAPORT4YCH12 = _ADC_SINGLECTRL_POSSEL_APORT4YCH12,
\r
465 adcPosSelAPORT4XCH13 = _ADC_SINGLECTRL_POSSEL_APORT4XCH13,
\r
466 adcPosSelAPORT4YCH14 = _ADC_SINGLECTRL_POSSEL_APORT4YCH14,
\r
467 adcPosSelAPORT4XCH15 = _ADC_SINGLECTRL_POSSEL_APORT4XCH15,
\r
468 adcPosSelAPORT4YCH16 = _ADC_SINGLECTRL_POSSEL_APORT4YCH16,
\r
469 adcPosSelAPORT4XCH17 = _ADC_SINGLECTRL_POSSEL_APORT4XCH17,
\r
470 adcPosSelAPORT4YCH18 = _ADC_SINGLECTRL_POSSEL_APORT4YCH18,
\r
471 adcPosSelAPORT4XCH19 = _ADC_SINGLECTRL_POSSEL_APORT4XCH19,
\r
472 adcPosSelAPORT4YCH20 = _ADC_SINGLECTRL_POSSEL_APORT4YCH20,
\r
473 adcPosSelAPORT4XCH21 = _ADC_SINGLECTRL_POSSEL_APORT4XCH21,
\r
474 adcPosSelAPORT4YCH22 = _ADC_SINGLECTRL_POSSEL_APORT4YCH22,
\r
475 adcPosSelAPORT4XCH23 = _ADC_SINGLECTRL_POSSEL_APORT4XCH23,
\r
476 adcPosSelAPORT4YCH24 = _ADC_SINGLECTRL_POSSEL_APORT4YCH24,
\r
477 adcPosSelAPORT4XCH25 = _ADC_SINGLECTRL_POSSEL_APORT4XCH25,
\r
478 adcPosSelAPORT4YCH26 = _ADC_SINGLECTRL_POSSEL_APORT4YCH26,
\r
479 adcPosSelAPORT4XCH27 = _ADC_SINGLECTRL_POSSEL_APORT4XCH27,
\r
480 adcPosSelAPORT4YCH28 = _ADC_SINGLECTRL_POSSEL_APORT4YCH28,
\r
481 adcPosSelAPORT4XCH29 = _ADC_SINGLECTRL_POSSEL_APORT4XCH29,
\r
482 adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,
\r
483 adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,
\r
484 adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD,
\r
485 adcPosSelBU = _ADC_SINGLECTRL_POSSEL_BU,
\r
486 adcPosSelAREG = _ADC_SINGLECTRL_POSSEL_AREG,
\r
487 adcPosSelVREGOUTPA = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,
\r
488 adcPosSelPDBU = _ADC_SINGLECTRL_POSSEL_PDBU,
\r
489 adcPosSelIO0 = _ADC_SINGLECTRL_POSSEL_IO0,
\r
490 adcPosSelIO1 = _ADC_SINGLECTRL_POSSEL_IO1,
\r
491 adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP,
\r
492 adcPosSelSP0 = _ADC_SINGLECTRL_POSSEL_SP0,
\r
493 adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP,
\r
494 adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0,
\r
495 adcPosSelTESTP = _ADC_SINGLECTRL_POSSEL_TESTP,
\r
496 adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1,
\r
497 adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2,
\r
498 adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1,
\r
499 adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB,
\r
500 adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT,
\r
501 adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS
\r
502 } ADC_PosSel_TypeDef;
\r
506 #if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
\r
507 /** Negative input selection for single and scan coversion. */
\r
510 adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,
\r
511 adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,
\r
512 adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,
\r
513 adcNegSelAPORT0XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH3,
\r
514 adcNegSelAPORT0XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH4,
\r
515 adcNegSelAPORT0XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH5,
\r
516 adcNegSelAPORT0XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH6,
\r
517 adcNegSelAPORT0XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH7,
\r
518 adcNegSelAPORT0XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH8,
\r
519 adcNegSelAPORT0XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH9,
\r
520 adcNegSelAPORT0XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH10,
\r
521 adcNegSelAPORT0XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH11,
\r
522 adcNegSelAPORT0XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH12,
\r
523 adcNegSelAPORT0XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH13,
\r
524 adcNegSelAPORT0XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH14,
\r
525 adcNegSelAPORT0XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH15,
\r
526 adcNegSelAPORT0YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH0,
\r
527 adcNegSelAPORT0YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH1,
\r
528 adcNegSelAPORT0YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH2,
\r
529 adcNegSelAPORT0YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH3,
\r
530 adcNegSelAPORT0YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH4,
\r
531 adcNegSelAPORT0YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH5,
\r
532 adcNegSelAPORT0YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH6,
\r
533 adcNegSelAPORT0YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH7,
\r
534 adcNegSelAPORT0YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH8,
\r
535 adcNegSelAPORT0YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH9,
\r
536 adcNegSelAPORT0YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH10,
\r
537 adcNegSelAPORT0YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH11,
\r
538 adcNegSelAPORT0YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH12,
\r
539 adcNegSelAPORT0YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH13,
\r
540 adcNegSelAPORT0YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH14,
\r
541 adcNegSelAPORT0YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH15,
\r
542 adcNegSelAPORT1XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH0,
\r
543 adcNegSelAPORT1YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH1,
\r
544 adcNegSelAPORT1XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH2,
\r
545 adcNegSelAPORT1YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH3,
\r
546 adcNegSelAPORT1XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH4,
\r
547 adcNegSelAPORT1YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH5,
\r
548 adcNegSelAPORT1XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH6,
\r
549 adcNegSelAPORT1YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH7,
\r
550 adcNegSelAPORT1XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH8,
\r
551 adcNegSelAPORT1YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH9,
\r
552 adcNegSelAPORT1XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH10,
\r
553 adcNegSelAPORT1YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH11,
\r
554 adcNegSelAPORT1XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH12,
\r
555 adcNegSelAPORT1YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH13,
\r
556 adcNegSelAPORT1XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH14,
\r
557 adcNegSelAPORT1YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH15,
\r
558 adcNegSelAPORT1XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH16,
\r
559 adcNegSelAPORT1YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH17,
\r
560 adcNegSelAPORT1XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH18,
\r
561 adcNegSelAPORT1YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH19,
\r
562 adcNegSelAPORT1XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH20,
\r
563 adcNegSelAPORT1YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH21,
\r
564 adcNegSelAPORT1XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH22,
\r
565 adcNegSelAPORT1YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH23,
\r
566 adcNegSelAPORT1XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH24,
\r
567 adcNegSelAPORT1YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH25,
\r
568 adcNegSelAPORT1XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH26,
\r
569 adcNegSelAPORT1YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH27,
\r
570 adcNegSelAPORT1XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH28,
\r
571 adcNegSelAPORT1YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH29,
\r
572 adcNegSelAPORT1XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH30,
\r
573 adcNegSelAPORT1YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH31,
\r
574 adcNegSelAPORT2YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH0,
\r
575 adcNegSelAPORT2XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH1,
\r
576 adcNegSelAPORT2YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH2,
\r
577 adcNegSelAPORT2XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH3,
\r
578 adcNegSelAPORT2YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH4,
\r
579 adcNegSelAPORT2XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH5,
\r
580 adcNegSelAPORT2YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH6,
\r
581 adcNegSelAPORT2XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH7,
\r
582 adcNegSelAPORT2YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH8,
\r
583 adcNegSelAPORT2XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH9,
\r
584 adcNegSelAPORT2YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH10,
\r
585 adcNegSelAPORT2XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH11,
\r
586 adcNegSelAPORT2YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH12,
\r
587 adcNegSelAPORT2XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH13,
\r
588 adcNegSelAPORT2YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH14,
\r
589 adcNegSelAPORT2XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH15,
\r
590 adcNegSelAPORT2YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH16,
\r
591 adcNegSelAPORT2XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH17,
\r
592 adcNegSelAPORT2YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH18,
\r
593 adcNegSelAPORT2XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH19,
\r
594 adcNegSelAPORT2YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH20,
\r
595 adcNegSelAPORT2XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH21,
\r
596 adcNegSelAPORT2YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH22,
\r
597 adcNegSelAPORT2XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH23,
\r
598 adcNegSelAPORT2YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH24,
\r
599 adcNegSelAPORT2XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH25,
\r
600 adcNegSelAPORT2YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH26,
\r
601 adcNegSelAPORT2XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH27,
\r
602 adcNegSelAPORT2YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH28,
\r
603 adcNegSelAPORT2XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH29,
\r
604 adcNegSelAPORT2YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH30,
\r
605 adcNegSelAPORT2XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH31,
\r
606 adcNegSelAPORT3XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH0,
\r
607 adcNegSelAPORT3YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH1,
\r
608 adcNegSelAPORT3XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH2,
\r
609 adcNegSelAPORT3YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH3,
\r
610 adcNegSelAPORT3XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH4,
\r
611 adcNegSelAPORT3YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH5,
\r
612 adcNegSelAPORT3XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH6,
\r
613 adcNegSelAPORT3YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH7,
\r
614 adcNegSelAPORT3XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH8,
\r
615 adcNegSelAPORT3YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH9,
\r
616 adcNegSelAPORT3XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH10,
\r
617 adcNegSelAPORT3YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH11,
\r
618 adcNegSelAPORT3XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH12,
\r
619 adcNegSelAPORT3YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH13,
\r
620 adcNegSelAPORT3XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH14,
\r
621 adcNegSelAPORT3YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH15,
\r
622 adcNegSelAPORT3XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH16,
\r
623 adcNegSelAPORT3YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH17,
\r
624 adcNegSelAPORT3XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH18,
\r
625 adcNegSelAPORT3YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH19,
\r
626 adcNegSelAPORT3XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH20,
\r
627 adcNegSelAPORT3YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH21,
\r
628 adcNegSelAPORT3XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH22,
\r
629 adcNegSelAPORT3YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH23,
\r
630 adcNegSelAPORT3XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH24,
\r
631 adcNegSelAPORT3YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH25,
\r
632 adcNegSelAPORT3XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH26,
\r
633 adcNegSelAPORT3YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH27,
\r
634 adcNegSelAPORT3XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH28,
\r
635 adcNegSelAPORT3YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH29,
\r
636 adcNegSelAPORT3XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH30,
\r
637 adcNegSelAPORT3YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH31,
\r
638 adcNegSelAPORT4YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH0,
\r
639 adcNegSelAPORT4XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH1,
\r
640 adcNegSelAPORT4YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH2,
\r
641 adcNegSelAPORT4XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH3,
\r
642 adcNegSelAPORT4YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH4,
\r
643 adcNegSelAPORT4XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH5,
\r
644 adcNegSelAPORT4YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH6,
\r
645 adcNegSelAPORT4XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH7,
\r
646 adcNegSelAPORT4YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH8,
\r
647 adcNegSelAPORT4XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH9,
\r
648 adcNegSelAPORT4YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH10,
\r
649 adcNegSelAPORT4XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH11,
\r
650 adcNegSelAPORT4YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH12,
\r
651 adcNegSelAPORT4XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH13,
\r
652 adcNegSelAPORT4YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH14,
\r
653 adcNegSelAPORT4XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH15,
\r
654 adcNegSelAPORT4YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH16,
\r
655 adcNegSelAPORT4XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH17,
\r
656 adcNegSelAPORT4YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH18,
\r
657 adcNegSelAPORT4XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH19,
\r
658 adcNegSelAPORT4YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH20,
\r
659 adcNegSelAPORT4XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH21,
\r
660 adcNegSelAPORT4YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH22,
\r
661 adcNegSelAPORT4XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH23,
\r
662 adcNegSelAPORT4YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH24,
\r
663 adcNegSelAPORT4XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH25,
\r
664 adcNegSelAPORT4YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH26,
\r
665 adcNegSelAPORT4XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH27,
\r
666 adcNegSelAPORT4YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH28,
\r
667 adcNegSelAPORT4XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH29,
\r
668 adcNegSelAPORT4YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH30,
\r
669 adcNegSelAPORT4XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH31,
\r
670 adcNegSelTESTN = _ADC_SINGLECTRL_NEGSEL_TESTN,
\r
671 adcNegSelDEFAULT = _ADC_SINGLECTRL_NEGSEL_DEFAULT,
\r
672 adcNegSelVSS = _ADC_SINGLECTRL_NEGSEL_VSS
\r
673 } ADC_NegSel_TypeDef;
\r
677 #if defined( _ADC_SCANINPUTSEL_MASK )
\r
678 /* ADC scan input groups */
\r
681 adcScanInputGroup0 = 0,
\r
682 adcScanInputGroup1 = 1,
\r
683 adcScanInputGroup2 = 2,
\r
684 adcScanInputGroup3 = 3,
\r
685 } ADC_ScanInputGroup_TypeDef;
\r
687 /* ADC scan alternative negative inputs */
\r
690 adcScanNegInput1 = 1,
\r
691 adcScanNegInput3 = 3,
\r
692 adcScanNegInput5 = 5,
\r
693 adcScanNegInput7 = 7,
\r
694 adcScanNegInput8 = 8,
\r
695 adcScanNegInput10 = 10,
\r
696 adcScanNegInput12 = 12,
\r
697 adcScanNegInput14 = 14,
\r
698 adcScanNegInputDefault = 0xFF,
\r
699 } ADC_ScanNegInput_TypeDef;
\r
703 /** ADC Start command. */
\r
706 /** Start single conversion. */
\r
707 adcStartSingle = ADC_CMD_SINGLESTART,
\r
709 /** Start scan sequence. */
\r
710 adcStartScan = ADC_CMD_SCANSTART,
\r
713 * Start scan sequence and single conversion, typically used when tailgating
\r
714 * single conversion after scan sequence.
\r
716 adcStartScanAndSingle = ADC_CMD_SCANSTART | ADC_CMD_SINGLESTART
\r
717 } ADC_Start_TypeDef;
\r
720 /** Warm-up mode. */
\r
723 /** ADC shutdown after each conversion. */
\r
724 adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL,
\r
726 #if defined( _ADC_CTRL_WARMUPMODE_FASTBG )
\r
727 /** Do not warm-up bandgap references. */
\r
728 adcWarmupFastBG = _ADC_CTRL_WARMUPMODE_FASTBG,
\r
731 #if defined( _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM )
\r
732 /** Reference selected for scan mode kept warm.*/
\r
733 adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM,
\r
736 #if defined( _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY )
\r
737 /** ADC is kept in standby mode between conversion. 1us warmup time needed
\r
738 before next conversion. */
\r
739 adcWarmupKeepInStandby = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY,
\r
742 #if defined( _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC )
\r
743 /** ADC is kept in slow acquisition mode between conversions. 1us warmup
\r
744 time needed before next conversion. */
\r
745 adcWarmupKeepInSlowAcq = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC,
\r
748 /** ADC and reference selected for scan mode kept warmup, allowing
\r
749 continuous conversion. */
\r
750 adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,
\r
752 } ADC_Warmup_TypeDef;
\r
755 #if defined( _ADC_CTRL_ADCCLKMODE_MASK )
\r
756 /** ADC EM2 clock configuration */
\r
759 adcEm2Disabled = 0,
\r
760 adcEm2ClockOnDemand = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ASNEEDED,
\r
761 adcEm2ClockAlwaysOn = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ALWAYSON,
\r
762 } ADC_EM2ClockConfig_TypeDef;
\r
766 /*******************************************************************************
\r
767 ******************************* STRUCTS ***********************************
\r
768 ******************************************************************************/
\r
770 /** ADC init structure, common for single conversion and scan sequence. */
\r
774 * Oversampling rate select. In order to have any effect, oversampling must
\r
775 * be enabled for single/scan mode.
\r
777 ADC_OvsRateSel_TypeDef ovsRateSel;
\r
779 #if defined( _ADC_CTRL_LPFMODE_MASK )
\r
780 /** Lowpass or decoupling capacitor filter to use. */
\r
781 ADC_LPFilter_TypeDef lpfMode;
\r
784 /** Warm-up mode to use for ADC. */
\r
785 ADC_Warmup_TypeDef warmUpMode;
\r
788 * Timebase used for ADC warm up. Select N to give (N+1)HFPERCLK cycles.
\r
789 * (Additional delay is added for bandgap references, please refer to the
\r
790 * reference manual.) Normally, N should be selected so that the timebase
\r
791 * is at least 1 us. See ADC_TimebaseCalc() for a way to obtain
\r
792 * a suggested timebase of at least 1 us.
\r
796 /** Clock division factor N, ADC clock = HFPERCLK / (N + 1). */
\r
799 /** Enable/disable conversion tailgating. */
\r
802 /** ADC EM2 clock configuration */
\r
803 #if defined( _ADC_CTRL_ADCCLKMODE_MASK )
\r
804 ADC_EM2ClockConfig_TypeDef em2ClockConfig;
\r
806 } ADC_Init_TypeDef;
\r
809 /** Default config for ADC init structure. */
\r
810 #if defined( _ADC_CTRL_LPFMODE_MASK ) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
\r
811 #define ADC_INIT_DEFAULT \
\r
813 adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
\r
814 adcLPFilterBypass, /* No input filter selected. */ \
\r
815 adcWarmupNormal, /* ADC shutdown after each conversion. */ \
\r
816 _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
\r
817 _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
\r
818 false /* Do not use tailgate. */ \
\r
820 #elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
\r
821 #define ADC_INIT_DEFAULT \
\r
823 adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
\r
824 adcWarmupNormal, /* ADC shutdown after each conversion. */ \
\r
825 _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
\r
826 _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
\r
827 false /* Do not use tailgate. */ \
\r
829 #elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && defined( _ADC_CTRL_ADCCLKMODE_MASK )
\r
830 #define ADC_INIT_DEFAULT \
\r
832 adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
\r
833 adcWarmupNormal, /* ADC shutdown after each conversion. */ \
\r
834 _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
\r
835 _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
\r
836 false, /* Do not use tailgate. */ \
\r
837 adcEm2Disabled /* ADC disabled in EM2 */ \
\r
842 /** Scan input configuration */
\r
845 /** Input range select to be applied to ADC_SCANCHCONF. */
\r
846 int32_t scanInputSel;
\r
848 /** Input enable mask */
\r
849 uint32_t scanInputEn;
\r
851 /** Alternative negative input */
\r
852 uint32_t scanNegSel;
\r
853 } ADC_InitScanInput_TypeDef;
\r
856 /** Scan sequence init structure. */
\r
860 * Peripheral reflex system trigger selection. Only applicable if @p prsEnable
\r
863 ADC_PRSSEL_TypeDef prsSel;
\r
865 /** Acquisition time (in ADC clock cycles). */
\r
866 ADC_AcqTime_TypeDef acqTime;
\r
869 * Sample reference selection. Notice that for external references, the
\r
870 * ADC calibration register must be set explicitly.
\r
872 ADC_Ref_TypeDef reference;
\r
874 /** Sample resolution. */
\r
875 ADC_Res_TypeDef resolution;
\r
877 #if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
\r
879 * Scan input selection. If single ended (@p diff is false), use logical
\r
880 * combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input
\r
881 * (@p diff is true), use logical combination of ADC_SCANCTRL_INPUTMASK_CHxCHy
\r
882 * defines. (Notice underscore prefix for defines used.)
\r
887 #if defined( _ADC_SCANINPUTSEL_MASK )
\r
889 * Scan input configuration. Use ADC_ScanSingleEndedInit() or ADC_ScanDifferentialInit()
\r
890 * to write this struct. Note that the diff variable is included in ADC_InitScanInput_TypeDef.
\r
892 ADC_InitScanInput_TypeDef scanInputConfig;
\r
895 /** Select if single ended or differential input. */
\r
898 /** Peripheral reflex system trigger enable. */
\r
901 /** Select if left adjustment should be done. */
\r
904 /** Select if continuous conversion until explicit stop. */
\r
907 /** When true, DMA is available in EM2 for scan conversion */
\r
908 #if defined( _ADC_CTRL_SCANDMAWU_MASK )
\r
912 #if defined( _ADC_SCANCTRLX_FIFOOFACT_MASK )
\r
913 /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
\r
914 The SINGLEOF IRQ is triggered in both cases. */
\r
915 bool fifoOverwrite;
\r
917 } ADC_InitScan_TypeDef;
\r
919 /** Default config for ADC scan init structure. */
\r
920 #if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
\r
921 #define ADC_INITSCAN_DEFAULT \
\r
923 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
\r
924 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
\r
925 adcRef1V25, /* 1.25V internal reference. */ \
\r
926 adcRes12Bit, /* 12 bit resolution. */ \
\r
927 0, /* No input selected. */ \
\r
928 false, /* Single-ended input. */ \
\r
929 false, /* PRS disabled. */ \
\r
930 false, /* Right adjust. */ \
\r
931 false, /* Deactivate conversion after one scan sequence. */ \
\r
935 #if defined( _ADC_SCANINPUTSEL_MASK )
\r
936 #define ADC_INITSCAN_DEFAULT \
\r
938 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
\r
939 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
\r
940 adcRef1V25, /* 1.25V internal reference. */ \
\r
941 adcRes12Bit, /* 12 bit resolution. */ \
\r
942 0, /* Default ADC inputs */ \
\r
943 0, /* Default input mask (all off) */ \
\r
944 _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */ \
\r
945 false, /* Single-ended input. */ \
\r
946 false, /* PRS disabled. */ \
\r
947 false, /* Right adjust. */ \
\r
948 false, /* Deactivate conversion after one scan sequence. */ \
\r
949 false, /* No EM2 DMA wakeup from scan FIFO DVL */ \
\r
950 false /* Discard new data on full FIFO. */ \
\r
955 /** Single conversion init structure. */
\r
959 * Peripheral reflex system trigger selection. Only applicable if @p prsEnable
\r
962 ADC_PRSSEL_TypeDef prsSel;
\r
964 /** Acquisition time (in ADC clock cycles). */
\r
965 ADC_AcqTime_TypeDef acqTime;
\r
968 * Sample reference selection. Notice that for external references, the
\r
969 * ADC calibration register must be set explicitly.
\r
971 ADC_Ref_TypeDef reference;
\r
973 /** Sample resolution. */
\r
974 ADC_Res_TypeDef resolution;
\r
976 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
\r
978 * Sample input selection, use single ended or differential input according
\r
979 * to setting of @p diff.
\r
981 ADC_SingleInput_TypeDef input;
\r
984 #if defined( _ADC_SINGLECTRL_POSSEL_MASK )
\r
985 /** Select positive input for for single channel conversion mode. */
\r
986 ADC_PosSel_TypeDef posSel;
\r
989 #if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
\r
990 /** Select negative input for single channel conversion mode. Negative input is grounded
\r
991 for single ended (non-differential) converison. */
\r
992 ADC_NegSel_TypeDef negSel;
\r
995 /** Select if single ended or differential input. */
\r
998 /** Peripheral reflex system trigger enable. */
\r
1001 /** Select if left adjustment should be done. */
\r
1004 /** Select if continuous conversion until explicit stop. */
\r
1007 #if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
\r
1008 /** When true, DMA is available in EM2 for single conversion */
\r
1009 bool singleDmaEm2Wu;
\r
1012 #if defined( _ADC_SINGLECTRLX_FIFOOFACT_MASK )
\r
1013 /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
\r
1014 The SCANOF IRQ is triggered in both cases. */
\r
1015 bool fifoOverwrite;
\r
1017 } ADC_InitSingle_TypeDef;
\r
1019 /** Default config for ADC single conversion init structure. */
\r
1020 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
\r
1021 #define ADC_INITSINGLE_DEFAULT \
\r
1023 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
\r
1024 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
\r
1025 adcRef1V25, /* 1.25V internal reference. */ \
\r
1026 adcRes12Bit, /* 12 bit resolution. */ \
\r
1027 adcSingleInpCh0, /* CH0 input selected. */ \
\r
1028 false, /* Single ended input. */ \
\r
1029 false, /* PRS disabled. */ \
\r
1030 false, /* Right adjust. */ \
\r
1031 false /* Deactivate conversion after one scan sequence. */ \
\r
1034 #define ADC_INITSINGLE_DEFAULT \
\r
1036 adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
\r
1037 adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
\r
1038 adcRef1V25, /* 1.25V internal reference. */ \
\r
1039 adcRes12Bit, /* 12 bit resolution. */ \
\r
1040 adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \
\r
1041 adcNegSelAPORT0XCH1, /* Select node BUS0XCH1 as negSel */ \
\r
1042 false, /* Single ended input. */ \
\r
1043 false, /* PRS disabled. */ \
\r
1044 false, /* Right adjust. */ \
\r
1045 false, /* Deactivate conversion after one scan sequence. */ \
\r
1046 false, /* No EM2 DMA wakeup from single FIFO DVL */ \
\r
1047 false /* Discard new data on full FIFO. */ \
\r
1051 /*******************************************************************************
\r
1052 ***************************** PROTOTYPES **********************************
\r
1053 ******************************************************************************/
\r
1055 /***************************************************************************//**
\r
1057 * Get single conversion result.
\r
1060 * Check data valid flag before calling this function.
\r
1063 * Pointer to ADC peripheral register block.
\r
1066 * Single conversion data.
\r
1067 ******************************************************************************/
\r
1068 __STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc)
\r
1070 return adc->SINGLEDATA;
\r
1074 /***************************************************************************//**
\r
1076 * Peek single conversion result.
\r
1079 * Check data valid flag before calling this function.
\r
1082 * Pointer to ADC peripheral register block.
\r
1085 * Single conversion data.
\r
1086 ******************************************************************************/
\r
1087 __STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc)
\r
1089 return adc->SINGLEDATAP;
\r
1093 /***************************************************************************//**
\r
1095 * Get scan result.
\r
1098 * Check data valid flag before calling this function.
\r
1101 * Pointer to ADC peripheral register block.
\r
1104 * Scan conversion data.
\r
1105 ******************************************************************************/
\r
1106 __STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc)
\r
1108 return adc->SCANDATA;
\r
1112 /***************************************************************************//**
\r
1114 * Peek scan result.
\r
1117 * Check data valid flag before calling this function.
\r
1120 * Pointer to ADC peripheral register block.
\r
1123 * Scan conversion data.
\r
1124 ******************************************************************************/
\r
1125 __STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc)
\r
1127 return adc->SCANDATAP;
\r
1131 #if defined( _ADC_SCANDATAX_MASK )
\r
1132 uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);
\r
1135 void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init);
\r
1136 void ADC_Reset(ADC_TypeDef *adc);
\r
1137 void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init);
\r
1139 #if defined( _ADC_SCANINPUTSEL_MASK )
\r
1140 void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit);
\r
1141 uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
\r
1142 ADC_ScanInputGroup_TypeDef inputGroup,
\r
1143 ADC_PosSel_TypeDef singleEndedSel);
\r
1144 uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,
\r
1145 ADC_ScanInputGroup_TypeDef inputGroup,
\r
1146 ADC_PosSel_TypeDef posSel,
\r
1147 ADC_ScanNegInput_TypeDef adcScanNegInput);
\r
1150 void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);
\r
1151 uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
\r
1152 uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
\r
1155 /***************************************************************************//**
\r
1157 * Clear one or more pending ADC interrupts.
\r
1160 * Pointer to ADC peripheral register block.
\r
1162 * @param[in] flags
\r
1163 * Pending ADC interrupt source to clear. Use a bitwise logic OR combination
\r
1164 * of valid interrupt flags for the ADC module (ADC_IF_nnn).
\r
1165 ******************************************************************************/
\r
1166 __STATIC_INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
\r
1172 /***************************************************************************//**
\r
1174 * Disable one or more ADC interrupts.
\r
1177 * Pointer to ADC peripheral register block.
\r
1179 * @param[in] flags
\r
1180 * ADC interrupt sources to disable. Use a bitwise logic OR combination of
\r
1181 * valid interrupt flags for the ADC module (ADC_IF_nnn).
\r
1182 ******************************************************************************/
\r
1183 __STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
\r
1185 adc->IEN &= ~flags;
\r
1189 /***************************************************************************//**
\r
1191 * Enable one or more ADC interrupts.
\r
1194 * Depending on the use, a pending interrupt may already be set prior to
\r
1195 * enabling the interrupt. Consider using ADC_IntClear() prior to enabling
\r
1196 * if such a pending interrupt should be ignored.
\r
1199 * Pointer to ADC peripheral register block.
\r
1201 * @param[in] flags
\r
1202 * ADC interrupt sources to enable. Use a bitwise logic OR combination of
\r
1203 * valid interrupt flags for the ADC module (ADC_IF_nnn).
\r
1204 ******************************************************************************/
\r
1205 __STATIC_INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags)
\r
1207 adc->IEN |= flags;
\r
1211 /***************************************************************************//**
\r
1213 * Get pending ADC interrupt flags.
\r
1216 * The event bits are not cleared by the use of this function.
\r
1219 * Pointer to ADC peripheral register block.
\r
1222 * ADC interrupt sources pending. A bitwise logic OR combination of valid
\r
1223 * interrupt flags for the ADC module (ADC_IF_nnn).
\r
1224 ******************************************************************************/
\r
1225 __STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
\r
1231 /***************************************************************************//**
\r
1233 * Get enabled and pending ADC interrupt flags.
\r
1234 * Useful for handling more interrupt sources in the same interrupt handler.
\r
1237 * Pointer to ADC peripheral register block.
\r
1240 * Interrupt flags are not cleared by the use of this function.
\r
1243 * Pending and enabled ADC interrupt sources.
\r
1244 * The return value is the bitwise AND combination of
\r
1245 * - the OR combination of enabled interrupt sources in ADCx_IEN_nnn
\r
1246 * register (ADCx_IEN_nnn) and
\r
1247 * - the OR combination of valid interrupt flags of the ADC module
\r
1249 ******************************************************************************/
\r
1250 __STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc)
\r
1254 /* Store ADCx->IEN in temporary variable in order to define explicit order
\r
1255 * of volatile accesses. */
\r
1258 /* Bitwise AND of pending and enabled interrupts */
\r
1259 return adc->IF & ien;
\r
1263 /***************************************************************************//**
\r
1265 * Set one or more pending ADC interrupts from SW.
\r
1268 * Pointer to ADC peripheral register block.
\r
1270 * @param[in] flags
\r
1271 * ADC interrupt sources to set to pending. Use a bitwise logic OR combination
\r
1272 * of valid interrupt flags for the ADC module (ADC_IF_nnn).
\r
1273 ******************************************************************************/
\r
1274 __STATIC_INLINE void ADC_IntSet(ADC_TypeDef *adc, uint32_t flags)
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1280 /***************************************************************************//**
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1282 * Start scan sequence and/or single conversion.
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1285 * Pointer to ADC peripheral register block.
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1288 * Command indicating which type of sampling to start.
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1289 ******************************************************************************/
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1290 __STATIC_INLINE void ADC_Start(ADC_TypeDef *adc, ADC_Start_TypeDef cmd)
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1292 adc->CMD = (uint32_t)cmd;
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1296 /** @} (end addtogroup ADC) */
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1297 /** @} (end addtogroup EM_Library) */
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1299 #ifdef __cplusplus
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1303 #endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
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1304 #endif /* __SILICON_LABS_EM_ADC_H__ */
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