1 /**********************************************************************
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2 * $Id$ lpc18xx_can.c 2011-06-02
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4 * @file lpc18xx_can.c
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5 * @brief Contains all functions support for C CAN firmware library
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8 * @date 02. June. 2011
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9 * @author NXP MCU SW Application Team
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11 * Copyright(C) 2011, NXP Semiconductor
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12 * All rights reserved.
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14 ***********************************************************************
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15 * Software that is described herein is for illustrative purposes only
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16 * which provides customers with programming information regarding the
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17 * products. This software is supplied "AS IS" without any warranties.
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18 * NXP Semiconductors assumes no responsibility or liability for the
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19 * use of the software, conveys no license or title under any patent,
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20 * copyright, or mask work right to the product. NXP Semiconductors
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21 * reserves the right to make changes in the software without
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22 * notification. NXP Semiconductors also make no representation or
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23 * warranty that such application will be suitable for the specified
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24 * use without further testing or modification.
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25 **********************************************************************/
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27 /* Peripheral group ----------------------------------------------------------- */
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28 /** @addtogroup C_CAN
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32 /* Includes ------------------------------------------------------------------- */
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33 #include "LPC18xx.h"
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34 #include "lpc18xx_can.h"
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35 #include "lpc18xx_cgu.h"
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37 /* If this source file built with example, the LPC18xx FW library configuration
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38 * file in each example directory ("lpc18xx_libcfg.h") must be included,
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39 * otherwise the default FW library configuration file must be included instead
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41 #ifdef __BUILD_WITH_EXAMPLE__
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42 #include "lpc18xx_libcfg.h"
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44 #include "lpc18xx_libcfg_default.h"
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45 #endif /* __BUILD_WITH_EXAMPLE__ */
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49 /* Private Macros ---------------------------------------------------------- */
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51 /* Macro for reading and writing to CCAN IF registers */
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52 #define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->##IFsel##_##reg)
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53 #define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->##IFsel##_##reg=val)
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55 /* Macro for writing IF to specific RAM message object */
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56 #define CAN_IF_readBuf(IFsel,msg) \
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57 LPC_C_CAN0->##IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
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58 LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \
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59 while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY );
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61 /* Macro for reading specific RAM message object to IF */
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62 #define CAN_IF_writeBuf(IFsel,msg) \
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63 LPC_C_CAN0->##IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
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64 LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \
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65 while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY );
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67 #define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->IFsel##_##reg)
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68 #define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->IFsel ## _ ## reg = val)
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70 /* Macro for writing IF to specific RAM message object */
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71 #define CAN_IF_readBuf(IFsel,msg) \
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72 LPC_C_CAN0->IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
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73 LPC_C_CAN0->IFsel##_##CMDREQ=msg; \
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74 while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY );
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76 /* Macro for reading specific RAM message object to IF */
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77 #define CAN_IF_writeBuf(IFsel,msg) \
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78 LPC_C_CAN0->IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
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79 LPC_C_CAN0->IFsel##_##CMDREQ=msg; \
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80 while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY );
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86 #define CAN_STATUS_INTERRUPT 0x8000 /* 0x0001-0x0020 are the # of the message
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88 /* 0x8000 is the status interrupt */
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90 /* CAN Message interface register definitions */
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91 /* bit field of IF command request n register */
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92 #define IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when
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94 /* CAN CTRL register */
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95 #define CTRL_INIT (1 << 0)
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96 #define CTRL_IE (1 << 1)
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97 #define CTRL_SIE (1 << 2)
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98 #define CTRL_EIE (1 << 3)
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99 #define CTRL_DAR (1 << 5)
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100 #define CTRL_CCE (1 << 6)
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101 #define CTRL_TEST (1 << 7)
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103 /* CAN Test register */
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104 #define TEST_BASIC (1 << 2)
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105 #define TEST_SILENT (1 << 3)
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106 #define TEST_LBACK (1 << 4)
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108 /* CAN Status register */
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109 #define STAT_LEC (0x7 << 0)
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110 #define STAT_TXOK (1 << 3)
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111 #define STAT_RXOK (1 << 4)
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112 #define STAT_EPASS (1 << 5)
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113 #define STAT_EWARN (1 << 6)
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114 #define STAT_BOFF (1 << 7)
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116 #define NO_ERR 0 // No Error
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117 #define STUFF_ERR 1 // Stuff Error : More than 5 equal bits in a sequence have occurred in a part
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118 // of a received message where this is not allowed.
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119 #define FORM_ERR 2 // Form Error : A fixed format part of a received frame has the wrong format.
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120 #define ACK_ERR 3 // AckError : The message this CAN Core transmitted was not acknowledged
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121 // by another node.
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122 #define BIT1_ERR 4 // Bit1Error : During the transmission of a message (with the exception of
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123 // the arbitration field), the device wanted to send a recessive level (bit of
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124 // logical value �1�), but the monitored bus value was dominant.
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125 #define BIT0_ERR 5 // Bit0Error : During the transmission of a message (or acknowledge bit,
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126 // or active error flag, or overload flag), the device wanted to send a
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127 // LOW/dominant level (data or identifier bit logical value �0�), but the
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128 // monitored Bus value was HIGH/recessive. During busoff recovery this
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129 // status is set each time a
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130 // sequence of 11 HIGH/recessive bits has been monitored. This enables
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131 // the CPU to monitor the proceeding of the busoff recovery sequence
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132 // (indicating the bus is not stuck at LOW/dominant or continuously
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134 #define CRC_ERR 6 // CRCError: The CRC checksum was incorrect in the message received.
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137 /* bit field of IF command mask register */
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138 #define DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */
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139 #define DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */
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140 #define NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */
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141 #define CLRINTPND (1 << 3)
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142 #define CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */
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143 #define ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */
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144 #define MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */
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145 #define WR (1 << 7) /* 0 is READ, 1 is WRITE */
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148 /* bit field of IF mask 2 register */
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149 #define MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
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150 #define MASK_MDIR (1 << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */
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152 /* bit field of IF identifier 2 register */
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153 #define ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */
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154 #define ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
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155 #define ID_DIR (1 << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */
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157 /* bit field of IF message control register */
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158 #define NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */
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159 #define MLST (1 << 14) /* 1 indicates a message loss. */
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160 #define INTP (1 << 13) /* 1 indicates message object is an interrupt source */
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161 #define UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */
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162 #define TXIE (1 << 11) /* 1 is TX interrupt enabled */
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163 #define RXIE (1 << 10) /* 1 is RX interrupt enabled */
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166 #define RMTEN (1 << 9) /* 1 is remote frame enabled */
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171 #define TXRQ (1 << 8) /* 1 is TxRqst enabled */
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172 #define EOB (1 << 7) /* End of buffer, always write to 1 */
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173 #define DLC 0x000F /* bit mask for DLC */
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175 #define ID_STD_MASK 0x07FF
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176 #define ID_EXT_MASK 0x1FFFFFFF
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177 #define DLC_MASK 0x0F
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179 /* Private Variables ---------------------------------------------------------- */
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180 /* Statistics of all the interrupts */
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181 /* Buss off status counter */
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182 volatile uint32_t BOffCnt = 0;
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183 /* Warning status counter. At least one of the error counters
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184 in the EML has reached the error warning limit of 96 */
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185 volatile uint32_t EWarnCnt = 0;
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186 /* More than 5 equal bits in a sequence in received message */
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187 volatile uint32_t StuffErrCnt = 0;
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188 /* Wrong format of fixed format part of a received frame */
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189 volatile uint32_t FormErrCnt = 0;
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190 /* Transmitted message not acknowledged. */
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191 volatile uint32_t AckErrCnt = 0;
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192 /* Send a HIGH/recessive level, but monitored LOW/dominant */
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193 volatile uint32_t Bit1ErrCnt = 0;
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194 /* Send a LOW/dominant level, but monitored HIGH/recessive */
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195 volatile uint32_t Bit0ErrCnt = 0;
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196 /* The CRC checksum was incorrect in the message received */
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197 volatile uint32_t CRCErrCnt = 0;
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198 /* Message object new data error counter */
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199 volatile uint32_t ND1ErrCnt = 0;
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201 MSG_CB TX_cb, RX_cb;
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203 message_object can_buff[CAN_MSG_OBJ_MAX];
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204 message_object recv_buff;
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207 uint32_t CANStatusLog[100];
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208 uint32_t CANStatusLogCount = 0;
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212 //uint32_t CAN_IF_Read(uint32_t reg,uint32_t IFsel){
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213 // if(IFsel == IF1){
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214 // return (LPC_C_CAN0->IF1_reg);
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216 // return (LPC_C_CAN0->IF2_reg);
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219 //void CAN_IF_Write(uint32_t reg, uint32_t IFsel,uint32_t val){
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220 // if(IFsel == IF1){
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221 // (LPC_C_CAN0->IF1_reg=val);
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223 // (LPC_C_CAN0->IF2_reg=val);
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227 ///* Macro for writing IF to specific RAM message object */
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228 //void CAN_IF_readBuf(uint32_t IFsel,uint32_t msg){
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229 // if(IFsel == IF1){
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230 // LPC_C_CAN0->IF1_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
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231 // LPC_C_CAN0->IF1_CMDREQ=msg;
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232 // while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY );
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234 // LPC_C_CAN0->IF2_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
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235 // LPC_C_CAN0->IF2_CMDREQ=msg;
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236 // while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY );
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241 ///* Macro for reading specific RAM message object to IF */
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242 //void CAN_IF_writeBuf(uint32_t IFsel,uint32_t msg){
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243 // if(IFsel == IF1){
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244 // LPC_C_CAN0->IF1_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
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245 // LPC_C_CAN0->IF1_CMDREQ=msg;
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246 // while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY );
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248 // LPC_C_CAN0->IF2_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
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249 // LPC_C_CAN0->IF2_CMDREQ=msg;
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250 // while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY );
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255 /*********************************************************************//**
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256 * @brief Handle valid received message
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257 * @param[in] msg_no Message Object number
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259 **********************************************************************/
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260 void CAN_RxInt_MessageProcess( uint8_t msg_no )
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264 uint32_t reg1, reg2;
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266 /* Import message object to IF2 */
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267 CAN_IF_readBuf(IF2, msg_no); /* Read the message into the IF registers */
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269 p_add = (uint32_t *)&recv_buff;
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271 if( CAN_IF_Read(ARB2, IF2) & ID_MTD ) /* bit 28-0 is 29 bit extended frame */
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273 /* mask off MsgVal and Dir */
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274 reg1 = CAN_IF_Read(ARB1, IF2);
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275 reg2 = CAN_IF_Read(ARB2, IF2);
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276 msg_id = (reg1|(reg2<<16));
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280 /* bit 28-18 is 11-bit standard frame */
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281 msg_id = (CAN_IF_Read(ARB2, IF2) &0x1FFF) >> 2;
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285 p_add[1] = CAN_IF_Read(MCTRL, IF2) & 0x000F; /* Get Msg Obj Data length */
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286 p_add[2] = (CAN_IF_Read(DA2, IF2)<<16) | CAN_IF_Read(DA1, IF2);
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287 p_add[3] = (CAN_IF_Read(DB2, IF2)<<16) | CAN_IF_Read(DB1, IF2);
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289 /* Clear interrupt pending bit */
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290 CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX);
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291 /* Save changes to message RAM */
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292 CAN_IF_writeBuf(IF2, msg_no);
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296 /*********************************************************************//**
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297 * @brief Handle valid transmit message
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298 * @param[in] msg_no Message Object number
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300 **********************************************************************/
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301 void CAN_TxInt_MessageProcess( uint8_t msg_no )
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303 /* Clear interrupt pending bit */
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304 CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX);
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305 /* Save changes to message RAM */
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306 CAN_IF_writeBuf(IF2,msg_no);
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310 /*********************************************************************//**
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311 * @brief CAN interrupt handler
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314 **********************************************************************/
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315 volatile uint32_t nd_tmp;
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316 void CAN_IRQHandler(void)
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318 uint32_t canstat = 0;
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319 uint32_t can_int, msg_no;
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321 while ( (can_int = LPC_C_CAN0->INT) != 0 ) /* While interrupt is pending */
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323 canstat = LPC_C_CAN0->STAT; /* Read CAN status register */
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325 if ( can_int & CAN_STATUS_INTERRUPT )
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327 /* Passive state monitored frequently in main. */
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329 if ( canstat & STAT_EWARN )
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334 if ( canstat & STAT_BOFF )
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340 switch (canstat&STAT_LEC) /* LEC Last Error Code (Type of the last error to occur on the CAN bus) */
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366 /* Clear all warning/error states except RXOK/TXOK */
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367 LPC_C_CAN0->STAT &= STAT_RXOK|STAT_TXOK;
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371 if ( (canstat & STAT_LEC) == 0 ) /* NO ERROR */
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373 msg_no = can_int & 0x7FFF;
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374 if((msg_no >= 1 ) && (msg_no <= 16))
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376 LPC_C_CAN0->STAT &= ~STAT_RXOK;
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377 /* Check if message number is correct by reading NEWDAT registers.
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378 By reading out the NEWDAT bits, the CPU can check for which Message
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379 Object the data portion was updated
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380 Only first 16 message object used for receive : only use ND1 */
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381 if((1<<(msg_no-1)) != LPC_C_CAN0->ND1)
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383 /* message object does not contain new data! */
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387 CAN_RxInt_MessageProcess(msg_no);
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392 LPC_C_CAN0->STAT &= ~STAT_TXOK;
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393 CAN_TxInt_MessageProcess(msg_no);
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402 /*********************************************************************//**
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403 * @brief Initialize CAN peripheral
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404 * @param[in] BitClk CAN bit clock setting
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405 * @param[in] ClkDiv CAN bit clock setting
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406 * @param[in] Tx_cb point to call-back function when transmitted
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407 * @param[in] Rx_cb point to call-back function when received
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409 **********************************************************************/
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410 void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb)
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415 if ( !(LPC_C_CAN0->CNTL & CTRL_INIT) )
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417 /* If it's in normal operation already, stop it, reconfigure
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418 everything first, then restart. */
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419 LPC_C_CAN0->CNTL |= CTRL_INIT; /* Default state */
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422 LPC_C_CAN0->CLKDIV = ClkDiv; /* Divider for CAN VPB3 clock */
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423 LPC_C_CAN0->CNTL |= CTRL_CCE; /* Start configuring bit timing */
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424 LPC_C_CAN0->BT = BitClk;
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425 LPC_C_CAN0->BRPE = 0x0000;
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426 LPC_C_CAN0->CNTL &= ~CTRL_CCE; /* Stop configuring bit timing */
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428 LPC_C_CAN0->CNTL &= ~CTRL_INIT; /* Initialization finished, normal operation now. */
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429 while ( LPC_C_CAN0->CNTL & CTRL_INIT );
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431 /* By default, auto TX is enabled, enable all related interrupts */
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432 LPC_C_CAN0->CNTL |= (CTRL_IE|CTRL_SIE|CTRL_EIE);
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436 /*********************************************************************//**
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437 * @brief Send a message to the CAN port
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438 * @param[in] msg_no message object number
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439 * @param[in] msg_ptr msg buffer pointer
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441 **********************************************************************/
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442 void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr )
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444 uint32_t tx_id, Length;
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446 if(msg_ptr == NULL) return;
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448 /* first is the ID, second is length, the next four are data */
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449 tx_id = *msg_ptr++;
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450 Length = *msg_ptr++;
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452 if(Length>CAN_DLC_MAX)Length = CAN_DLC_MAX;
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453 CAN_IF_Write(MCTRL, IF1, UMSK|TXIE|TXRQ|EOB|RMTEN|(Length & DLC_MASK));
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454 CAN_IF_Write(DA1, IF1, *msg_ptr); /* Lower two bytes of message pointer */
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455 CAN_IF_Write(DA2, IF1, (*msg_ptr++)>>16); /* Upper two bytes of message pointer */
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456 CAN_IF_Write(DB1, IF1, *msg_ptr); /* Lower two bytes of message pointer */
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457 CAN_IF_Write(DB2, IF1, (*msg_ptr)>>16); /* Upper two bytes of message pointer */
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459 /* Configure arbitration */
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460 if(!(tx_id & (0x1<<30))) /* bit 30 is 0, standard frame */
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462 /* Mxtd: 0, Mdir: 1, Mask is 0x7FF */
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463 CAN_IF_Write(MSK2, IF1, MASK_MDIR | (ID_STD_MASK << 2));
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464 CAN_IF_Write(MSK1, IF1, 0x0000);
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466 /* MsgVal: 1, Mtd: 0, Dir: 1, ID = 0x200 */
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467 CAN_IF_Write(ARB1, IF1, 0x0000);
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468 CAN_IF_Write(ARB2, IF1, ID_MVAL| ID_DIR | (tx_id << 2));
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470 else /* Extended frame */
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472 /* Mxtd: 1, Mdir: 1, Mask is 0x7FF */
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473 CAN_IF_Write(MSK2, IF1, MASK_MXTD | MASK_MDIR | (ID_EXT_MASK >> 16));
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474 CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0x0000FFFF);
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476 /* MsgVal: 1, Mtd: 1, Dir: 1, ID = 0x200000 */
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477 CAN_IF_Write(ARB1, IF1, tx_id & 0x0000FFFF);
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478 CAN_IF_Write(ARB2, IF1, ID_MVAL|ID_MTD | ID_DIR | (tx_id >> 16));
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481 /* Write changes to message RAM */
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482 CAN_IF_writeBuf(IF1, msg_no);
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487 /*********************************************************************//**
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488 * @brief Listen for a message on CAN bus
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489 * @param[in] msg_no message object number
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490 * @param[in] msg_ptr msg buffer pointer
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491 * @param[in] RemoteEnable Enable/disable remote frame support, should be:
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495 **********************************************************************/
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496 void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable)
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498 uint32_t rx_id = *msg_ptr;
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499 uint32_t rmten = 0;
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503 if(!(rx_id & (0x1<<30))){ /* standard frame */
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505 /* Mxtd: 0, Mdir: 0, Mask is 0x7FF */
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506 CAN_IF_Write(MSK1, IF1, 0x0000);
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507 CAN_IF_Write(MSK2, IF1, ID_STD_MASK << 2);
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508 /* MsgVal: 1, Mtd: 0, Dir: 0 */
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509 CAN_IF_Write(ARB1, IF1, 0x0000);
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510 CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX);
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511 CAN_IF_Write(DA1, IF1, 0x0000);
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512 CAN_IF_Write(DA2, IF1, 0x0000);
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513 CAN_IF_Write(DB1, IF1, 0x0000);
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514 CAN_IF_Write(DB2, IF1, 0x0000);
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515 CAN_IF_Write(ARB2, IF1, ID_MVAL | ((rx_id) << 2));
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516 /* Transfer data to message RAM */
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517 CAN_IF_writeBuf(IF1, msg_no);
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521 rx_id &= (0x1<<30)-1 ; /* Mask ID bit */
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522 /* Mxtd: 1, Mdir: 0, Mask is 0x1FFFFFFF */
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523 CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0xFFFF);
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524 CAN_IF_Write(MSK2, IF1, MASK_MXTD | (ID_EXT_MASK >> 16));
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525 /* MsgVal: 1, Mtd: 1, Dir: 0 */
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526 CAN_IF_Write(ARB1, IF1, (rx_id) & 0xFFFF);
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527 CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX);
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528 CAN_IF_Write(DA1, IF1, 0x0000);
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529 CAN_IF_Write(DA2, IF1, 0x0000);
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530 CAN_IF_Write(DB1, IF1, 0x0000);
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531 CAN_IF_Write(DB2, IF1, 0x0000);
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532 CAN_IF_Write(ARB2, IF1, ID_MVAL | ID_MTD | ((rx_id) >> 16));
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533 /* Transfer data to message RAM */
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534 CAN_IF_writeBuf(IF1, msg_no);
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539 /*********************************************************************//**
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540 * @brief Read a message from Message RAM to buffer
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541 * @param[in] msg_no message object number
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542 * @param[in] buff msg buffer pointer
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544 **********************************************************************/
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545 void CAN_ReadMsg(uint32_t msg_no, message_object* buff){
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547 buff->id = recv_buff.id;
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548 buff->dlc = recv_buff.dlc;
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549 if(recv_buff.dlc>CAN_DLC_MAX) recv_buff.dlc = CAN_DLC_MAX;
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550 for(i=0;i<recv_buff.dlc;i++)
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551 buff->data[i] = recv_buff.data[i];
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559 /* --------------------------------- End Of File ------------------------------ */
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